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electronic devices 
and circuit theory 



ROBERT L. BOYLESTAD LOUIS NASHELSKY 




SIGNIFICANT EQUATIONS 



1 Semiconductor Diodes W = QV, 1 eV = 1.6 X 10 l9 J, I D = /, - 1), V T = kT/q, T K = T c + 213°, 

k= 1.38 X 10“ 23 J/K, V K = 0.7 V (Si), V K = 0.3 V(Ge), V K = 1.2V(GaAs), R D = V D /I D , r d = 26mV/I D , = A V d /AI d \ pttopt , 
Pd = V D I D , T c = (A Vz/Vd/V! - T 0 ) X 100%/°C 

2 Diode Applications Silicon: V K = 0.7 V, germanium: V K = 0.3 V, GaAs: V K = 1.2 Y; half-wave: V dc = 0.318Y m ; 
full-wave: V dc = 0.636V m 

3 Bipolar Junction Transistors I E = I c + I B , 7 c = 7 c majority + 7 co minority , 7 c = 7 & V BE = 0.7 V, o dc = I C /I E , 7 c = « 7 e + 7 cbo> 
a ac = Mc/M e ,Ic E o = r C Bo/(\ ~ a),p dc = I C /I B , fac = A 7 cMt, « = W + l).j8 = «/(l - a), 7 c = fa 8^ fa = (j3 + 1)/ B> 

^Gnax V CfJc 

4 DC Biasing— BJTs In general: = 0.7 V, 7 C = / £ , / c = (3 I B ; fixed-bias: I P , = (V cc - V BE )/R B ,V CE = V cc - 1 C R C , 

7 c sat = V cc / R c, emitter-stabilized: I B = (V cc ~ V BE )/(R B + (fi + 1 )R E ), R, = (fi + 1 )R e , V ce = V cc - I C (R C + R E ), 

7 c sat = VccARc + r eY voltage-divider: exact: /? Th = R \ ll^ Gh = R iVccK R \ + R 2 \fa = (Uh “ v be)^ r 'y\x + (j3 + 1 )R E ), 
v ce = V C c ~ 7 c ( R c + r e)> approximate: jiR E > 10/G, V B = R 2 V C c/( r i + R 2 ), v e = V B - v be- ! c = fa = V E /R E ; voltage-feedback: 
hi = (Vcc - V BE )/(R B + [3(R C + R E )); common-base: 1„ = (V EE - V BE )/R E , switching transistors: t on = t r + t d , t oS = t s + t f ; 
stability: S(I C o) — A/ G /A/ GG ; fixed-bias: S(J C o) = /3 + 1; emitter-bias: S(I C0 ) = (/3 4- 1)(1 + R B /R E )/(\ + p 4- R B /R E )\ 
voltage-divider: S(I C0 ) = (P + 1)(1 + W^)/(l + P + feedback-bias: 5(/ co ) = (j3 + 1)(1 + V^c)/(1 + P + 

S(Vbe) = A/ G /AVg#; fixed-bias: S(V BE ) = ~/3/R B ; emitter-bias: S(V BE ) = -p/(R B + Q3 + l)R E )', voltage-divider: S(V BE ) = 

-/3/(R Th + 03 + 1)^); feedback bias: 5 (Vb £ ) = + (j8 + l)fl c ), SQ3) = A/ C /Aj8; fixed-bias: 5(/3) = / Cl /ft; 

emitter-bias: 5(j8) = / Cl (l + + & + Rb/Re))\ voltage-divider: 5(j8) = / Cl (l + R Th /R E )/(Pi(l + & + ^Th/^)); 

feedback-bias: 5(j8) = / Cl (l + ^c)/03i(l + ft + ^c)). A/ c = 5(/ C0 ) A/ co + AY fi£ + S((3) A (3 

5 BJT AC Analysis r e = 26 mV// £ ; CE fixed-bias: = (3r e , Z 0 = R c , A v = —R c /r e \ voltage-divider bias: Z; = /?] || /? 2 1| fir e , Z () = R c , 

A v = -R c /r e \ CE emitter-bias: Z t = R B \\/3R E ,Z 0 = R E ,A V = —R C /R E ; emitter-follower: Z t = R B \\l3R E ,Z 0 = r e ,A v = 1; 
common-base: Z t = R E \\r e ,Z Q = R&A V = Rc/r e \ collector feedback: Z t = r e /(l/p + R C /R F ),Z 0 = R c \\R f ,A v = —R c /r e \ collector 
dc feedback: Z t = R Fl \\/3r e ,Z 0 = R c || Rp 2 ,A v = — (/? F2 || Rc)/r e \ effect of load impedance: A v = R e A Vnl /(R e + R 0 ),Ai = —A v Zi/R l \ 
effect of source impedance: V t = RiV s /(Ri + R s ), A Vs = R(A Vnl / (R t + R s ), I s = V S /{R S + R t )\ combined effect of load and source 
impedance: A v = R l A Vnl /(R l + R a ), A Vg = ( R^ + R S ))(R L /(R L + R q Mv nV = -A v Ri/R L , , A ig = -A Vg (R s + R$/R L ; cascode 
connection: A v = A Vl A V2 ; Darlington connection: p D = jSp8 2 ; emitter-follower configuration: I B = ( V C c ~ + PdRe)> 

Ic = h = Pr>hh Z, = R B \\PiP 2 R E ,Ai = (3 D R B /(R B + (3 D R E ),A V = 1 ,Z 0 = r e J F _ + r ( .,; basic amplifier configuration: Z, = R l \\R 2 \\ZI, 
Z/ = j8i(r ei + P 2 r e2 ),Ai = /3 d ( r i\\ r 2)/( r i\\ r 2 + Z/),A V = p D R c /z;,Z 0 = R c \\r 02 , feedback pair: I Bl = ( V cc - V BEl )/(R B + fa /3 2 R C ), 
Z, = R B \\Z-,Z[ = + p\faR c ,Ai = -PifaR B /( R B + Pifa R c) A v = fa R c/( r e + fa R c) = 1 >Z 0 = r e Jfa. 

6 Field-Effect Transistors I G = 0 A, I D = I DSS (1 - VgVU) 2 . 7 d = / S Tcs = ^p(1 “ VWW- h> = fass / 4 (if F GS = k P /2), 

In = bss/ 2 (if F cs = 0.3 k P ), = y DS / D , r d = r 0 /(l - y GS /F P ) 2 ; MOSFET: / D = k(V GS - y r ) 2 ( k = l D « m) /(Vcs( 0 ») ~ V T f 

1 FET Biasing Fixed-bias: = ~VgG’ Vds = Vdd ~ IdRd’i self-bias: Vq B = —IpRs, V D s = V DD — I F iRs + ^d)» = 

voltage-divider: V G = R 2 V D d/(R i + ^ 2 )^ - / G /? s , = V DD — Io(Ro + R$)\ common-gate configuration: V GS = V S s ~ IdRs> 

Vds = Vdd + Vss ~ Id(Rd + Rs)> special case: Vgs q = 0 Y: I Iq = loss, Vds = Vdd ~ IdRd> Vd = Vds> Vs = 0 V. enhancement-type 
MOSFET: I D = k(V GS - V GS ( Th y) 2 , k = lD(on)/(V G S(on) ~ ^G5(Th)) 2 » feedback bias: V DS = V GS , V GS = V DE > - IqRd\ voltage-divider: 

Vq = R^Ydd/ (R\ + Rt)i V G s — Y g - I d R s ; universal curve: m = \V P \/I DSS R S , M = m X V g /\V p \,Vg = RiYddKRi + Ri) 



8 FET Amplifiers g m yj- s Alj)/AV GB , g m Q j | V P | , 8mo(^ V G s/V P ), g m g m o V/Id/Idss* r d ^-/yos 

A V ds /AI d I y G5=cons t ant ; fixed-bias: Z, = R G , Z 0 = R D , A v = ~g m R D ; self-bias (bypassed Rs): Z t = R G , Z 0 = R D , A v = ~g m R D ; self-bias 
(unbypassed Rs): Z t = R G ,Z Q = R D , A v = — g m /? D /( l + g m R s )', voltage-divider bias: Z t = R\ || R 2 , Z a = R D , A v = — source follower: 
Z; = R g ,Z 0 = R s || l/g m ,A v m g m R s /( 1 + g m R s ) m , common-gate: Z,- = R s \\l/g m ,Z 0 = R D , A v = g m R D ; enhancement- type MOSFETs: 
g m = 2k(V GSQ - V G s (Th) ); drain-feedback configuration: Z,- = R F /( 1 + g m R D ),Z 0 = R D ,A V = ~g m R D \ voltage-divider bias: Z ; = R x || R 2 , 
Z 0 : Rd-> Ay ~~ 8 mRd- 



9 BJT and JFET Frequency Response lo g e a = 2.3 log 10 «, log 10 l — 0, logi oa/b = logi 0 a — log 10 ^, log 10 l/& — — logi 0 b, 
loglO ab = lo gi 0 a + logi 0 b, G dB = 10 log 10 P 2 /P 11 G dBm = lOlogio^/l 1 600 n ^ ^dB ~ 201og 10 V 2 /V 1 , 

G d B T = G dB] + G dBl + • • • + G dBn P OHpF = 0.5 P 0m . d , BW = /1 - / 2 ; low frequency (BJT): f Lg = 1/2t t(R s + R/)C 5 , 

A c = 1/277 (7? c + R L )C 0 f LE = l/2irR e C E ,R e = R e \\(R' s /P + r e ), R' s = /? V |K|| R 2 , FET: f L( , = 1/2t 7 (7? sig + 7?,)C G , 

Il c = \/2ir(Ro + R L )Cc,fL s = l/2TTR eq C s ,R eq = R s \\l/gmKd = co ft); Miller effect: C M . = (1 - A v )C /s C Mg = (1 - l/A v )C /; 
high frequency (BJT): f H . = I /IttR-^.C,, R [h . = tfjT?! ||7? 2 ||7? ; , C,- = C w . + C be + (1 - A v )C bc , f Hg = 1/2-7 77? Th< C 0 , 

Rjb 0 = II /'’r II >'(r C„ = C Wg + C ce + C Mg , fp = l/2Trf3 nM r e (C be + C bc ), f T = P mK \ ffi- FET: f H . = 1/277 /? Th; Q, /? Th( . = /? sig ||/? G , 

Q = Cn- ; + C, s + C M , C M . = (1 — A v )C gd f Hg = 1/277 Rj bg C 0 , R^ = /Jol/Jil r d , C a = C Wg + C ds + C Mg , C M(J = (1 - 1 /A v )C gd , 
multistage: /{ = f] / \/ 2 1 — I , / 2 = (V2 1 /” — l)/ 2 ; square-wave testing: f Hj = 0.35/f r , % tilt = P% = ((V — V')/V) X 100%, 

f Lo = (PML 

10 Operational Amplifiers CMRR = A d /A c ; CMRR(log) = 20 log 10 (A^/AJ; constant-gain multiplier: V 0 /V\ = - Rf/R\ ; 
noninverting amplifier: V 0 /Vi = 1 + Rf/R\\ unity follower: V Q = V\\ summing amplifier: V Q = —[(Ry/R 1 )V 1 + (Rf/R 2 )V 2 + (Rf/R 2 )V 3 \; 
integrator: v 0 (t) = — (\/R\C{) fvidt 

11 Op-Amp Applications Constant-gain multiplier: A = — Rf/R\\ noninverting: A = 1 + Rf/R\. voltage summing: 

V 0 = ~[(Rf/R\)V\ + (Rf/R 2 )V 2 + (Rf/R 3 )V 3 ]; high-pass active filter: f oL = 1/2 ttR\C\\ low-pass active filter: f oH = 1/2 ttRiCi 



12 Power Amplifiers 

Power in: P t = V c dcQ 

power out: P a = V CE I C = l}R c = V} :E / R c rms 

= V ce I c /2 = Uc/2)R c = V 2 CE I(2R C ) peak 
= V CE I C / 8 = (ll/m C = VcfJCZRc) peak-to-peak 

efficiency: %rj = (P Q /Pj) X 100%; maximum efficiency: Class A, series-fed = 25%; Class A, transformer-coupled = 50%; Class B, 
push-pull = 78.5%; transformer relations: V 2 /V\ = N 2 /N\ = I\/I 2 ,R 2 = (N 2 /N\) 2 R\\ power output: P Q = [( Vqe ~ Vce ■ ) 

(/c max - /c min )]/8; class B power amplifier: P t = V cc [(2/7r)/ peak ] ; P 0 = V L 2 (peak)/(2R L ); % V = (tt/ 4)[ V L (peak)/y cc ] Tw.; 
Pq = P 2 q/2- (Pi — P Q )/ 2; maximum P 0 = Vc C /2R L \ maximum P t = 2 Vc C /ttR l \ maximum P 2 q = 2 Vcc/^Rp, % total harmonic 
distortion (% THD) = V D 2 + D 2 + D\ + • • • X 100%; heat- sink: Tj — Pd^ja + T A ,0 JA = 40°C/W (free air); 

Pd = (Pj ~ Ta)/(0jc + Ocs + Osa) 



13 Linear-Digital ICs Ladder network: V 0 = [(Dq X 2° + D\ X 2 1 + D 2 X 2 2 + • • • + D n X 2 n )/2 n ]V re f ; 

555 oscillator: / = 1.44(R A + 2R 5 )C; 555 monostable: r high = 1.1R A C; VCO :f a = (2/R l C l )[(V + - V c )/V + ]; phase- 
locked loop (PLL): /„ = 0.3/^QJi. = ±8 f 0 /V,f c = ±fl/277)V277/ L /(3.6 X 10 3 )C 2 



14 Feedback and Oscillator Circuits Ay = A/(l + /3A); series feedback; Zy = Z ; (l + j8A); shunt feedback: Zy = Z £ -/(l + /3A); 
voltage feedback: Z 0 y = Z 0 /(l + (3A ); current feedback; Z 0 y = Z 0 (l + (3A ); gain stability: JAy/Ay = l/(|l + ^8A|)(dA/A); oscillator; 

/3A = 1; phase shift:/ = 1/27tRCV6, /3 = 1/29, A > 29; FET phase shift: \A\ = g m R^RL = RD r d/(RD + r d )i transistor phase shift: 
/= (I /2ttRC)\\ j\/(i + 4(/? c //?)l, h fe > 23 + 2%R C /R) + 4(/f//? c ); Wien bridge: /f 3 //? 4 = /?,/W 2 + C 2 /C h f a = 1 /2-irVRiCiR 2 C 2 ; 
tuned: f a = 1/277 VLC eq , C eq = CjQ/CQ + C 2 ), Hartley: L eq = L x + L 2 + 2 M, f a = 1/277 VL eq C 



15 Power Supplies (Voltage Regulators) Filters: r = V r (rms)/V dc X 100%, V.R. = (V NL — V FL )/V FL X 100%, F d c = v m - v r (p-p)/ 2 , 
V r (rms) = K(P-P)/2V3, y r (rms) = (/ dc /4V3)(y dc /y m ); full-wave, light load y r (rms) = 2.4/ dc /C, y dc = V m - 4.177 dc /C, r = 
(2.4/ dc Cy dc ) X 100% = 2A/R l C X 100%, / peak = T/T x X 7 dc ; RC filter: V dc = R L V dc /(R + R L ),X C = 2.653/C(half-wave), X c = 
1.326/C (full-wave), y/(rms) = (X c /Vt ? 2 + *|); regulators: 77? = (7 WL - I FL )/I FL X 100%, y L = V z (l + R\/R 2 ), V a = 

Kef (1 + R 2 /R 1 ) + 4dj^2 

16 Other Two-Terminal Devices Varactor diode: C r = C(0)/(1 + V,./V T \)", TC ( . = ( XC/C 0 (T\ — 7q)) X 100%; photodiode: 

W= Hf,\ = v/f, 1 lm = 1.496 X 10 ~ 10 W, 1 A = 10~ 10 m, 1 fc = 1 lm/ft 2 = 1.609 X 10“ 9 W/m 2 

17 pnpn and Other Devices Diac: V BK[ = V BKl ± 0.1 V BRl UJT: R BB = (R B[ + Rb 2 )\i e =o, Vr Bi = vV BB \, l =(h 

V = r bA R B\ + R B 2 )\i,-=<h Vp = 7 iV BB + V D - phototransistor: 7 C = h fe I x \ PUT: 77 = R Bi /(Rb 1 + r b 2 ^ v p = V v bb + v d 



Electronic 
Devices and 
Circuit Theory 



Eleventh Edition 

Robert L. Boylestad 
Louis Nashelsky 



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Library of Congress Cataloging-in-Publication Data 

Boylestad, Robert L. 

Electronic devices and circuit theory / Robert L. Boylestad, Louis Nashelsky. — 1 1th ed. 



p. cm. 

ISBN 978-0-13-262226-4 

1. Electronic circuits. 2. Electronic apparatus and appliances. I. Nashelsky, Louis. II. Title. 
TK7867.B66 2013 
621.3815— dc23 



2011052885 



10 987654321 




ISBN 10: 0-13-262226-2 

ISBN 13: 978-0-13-262226-4 





DEDICATION 



To Else Marie, Alison and Mark, Eric and Rachel, Stacey and Jonathan, 
and our eight granddaughters: Kelcy, Morgan, Codie, Samantha, Lindsey, 

Britt, Skylar, and Aspen. 

To Katrin, Kira and Thomas, Larren and Patricia, and our six grandsons: 
Justin, Brendan, Owen, Tyler, Colin, and Dillon. 



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PREFACE 



The preparation of the preface for the 11th edition resulted in a bit of reflection on the 40 
years since the first edition was published in 1972 by two young educators eager to test 
their ability to improve on the available literature on electronic devices. Although one may 
prefer the term semiconductor devices rather than electronic devices, the first edition was 
almost exclusively a survey of vacuum-tube devices — a subject without a single section in 
the new Table of Contents. The change from tubes to predominantly semiconductor devices 
took almost five editions, but today it is simply referenced in some sections. It is interest- 
ing, however, that when field-effect transistor (FET) devices surfaced in earnest, a number 
of the analysis techniques used for tubes could be applied because of the similarities in the 
ac equivalent models of each device. 

We are often asked about the revision process and how the content of a new edition is 
defined. In some cases, it is quite obvious that the computer software has been updated, 
and the changes in application of the packages must be spelled out in detail. This text 
was the first to emphasize the use of computer software packages and provided a level 
of detail unavailable in other texts. With each new version of a software package, we 
have found that the supporting literature may still be in production, or the manuals lack 
the detail for new users of these packages. Sufficient detail in this text ensures that a 
student can apply each of the software packages covered without additional instruc- 
tional material. 

The next requirement with any new edition is the need to update the content reflecting 
changes in the available devices and in the characteristics of commercial devices. This 
can require extensive research in each area, followed by decisions regarding depth of 
coverage and whether the listed improvements in response are valid and deserve recog- 
nition. The classroom experience is probably one of the most important resources for 
defining areas that need expansion, deletion, or revision. The feedback from students 
results in marked-up copies of our texts with inserts creating a mushrooming copy of the 
material. Next, there is the input from our peers, faculty at other institutions using the 
text, and, of course, reviewers chosen by Pearson Education to review the text. One 
source of change that is less obvious is a simple rereading of the material following the 
passing of the years since the last edition. Rereading often reveals material that can be 
improved, deleted, or expanded. 

For this revision, the number of changes far outweighs our original expectations. How- 
ever, for someone who has used previous editions of the text, the changes will probably 
be less obvious. However, major sections have been moved and expanded, some 100-plus 
problems have been added, new devices have been introduced, the number of applications 
has been increased, and new material on recent developments has been added through- 
out the text. We believe that the current edition is a significant improvement over the 
previous editions. 

As instructors, we are all well aware of the importance of a high level of accuracy 
required for a text of this kind. There is nothing more frustrating for a student than to 
work a problem over from many different angles and still find that the answer differs 
from the solution at the back of the text or that the problem seems undoable. We were 
pleased to find that there were fewer than half a dozen errors or misprints reported since 



Vi PREFACE 



the last edition. When you consider the number of examples and problems in the text 
along with the length of the text material, this statistic clearly suggests that the text is as 
error-free as possible. Any contributions from users to this list were quickly acknowl- 
edged, and the sources were thanked for taking the time to send the changes to the pub- 
lisher and to us. 

Although the current edition now reflects all the changes we feel it should have, we 
expect that a revised edition will be required somewhere down the line. We invite you to 
respond to this edition so that we can start developing a package of ideas and thoughts that 
will help us improve the content for the next edition. We promise a quick response to your 
comments, whether positive or negative. 

NEW TO THIS EDITION 

• Throughout the chapters, there are extensive changes in the problem sections. Over 100 
new problems have been added, and a significant number of changes have been made to 
the existing problems. 

• A significant number of computer programs were all rerun and the descriptions updated 
to include the effects of using OrCAD version 16.3 and Multisim version 11.1. In addi- 
tion, the introductory chapters are now assuming a broader understanding of computer 
methods, resulting in a revised introduction to the two programs. 

• Throughout the text, photos and biographies of important contributors have been added. 
Included among these are Sidney Darlington, Walter Schottky, Harry Nyquist, Edwin 
Colpitts, and Ralph Hartley. 

• New sections were added throughout the text. There is now a discussion on the impact 
of combined dc and ac sources on diode networks, of multiple BJT networks, VMOS 
and UMOS power FETs, Early voltage, frequency impact on the basic elements, 
effect of R s on an amplifier’s frequency response, gain-bandwidth product, and a 
number of other topics. 

• A number of sections were completely rewritten due to reviewers’ comments or 
changing priorities. Some of the areas revised include bias stabilization, current 
sources, feedback in the dc and ac modes, mobility factors in diode and transistor 
response, transition and diffusion capacitive effects in diodes and transistor response 
characteristics, reverse- saturation current, breakdown regions (cause and effect), and 
the hybrid model. 

• In addition to the revision of numerous sections described above, there are a number of 
sections that have been expanded to respond to changes in priorities for a text of this 
kind. The section on solar cells now includes a detailed examination of the materials 
employed, additional response curves, and a number of new practical applications. The 
coverage of the Darlington effect was totally rewritten and expanded to include detailed 
examination of the emitter-follower and collector gain configurations. The coverage of 
transistors now includes details on the cross-bar latch transistor and carbon nanotubes. 
The discussion of LEDs includes an expanded discussion of the materials employed, 
comparisons to today’s other lighting options, and examples of the products defining 
the future of this important semiconductor device. The data sheets commonly included 
in a text of this type are now discussed in detail to ensure a well-established link when 
the student enters the industrial community. 

• Updated material appears throughout the text in the form of photos, artwork, data 
sheets, and so forth, to ensure that the devices included reflect the components avail- 
able today with the characteristics that have changed so rapidly in recent years. In 
addition, the parameters associated with the content and all the example problems are 
more in line with the device characteristics available today. Some devices, no longer 
available or used very infrequently, were dropped to ensure proper emphasis on the 
current trends. 

• There are a number of important organizational changes throughout the text to ensure 
the best sequence of coverage in the learning process. This is readily apparent in the 
early dc chapters on diodes and transistors, in the discussion of current gain in the ac 
chapters for BJTs and JFETs, in the Darlington section, and in the frequency response 
chapters. It is particularly obvious in Chapter 16, where topics were dropped and the 
order of sections changed dramatically. 



INSTRUCTOR SUPPLEMENTS 



PREFACE 



vii 



To download the supplements listed below, please visit: http://www.pearsonhighered. 
com/irc and enter “Electronic Devices and Circuit Theory” in the search bar. From there, 
you will be able to register to receive an instructor’s access code. Within 48 hours after 
registering, you will receive a confirming email, including an instructor access code. 
Once you have received your code, return to the site and log on for full instructions on 
how to download the materials you wish to use. 

PowerPoint Presentation-(ISBN 0132783746). This supplement contains all figures 
from the text as well as a new set of lecture notes highlighting important concepts. 

TestGen® Computerized Test Bank-(ISBN 013278372X). This electronic bank of test 
questions can be used to develop customized quizzes, tests, and/or exams. 

Instructor’s Resource Manual-(ISBN 0132783738). This supplement contains the solu- 
tions to the problems in the text and lab manual. 

STUDENT SUPPLEMENTS 

Laboratory Manual-(ISBN 0132622459) . This supplement contains over 35 class-tested 
experiments for students to use to demonstrate their comprehension of course material. 

Companion Website-Student study resources are available at www.pearsonhighered. 
com/boylestad 

ACKNOWLEDGMENTS 

The following individuals supplied new photographs for this edition. 

Sian Cummings International Rectifier Inc. 

Michele Drake Agilent Technologies Inc. 

Edward Eckert Alcatel-Lucent Inc. 

Amy Flores Agilent Technologies Inc. 

Ron Forbes B&K Precision Corporation 
Christopher Frank Siemens AG 
Amber Hall Hewlett-Packard Company 
Jonelle Hester National Semiconductor Inc. 

George Kapczak AT&T Inc. 

Patti Olson Fairchild Semiconductor Inc. 

Jordon Papanier LEDtronics Inc. 

Andrew W. Post Vishay Inc. 

Gilberto Ribeiro Hewlett-Packard Company 
Paul Ross Alcatel-Lucent Inc. 

Craig R. Schmidt Agilent Technologies, Inc. 

Mitch Segal Hewlett-Packard Company 
Jim Simon Agilent Technologies, Inc. 

Debbie Van Velkinburgh Tektronix, Inc. 

Steve West On Semiconductor Inc. 

Marcella Wilhite Agilent Technologies, Inc. 

Stan Williams Hewlett-Packard Company 
J. Joshua Wang Hewlett-Packard Company 



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BRIEF CONTENTS 



v 

CHAPTER 1 : Semiconductor Diodes 1 

CHAPTER 2: Diode Applications 55 

CHAPTER 3: Bipolar Junction Transistors 129 

CHAPTER 4: DC Biasing-BJTs 160 

CHAPTER 5: BJT AC Analysis 253 

CHAPTER 6: Field-Effect Transistors 378 

CHAPTER 7: FET Biasing 422 

CHAPTER 8: FET Amplifiers 481 

CHAPTER 9: BJT and JFET Frequency Response 545 

CHAPTER 1 0: Operational Amplifiers 607 

CHAPTER 1 1 : Op-Amp Applications 653 

CHAPTER 12: Power Amplifiers 683 

CHAPTER 13: Linear-Digital ICs 722 

CHAPTER 14: Feedback and Oscillator Circuits 751 

CHAPTER 15: Power Supplies (Voltage Regulators) 783 

CHAPTER 16: Other Two-Terminal Devices 81 1 

CHAPTER 17: pnpn and Other Devices 841 

Appendix A: Hybrid Parameters-Graphical 

Determinations and Conversion Equations (Exact 

and Approximate) 879 









brief contents Appendix B: Ripple Factor and Voltage Calculations 885 

Appendix C: Charts and Tables 891 

Appendix D: Solutions to Selected 

Odd-Numbered Problems 893 

Index 901 



CONTENTS 



Preface v 

CHAPTER 1 : Semiconductor Diodes 1 

1.1 Introduction 1 

1.2 Semiconductor Materials: Ge, Si, and GaAs 2 

1.3 Covalent Bonding and Intrinsic Materials 3 

1.4 Energy Levels 5 

1.5 n-Type and p-Type Materials 7 

1.6 Semiconductor Diode 10 

1.7 Ideal Versus Practical 20 

1.8 Resistance Levels 21 

1.9 Diode Equivalent Circuits 27 

1.10 Transition and Diffusion Capacitance 30 

1.11 Reverse Recovery Time 31 

1.12 Diode Specification Sheets 32 

1.13 Semiconductor Diode Notation 35 

1.14 Diode Testing 36 

1.15 Zener Diodes 38 

1.16 Light-Emitting Diodes 41 

1.17 Summary 48 

1.18 Computer Analysis 49 

CHAPTER 2: Diode Applications 55 

2.1 Introduction 55 

2.2 Load-Line Analysis 56 

2.3 Series Diode Configurations 61 

2.4 Parallel and Series-Parallel Configurations 67 

2.5 AND/OR Gates 70 

2.6 Sinusoidal Inputs; Half-Wave Rectification 72 

2.7 Full-Wave Rectification 75 

2.8 Clippers 78 

2.9 Clampers 85 

2.10 Networks with a dc and ac Source 88 



Xii CONTENTS 



2.11 Zener Diodes 91 

2.12 Voltage-Multiplier Circuits 98 

2.13 Practical Applications 101 

2.14 Summary 111 

2.15 Computer Analysis 112 

CHAPTER 3: Bipolar Junction Transistors 129 

3.1 Introduction 129 

3.2 Transistor Construction 130 

3.3 Transistor Operation 130 

3.4 Common-Base Configuration 131 

3.5 Common-Emitter Configuration 136 

3.6 Common-Collector Configuration 143 

3.7 Limits of Operation 144 

3.8 Transistor Specification Sheet 145 

3.9 Transistor Testing 149 

3.10 Transistor Casing and Terminal Identification 151 

3.11 Transistor Development 152 

3.12 Summary 154 

3.13 Computer Analysis 155 

CHAPTER 4: DC Biasing-BJTs 160 

4.1 Introduction 160 

4.2 Operating Point 161 

4.3 Fixed-Bias Configuration 163 

4.4 Emitter-Bias Configuration 169 

4.5 Voltage-Divider Bias Configuration 175 

4.6 Collector Feedback Configuration 181 

4.7 Emitter-Follower Configuration 186 

4.8 Common-Base Configuration 187 

4.9 Miscellaneous Bias Configurations 189 

4.10 Summary Table 192 

4.11 Design Operations 194 

4.12 Multiple BJT Networks 199 

4.13 Current Mirrors 205 

4.14 Current Source Circuits 208 

4.15 pnp Transistors 210 

4.16 Transistor Switching Networks 211 

4.17 Troubleshooting Techniques 215 

4.18 Bias Stabilization 217 

4.19 Practical Applications 226 

4.20 Summary 233 

4.21 Computer Analysis 235 



CHAPTER 5: BIT AC Analysis 253 

5.1 Introduction 253 

5.2 Amplification in the AC Domain 253 

5.3 BJT Transistor Modeling 254 

5.4 The r e Transistor Model 257 

5.5 Common-Emitter Fixed-Bias Configuration 262 

5.6 Voltage-Divider Bias 265 

5.7 CE Emitter-Bias Configuration 267 

5.8 Emitter-Follower Configuration 273 

5.9 Common-Base Configuration 277 

5.10 Collector Feedback Configuration 279 

5.11 Collector DC Feedback Configuration 284 

5.12 Effect of R l and R s 286 

5.13 Determining the Current Gain 291 

5.14 Summary Tables 292 

5.15 Two-Port Systems Approach 292 

5.16 Cascaded Systems 300 

5.17 Darlington Connection 305 

5.18 Feedback Pair 314 

5.19 The Hybrid Equivalent Model 319 

5.20 Approximate Hybrid Equivalent Circuit 324 

5.21 Complete Hybrid Equivalent Model 330 

5.22 Hybrid tt Model 337 

5.23 Variations of Transistor Parameters 338 

5.24 Troubleshooting 340 

5.25 Practical Applications 342 

5.26 Summary 349 

5.27 Computer Analysis 352 

CHAPTER 6: Field-Effect Transistors 378 

6.1 Introduction 378 

6.2 Construction and Characteristics of JFETs 379 

6.3 Transfer Characteristics 386 

6.4 Specification Sheets (JFETs) 390 

6.5 Instrumentation 394 

6.6 Important Relationships 395 

6.7 Depletion-Type MOSFET 396 

6.8 Enhancement-Type MOSFET 402 

6.9 MOSFET Handling 409 

6.10 VMOS and UMOS Power and MOSFETs 410 

6.11 CMOS 411 

6.12 MESFETs 412 

6.13 Summary Table 414 



CONTENTS xiii 



xiv 



CONTENTS 



6.14 


Summary 


414 


6.15 


Computer Analysis 


416 


-IAPTER 7: FET Biasing 


422 


7.1 


Introduction 


422 


7.2 


Fixed-Bias Configuration 


423 


7.3 


Self-Bias Configuration 


427 


7.4 


Voltage-Divider Biasing 


431 


7.5 


Common-Gate Configuration 


436 


7.6 


Special Case I/ CSq = 0 V 


439 


7.7 


Depletion-Type MOSFETs 


439 


7.8 


Enhancement-Type MOSFETs 


443 


7.9 


Summary Table 


449 


7.10 


Combination Networks 


449 


7.11 


Design 


452 


7.12 


Troubleshooting 


455 


7.13 


p-Channel FETs 


455 


7.14 


Universal JFET Bias Curve 


458 


7.15 


Practical Applications 


461 


7.16 


Summary 


470 


7.17 


Computer Analysis 


471 


■IAPTER 8: FET Amplifiers 


481 


8.1 


Introduction 


481 


8.2 


JFET Small-Signal Model 


482 


8.3 


Fixed-Bias Configuration 


489 


8.4 


Self-Bias Configuration 


492 


8.5 


Voltage-Divider Configuration 


497 


8.6 


Common-Gate Configuration 


498 


8.7 


Source-Follower (Common-Drain) Configuration 


501 


8.8 


Depletion-Type MOSFETs 


505 


8.9 


Enhancement-Type MOSFETs 


506 


8.10 


E-MOSFET Drain-Feedback Configuration 


507 


8.11 


E-MOSFET Voltage-Divider Configuration 


510 


8.12 


Designing FET Amplifier Networks 


511 


8.13 


Summary Table 


513 


8.14 


Effect of R l and R s , g 


516 


8.15 


Cascade Configuration 


518 


8.16 


Troubleshooting 


521 


8.17 


Practical Applications 


522 


8.18 


Summary 


530 


8.19 


Computer Analysis 


531 



CONTENTS xv 



CHAPTER 9: BIT and IFET Frequency Response 545 



9.1 


Introduction 


545 


9.2 


Logarithms 


545 


9.3 


Decibels 


550 


9.4 


General Frequency Considerations 


554 


9.5 


Normalization Process 


557 


9.6 


Low-Frequency Analysis— Bode Plot 


559 


9.7 


Low-Frequency Response— BJT Amplifier with R L 


564 


9.8 


Impact of R s on the BJT Low-Frequency Response 


568 


9.9 


Low-Frequency Response— FET Amplifier 


571 


9.10 


Miller Effect Capacitance 


574 


9.11 


High-Frequency Response— BJT Amplifier 


576 


9.12 


High-Frequency Response— FET Amplifier 


584 


9.13 


Multistage Frequency Effects 


586 


9.14 


Square-Wave Testing 


588 


9.15 


Summary 


591 


9.16 


Computer Analysis 


592 


CHAPTER 1 0: Operational Amplifiers 


607 


10.1 


Introduction 


607 


10.2 


Differential Amplifier Circuit 


610 


10.3 


BiFET, BiMOS, and CMOS Differential Amplifier Circuits 


617 


10.4 


Op-Amp Basics 


620 


10.5 


Practical Op-Amp Circuits 


623 


10.6 


Op-Amp Specifications— DC Offset Parameters 


628 


10.7 


Op-Amp Specifications— Frequency Parameters 


631 


10.8 


Op-Amp Unit Specifications 


634 


10.9 


Differential and Common-Mode Operation 


639 


10.10 


Summary 


643 


10.11 


Computer Analysis 


644 


CHAPTER 11: Op-Amp Applications 


653 


11.1 


Constant-Gain Multiplier 


653 


11.2 


Voltage Summing 


657 


11.3 


Voltage Buffer 


660 


11.4 


Controlled Sources 


661 


11.5 


Instrumentation Circuits 


663 


11.6 


Active Filters 


667 


11.7 


Summary 


670 


11.8 


Computer Analysis 


671 


CHAPTER 12: Power Amplifiers 


683 


12.1 


Introduction— Definitions and Amplifier Types 


683 


12.2 


Series-Fed Class A Amplifier 


685 



xvi CONTENTS 12.3 Transformer-Coupled Class A Amplifier 688 

12.4 Class B Amplifier Operation 695 

12.5 Class B Amplifier Circuits 699 

12.6 Amplifier Distortion 705 

12.7 Power Transistor Heat Sinking 709 

12.8 Class C and Class D Amplifiers 712 

12.9 Summary 714 

12.10 Computer Analysis 715 

CHAPTER 13: Linear-Digital ICs 722 

13.1 Introduction 722 

13.2 Comparator Unit Operation 722 

13.3 Digital-Analog Converters 729 

13.4 Timer 1C Unit Operation 732 

13.5 Voltage-Controlled Oscillator 736 

13.6 Phase-Locked Loop 738 

13.7 Interfacing Circuitry 742 

13.8 Summary 745 

13.9 Computer Analysis 745 

CHAPTER 14: Feedback and Oscillator Circuits 751 

14.1 Feedback Concepts 751 

14.2 Feedback Connection Types 752 

14.3 Practical Feedback Circuits 758 

14.4 Feedback Amplifier— Phase and Frequency Considerations 763 

14.5 Oscillator Operation 766 

14.6 Phase-Shift Oscillator 767 

14.7 Wien Bridge Oscillator 770 

14.8 Tuned Oscillator Circuit 771 

14.9 Crystal Oscillator 774 

14.10 Unijunction Oscillator 777 

14.11 Summary 778 

14.12 Computer Analysis 779 

CHAPTER 15: Power Supplies (Voltage Regulators) 783 

15.1 Introduction 783 

15.2 General Filter Considerations 784 

15.3 Capacitor Filter 786 

15.4 RC Filter 789 

15.5 Discrete Transistor Voltage Regulation 791 

15.6 1C Voltage Regulators 798 

15.7 Practical Applications 803 

15.8 Summary 805 

15.9 Computer Analysis 806 



CONTENTS xvii 



CHAPTER 16: Other Two-Terminal Devices 811 



16.1 


Introduction 


811 


16.2 


Schottky Barrier (Hot-Carrier) Diodes 


811 


16.3 


Varactor (Varicap) Diodes 


815 


16.4 


Solar Cells 


819 


16.5 


Photodiodes 


824 


16.6 


Photoconductive Cells 


826 


16.7 


IR Emitters 


828 


16.8 


Liquid-Crystal Displays 


829 


16.9 


Thermistors 


831 


16.10 


Tunnel Diodes 


833 


16.11 


Summary 


837 


CHAPTER 17: pnpn and Other Devices 


841 


17.1 


Introduction 


841 


17.2 


Silicon-Controlled Rectifier 


841 


17.3 


Basic Silicon-Controlled Rectifier Operation 


842 


17.4 


SCR Characteristics and Ratings 


843 


17.5 


SCR Applications 


845 


17.6 


Silicon-Controlled Switch 


849 


17.7 


Gate Turn-Off Switch 


851 


17.8 


Light-Activated SCR 


852 


17.9 


Shockley Diode 


854 


17.10 


Diac 


854 


17.11 


Triac 


856 


17.12 


Unijunction Transistor 


857 


17.13 


Phototransistors 


865 


17.14 


Opto-lsolators 


867 


17.15 


Programmable Unijunction Transistor 


869 


17.16 


Summary 


874 



Appendix A: Hybrid Parameters-Graphical Determinations 



and Conversion Equations (Exact and Approximate) 879 

A.1 Graphical Determination of the /j-Parameters 879 

A.2 Exact Conversion Equations 883 

A. 3 Approximate Conversion Equations 883 

Appendix B: Ripple Factor and Voltage Calculations 885 

B. l Ripple Factor of Rectifier 885 

B.2 Ripple Voltage of Capacitor Filter 886 

B.3 Relation of l/dc and V m to Ripple r 887 

B.4 Relation of I4(rms) and V m to Ripple r 888 

B.5 Relation Connecting Conduction Angle, Percentage 

Ripple, and / pe ak/Adc for Rectifier-Capacitor Filter Circuits 889 



XViii CONTENTS 



Appendix C: Charts and Tables 



891 



Appendix D: Solutions to Selected 




Odd-Numbered Problems 


893 


Index 


901 



Semiconductor Diodes 




CHAPTER OBJECTIVES ^ 

Become aware of the general characteristics of three important semiconductor 
materials: Si, Ge, GaAs. 

• Understand conduction using electron and hole theory. 

Be able to describe the difference between n- and /7-type materials. 

Develop a clear understanding of the basic operation and characteristics of a diode in 
the no-bias, forward-bias, and reverse-bias regions. 

Be able to calculate the dc, ac, and average ac resistance of a diode from the 
characteristics. 

Understand the impact of an equivalent circuit whether it is ideal or practical. 

Become familiar with the operation and characteristics of a Zener diode and 
light-emitting diode. 

1.1 INTRODUCTION ^ 

One of the noteworthy things about this field, as in many other areas of technology, is how 
little the fundamental principles change over time. Systems are incredibly smaller, current 
speeds of operation are truly remarkable, and new gadgets surface every day, leaving us to 
wonder where technology is taking us. However, if we take a moment to consider that the 
majority of all the devices in use were invented decades ago and that design techniques 
appearing in texts as far back as the 1930s are still in use, we realize that most of what we 
see is primarily a steady improvement in construction techniques, general characteristics, 
and application techniques rather than the development of new elements and fundamen- 
tally new designs. The result is that most of the devices discussed in this text have been 
around for some time, and that texts on the subject written a decade ago are still good ref- 
erences with content that has not changed very much. The major changes have been in the 
understanding of how these devices work and their full range of capabilities, and in 
improved methods of teaching the fundamentals associated with them. The benefit of all 
this to the new student of the subject is that the material in this text will, we hope, have 
reached a level where it is relatively easy to grasp and the information will have applica- 
tion for years to come. 

The miniaturization that has occurred in recent years leaves us to wonder about its limits. 
Complete systems now appear on wafers thousands of times smaller than the single element 
of earlier networks. The first integrated circuit (IC) was developed by Jack Kilby while 
working at Texas Instruments in 1958 (Fig. 1.1). Today, the Intel® Core™ i7 Extreme 



SEMICONDUCTOR 

DIODES 




Jack St. Clair Kilby, inventor of the 
integrated circuit and co-inventor of 
the electronic handheld calculator. 
(Courtesy of Texas Instruments.) 

Born: Jefferson City, Missouri, 1923. 
MS, University of Wisconsin. 
Director of Engineering and Tech- 
nology, Components Group, Texas 
Instruments. Fellow of the IEEE. 
Holds more than 60 U.S. patents. 




The first integrated circuit, a phase- 
shift oscillator, invented by Jack S. 
Kilby in 1958. (Courtesy of Texas 
Instruments.) 



FIG. 1.1 

Jack St. Clair Kilby. 



Edition Processor of Fig. 1.2 has 731 million transistors in a package that is only slightly 
larger than a 1.67 sq. inches. In 1965, Dr. Gordon E. Moore presented a paper predicting that 
the transistor count in a single IC chip would double every two years. Now, more than 
45 years, later we find that his prediction is amazingly accurate and expected to continue 
for the next few decades. We have obviously reached a point where the primary purpose 
of the container is simply to provide some means for handling the device or system and to 
provide a mechanism for attachment to the remainder of the network. Further miniaturiza- 
tion appears to be limited by four factors: the quality of the semiconductor material, the 
network design technique, the limits of the manufacturing and processing equipment, and 
the strength of the innovative spirit in the semiconductor industry. 

The first device to be introduced here is the simplest of ah electronic devices, yet has a 
range of applications that seems endless. We devote two chapters to the device to introduce 
the materials commonly used in solid-state devices and review some fundamental laws of 
electric circuits. 



1 .2 SEMICONDUCTOR MATERIALS: Ge, Si, AND GaAs ^ 

The construction of every discrete (individual) solid-state (hard crystal structure) electronic 
device or integrated circuit begins with a semiconductor material of the highest quality. 

Semiconductors are a special class of elements having a conductivity between that of a 
good conductor and that of an insulator. 

In general, semiconductor materials fall into one of two classes: single-crystal and 
compound. Single-crystal semiconductors such as germanium (Ge) and silicon (Si) have a 
repetitive crystal structure, whereas compound semiconductors such as gallium arsenide 
(GaAs), cadmium sulfide (CdS), gallium nitride (GaN), and gallium arsenide phosphide 
(GaAsP) are constructed of two or more semiconductor materials of different atomic 
structures. 

The three semiconductors used most frequently in the construction of electronic 
devices are Ge, Si, and GaAs. 

In the first few decades following the discovery of the diode in 1939 and the transis- 
tor in 1947 germanium was used almost exclusively because it was relatively easy to 
find and was available in fairly large quantities. It was also relatively easy to refine to 
obtain very high levels of purity, an important aspect in the fabrication process. How- 
ever, it was discovered in the early years that diodes and transistors constructed using 
germanium as the base material suffered from low levels of reliability due primarily to 
its sensitivity to changes in temperature. At the time, scientists were aware that another 
material, silicon, had improved temperature sensitivities, but the refining process for 
manufacturing silicon of very high levels of purity was still in the development stages. 
Finally, however, in 1954 the first silicon transistor was introduced, and silicon quickly 
became the semiconductor material of choice. Not only is silicon less temperature sensi- 
tive, but it is one of the most abundant materials on earth, removing any concerns about 
availability. The flood gates now opened to this new material, and the manufacturing 
and design technology improved steadily through the following years to the current high 
level of sophistication. 

As time moved on, however, the field of electronics became increasingly sensitive to 
issues of speed. Computers were operating at higher and higher speeds, and communica- 
tion systems were operating at higher levels of performance. A semiconductor material 
capable of meeting these new needs had to be found. The result was the development of 
the first GaAs transistor in the early 1970s. This new transistor had speeds of operation 
up to five times that of Si. The problem, however, was that because of the years of intense 
design efforts and manufacturing improvements using Si, Si transistor networks for most 
applications were cheaper to manufacture and had the advantage of highly efficient design 
strategies. GaAs was more difficult to manufacture at high levels of purity, was more ex- 
pensive, and had little design support in the early years of development. However, in time 
the demand for increased speed resulted in more funding for GaAs research, to the point that 
today it is often used as the base material for new high-speed, very large scale integrated 
(VFSI) circuit designs. 




This brief review of the history of semiconductor materials is not meant to imply that 
GaAs will soon be the only material appropriate for solid-state construction. Germanium 
devices are still being manufactured, although for a limited range of applications. Even 
though it is a temperature-sensitive semiconductor, it does have characteristics that find 
application in a limited number of areas. Given its availability and low manufacturing costs, 
it will continue to find its place in product catalogs. As noted earlier, Si has the benefit of 
years of development, and is the leading semiconductor material for electronic components 
and ICs. In fact, Si is still the fundamental building block for Intel’s new line of processors. 



1.3 COVALENT BONDING AND INTRINSIC MATERIALS ^ 



COVALENT BONDING 
AND INTRINSIC 
MATERIALS 




To fully appreciate why Si, Ge, and GaAs are the semiconductors of choice for the elec- 
tronics industry requires some understanding of the atomic structure of each and how the 
atoms are bound together to form a crystalline structure. The fundamental components of 
an atom are the electron, proton, and neutron. In the lattice structure, neutrons and protons 
form the nucleus and electrons appear in fixed orbits around the nucleus. The Bohr model 
for the three materials is provided in Fig. 1.3. 





FIG. 1.2 

Intel® Core™ 17 Extreme Edition 
Processor. 



(a) 



(b) 



Three valence Five valence 





(c) 

FIG. 1.3 

Atomic structure of (a) silicon; (b) germanium; and 
(c) gallium and arsenic. 



As indicated in Fig. 1.3, silicon has 14 orbiting electrons, germanium has 32 electrons, 
gallium has 31 electrons, and arsenic has 33 orbiting electrons (the same arsenic that is 
a very poisonous chemical agent). For germanium and silicon there are four electrons in 
the outermost shell, which are referred to as valence electrons. Gallium has three valence 
electrons and arsenic has five valence electrons. Atoms that have four valence electrons 
are called tetravalent , those with three are called trivalent , and those with five are called 
pentavalent. The term valence is used to indicate that the potential (ionization potential) 
required to remove any one of these electrons from the atomic structure is significantly 
lower than that required for any other electron in the structure. 



SEMICONDUCTOR 

DIODES 




Valence electrons 



FIG. 1.4 

Covalent bonding of the silicon atom. 



In a pure silicon or germanium crystal the four valence electrons of one atom form a 
bonding arrangement with four adjoining atoms, as shown in Fig. 1.4. 

This bonding of atoms, strengthened by the sharing of electrons, is called covalent 
bonding. 

Because GaAs is a compound semiconductor, there is sharing between the two different 
atoms, as shown in Fig. 1.5. Each atom, gallium or arsenic, is surrounded by atoms of the 
complementary type. There is still a sharing of electrons similar in structure to that of Ge 
and Si, but now five electrons are provided by the As atom and three by the Ga atom. 




FIG. 1.5 

Covalent bonding of the GaAs crystal. 



Although the covalent bond will result in a stronger bond between the valence electrons 
and their parent atom, it is still possible for the valence electrons to absorb sufficient kinetic 
energy from external natural causes to break the covalent bond and assume the “free” state. 
The term free is applied to any electron that has separated from the fixed lattice structure and 
is very sensitive to any applied electric fields such as established by voltage sources or any 
difference in potential. The external causes include effects such as light energy in the form 
of photons and thermal energy (heat) from the surrounding medium. At room temperature 
there are approximately 1.5 X 10 10 free carriers in 1 cm 3 of intrinsic silicon material, that 
is, 15,000,000,000 (15 billion) electrons in a space smaller than a small sugar cube — an 
enormous number. 



ENERGY LEVELS 



The term intrinsic is applied to any semiconductor material that has been carefully 
refined to reduce the number of impurities to a very low level — essentially as pure as 
can be made available through modern technology . 

The free electrons in a material due only to external causes are referred to as intrinsic car- 
riers. Table 1.1 compares the number of intrinsic carriers per cubic centimeter (abbreviated n\) 
for Ge, Si, and GaAs. It is interesting to note that Ge has the highest number and GaAs the 
lowest. In fact, Ge has more than twice the number as GaAs. The number of carriers in the 
intrinsic form is important, but other characteristics of the material are more significant 
in determining its use in the field. One such factor is the relative mobility (gL n ) of the free 
carriers in the material, that is, the ability of the free carriers to move throughout the mate- 
rial. Table 1.2 clearly reveals that the free carriers in GaAs have more than five times the 
mobility of free carriers in Si, a factor that results in response times using GaAs electronic 
devices that can be up to five times those of the same devices made from Si. Note also that 
free carriers in Ge have more than twice the mobility of electrons in Si, a factor that results 
in the continued use of Ge in high-speed radio frequency applications. 



TABLE 1.1 



Intrinsic Carriers ni 





Intrinsic Carriers 


Semiconductor 


(per cubic centimeter) 


GaAs 


1.7 X 10 6 


Si 


1.5 X 10 10 


Ge 


2.5 X 10 13 



TABLE 1.2 



Relative Mobility Factor /ji n 



Semiconductor 


p n (cm 2 /V*s) 


Si 


1500 


Ge 


3900 


GaAs 


8500 



One of the most important technological advances of recent decades has been the abil- 
ity to produce semiconductor materials of very high purity. Recall that this was one of the 
problems encountered in the early use of silicon — it was easier to produce germanium of 
the required purity levels. Impurity levels of 1 part in 10 billion are common today, with 
higher levels attainable for large-scale integrated circuits. One might ask whether these 
extremely high levels of purity are necessary. They certainly are if one considers that the 
addition of one part of impurity (of the proper type) per million in a wafer of silicon material 
can change that material from a relatively poor conductor to a good conductor of electricity. 
We obviously have to deal with a whole new level of comparison when we deal with the 
semiconductor medium. The ability to change the characteristics of a material through this 
process is called doping , something that germanium, silicon, and gallium arsenide readily 
and easily accept. The doping process is discussed in detail in Sections 1.5 and 1.6. 

One important and interesting difference between semiconductors and conductors is their 
reaction to the application of heat. For conductors, the resistance increases with an increase 
in heat. This is because the numbers of carriers in a conductor do not increase significantly 
with temperature, but their vibration pattern about a relatively fixed location makes it in- 
creasingly difficult for a sustained flow of carriers through the material. Materials that react 
in this manner are said to have a positive temperature coefficient. Semiconductor materials, 
however, exhibit an increased level of conductivity with the application of heat. As the tem- 
perature rises, an increasing number of valence electrons absorb sufficient thermal energy to 
break the covalent bond and to contribute to the number of free carriers. Therefore: 

Semiconductor materials have a negative temperature coefficient. 

1-4 ENERGY LEVELS ^ 

Within the atomic structure of each and every isolated atom there are specific energy levels 
associated with each shell and orbiting electron, as shown in Fig. 1.6. The energy levels 
associated with each shell will be different for every element. However, in general: 

The farther an electron is from the nucleus , the higher is the energy state , and any 
electron that has left its parent atom has a higher energy state than any electron in 
the atomic structure. 

Note in Fig. 1 .6a that only specific energy levels can exist for the electrons in the atomic 
structure of an isolated atom. The result is a series of gaps between allowed energy levels 



SEMICONDUCTOR 

DIODES 



Valence level (outermost shell) 




Second level (next inner shell) 
Third level (etc.) 

^ Nucleus 



(a) 



Energy 

Conduction band 



Electrons 
"free" to 
establish 
conduction 



Unable to reach 
conduction level 



E g > 5 eV 







Valence band 



Insulator 



1 / 



Valence — 
/ electrons 
bound to 
the atomic 
stucture 



Energy 



Conduction band 




Valence band 



E g = 0.67 eV (Ge) 

E g = 1.1 eV (Si) 

E g = 1.43 eV (GaAs) 

Semiconductor 



Energy 



The bands 
overlaps 



Conduction band 



Valence band 

Conductor 



(b) 



FIG. 1.6 



Energy levels: (a) discrete levels in isolated atomic structures; (b) conduction and valence bands of an insulator, 

a semiconductor, and a conductor. 



where carriers are not permitted. However, as the atoms of a material are brought closer 
together to form the crystal lattice structure, there is an interaction between atoms, which 
will result in the electrons of a particular shell of an atom having slightly different energy 
levels from electrons in the same orbit of an adjoining atom. The result is an expansion 
of the fixed, discrete energy levels of the valence electrons of Fig. 1.6a to bands as shown 
in Fig. 1.6b. In other words, the valence electrons in a silicon material can have varying 
energy levels as long as they fall within the band of Fig. 1.6b. Figure 1.6b clearly reveals 
that there is a minimum energy level associated with electrons in the conduction band and 
a maximum energy level of electrons bound to the valence shell of the atom. Between the 
two is an energy gap that the electron in the valence band must overcome to become a free 
carrier. That energy gap is different for Ge, Si, and GaAs; Ge has the smallest gap and GaAs 
the largest gap. In total, this simply means that: 

An electron in the valence band of silicon must absorb more energy than one in the 
valence band of germanium to become a free carrier. Similarly, an electron in the 
valence band of gallium arsenide must gain more energy than one in silicon or 
germanium to enter the conduction band. 

This difference in energy gap requirements reveals the sensitivity of each type of 
semiconductor to changes in temperature. For instance, as the temperature of a Ge sample 
increases, the number of electrons that can pick up thermal energy and enter the conduction 
band will increase quite rapidly because the energy gap is quite small. However, the number 
of electrons entering the conduction band for Si or GaAs would be a great deal less. This 
sensitivity to changes in energy level can have positive and negative effects. The design of 
photodetectors sensitive to light and security systems sensitive to heat would appear to be 
an excellent area of application for Ge devices. However, for transistor networks, where 
stability is a high priority, this sensitivity to temperature or light can be a detrimental factor. 




The energy gap also reveals which elements are useful in the construction of light-emitting 
devices such as light-emitting diodes (LEDs), which will be introduced shortly. The wider 
the energy gap, the greater is the possibility of energy being released in the form of visible 
or invisible (infrared) light waves. For conductors, the overlapping of valence and conduc- 
tion bands essentially results in all the additional energy picked up by the electrons being 
dissipated in the form of heat. Similarly, for Ge and Si, because the energy gap is so small, 
most of the electrons that pick up sufficient energy to leave the valence band end up in the 
conduction band, and the energy is dissipated in the form of heat. However, for GaAs the 
gap is sufficiently large to result in significant light radiation. For LEDs (Section 1.9) the 
level of doping and the materials chosen determine the resulting color. 

Before we leave this subject, it is important to underscore the importance of understand- 
ing the units used for a quantity. In Fig. 1 .6 the units of measurement are electron volts (eV). 
The unit of measure is appropriate because W (energy) = QV (as derived from the defining 
equation for voltage: V=W/Q). Substituting the charge of one electron and a potential dif- 
ference of 1 V results in an energy level referred to as one electron volt. 

That is, 

W= QV 

= (1.6 X 10 _19 C)(1 V) 

= 1.6 X 10“ 19 J 

and 



1 eV = 1.6 X 10“ 19 J 



( 1 . 1 ) 



n-TYPE AND p - TYPE 
MATERIALS 



1 .5 fl-TYPE AND p-TYPE MATERIALS ^ 

Because Si is the material used most frequently as the base (substrate) material in the con- 
struction of solid-state electronic devices, the discussion to follow in this and the next few 
sections deals solely with Si semiconductors. Because Ge, Si, and GaAs share a similar 
covalent bonding, the discussion can easily be extended to include the use of the other 
materials in the manufacturing process. 

As indicated earlier, the characteristics of a semiconductor material can be altered sig- 
nificantly by the addition of specific impurity atoms to the relatively pure semiconductor 
material. These impurities, although only added at 1 part in 10 million, can alter the band 
structure sufficiently to totally change the electrical properties of the material. 

A semiconductor material that has been subjected to the doping process is called an 
extrinsic material. 

There are two extrinsic materials of immeasureable importance to semiconductor device 
fabrication: n-type and p - type materials. Each is described in some detail in the following 
subsections. 

n-Type Material 

Both n-type and /7-type materials are formed by adding a predetermined number of impurity 
atoms to a silicon base. An n-type material is created by introducing impurity elements that 
have five valence electrons ( pentavalent ), such as antimony , arsenic , and phosphorus. Each is 
a member of a subset group of elements in the Periodic Table of Elements referred to as Group 
V because each has five valence electrons. The effect of such impurity elements is indicated in 
Fig. 1.7 (using antimony as the impurity in a silicon base). Note that the four covalent bonds 
are still present. There is, however, an additional fifth electron due to the impurity atom, which 
is unassociated with any particular covalent bond. This remaining electron, loosely bound to 
its parent (antimony) atom, is relatively free to move within the newly formed n-type material. 
Since the inserted impurity atom has donated a relatively “free” electron to the structure: 

Diffused impurities with five valence electrons are called donor atoms. 

It is important to realize that even though a large number of free carriers have been estab- 
lished in the n-type material, it is still electrically neutral since ideally the number of posi- 
tively charged protons in the nuclei is still equal to the number of free and orbiting negatively 
charged electrons in the structure. 



SEMICONDUCTOR 

DIODES 




© \ / © . 

Fifth valence electron 
of antimony 

oT \ e 



© 


Si 


© 


© 


Sb 


© 


- 


Si 


- 




Te] 






(e\ 


\ 




fe\ 














Antimony 


(Sb) 






[el 






ley 


impurity 


lej 






Si 


© 


© 


Si 


© 


- 


Si 


eT 




fe\ 




(e\ 




fe] 





FIG. 1.7 

Antimony impurity in n-type material 



The effect of this doping process on the relative conductivity can best be described 
through the use of the energy-band diagram of Fig. 1.8. Note that a discrete energy level 
(called the donor level) appears in the forbidden band with an E g significantly less than that 
of the intrinsic material. Those free electrons due to the added impurity sit at this energy 
level and have less difficulty absorbing a sufficient measure of thermal energy to move into 
the conduction band at room temperature. The result is that at room temperature, there are a 
large number of carriers (electrons) in the conduction level, and the conductivity of the ma- 
terial increases significantly. At room temperature in an intrinsic Si material there is about 
one free electron for every 10 12 atoms. If the dosage level is 1 in 10 million (10 7 ), the ratio 
10 12 /10 7 = 10 5 indicates that the carrier concentration has increased by a ratio of 100,000: 1 . 



Energy 



E g for intrinsic 
materials 



Conduction band | 

E g = considerably less than in Fig. 1.6(b) for semiconductors 

Donor energy level 

Valence band 




FIG. 1.8 

Effect of donor impurities on the energy band structure. 



p - Type Material 

The p - type material is formed by doping a pure germanium or silicon crystal with impurity 
atoms having three valence electrons. The elements most frequently used for this purpose 
are boron , gallium , and indium. Each is a member of a subset group of elements in the Peri- 
odic Table of Elements referred to as Group III because each has three valence electrons. 
The effect of one of these elements, boron, on a base of silicon is indicated in Fig. 1.9. 

Note that there is now an insufficient number of electrons to complete the covalent bonds 
of the newly formed lattice. The resulting vacancy is called a hole and is represented by a 
small circle or a plus sign, indicating the absence of a negative charge. Since the resulting 
vacancy will readily accept a free electron: 

The diffused impurities with three valence electrons are called acceptor atoms. 

The resulting /7-type material is electrically neutral, for the same reasons described for 
the 77-type material. 




n-TYPE AND p - TYPE 
MATERIALS 




Electron versus Hole Flow 

The effect of the hole on conduction is shown in Fig. 1.10. If a valence electron acquires 
sufficient kinetic energy to break its covalent bond and fills the void created by a hole, then 
a vacancy, or hole, will be created in the covalent bond that released the electron. There is, 
therefore, a transfer of holes to the left and electrons to the right, as shown in Fig. 1.10. 
The direction to be used in this text is that of conventional flow, which is indicated by the 
direction of hole flow. 




-► 

Electron flow 

(b) 



FIG. 1.10 

Electron versus hole flow. 



Majority and Minority Carriers 

In the intrinsic state, the number of free electrons in Ge or Si is due only to those few elec- 
trons in the valence band that have acquired sufficient energy from thermal or light sources 
to break the covalent bond or to the few impurities that could not be removed. The vacan- 
cies left behind in the covalent bonding structure represent our very limited supply of 
holes. In an n-type material, the number of holes has not changed significantly from this 
intrinsic level. The net result, therefore, is that the number of electrons far outweighs the 
number of holes. For this reason: 

In an n-type material (Fig. 1.11a) the electron is called the majority carrier and the 
hole the minority carrier. 

For the p - type material the number of holes far outweighs the number of electrons, as 
shown in Fig. 1.11b. Therefore: 

In a p-type material the hole is the majority carrier and the electron is the minority carrier. 

When the fifth electron of a donor atom leaves the parent atom, the atom remaining ac- 
quires a net positive charge: hence the plus sign in the donor-ion representation. For similar 
reasons, the minus sign appears in the acceptor ion. 




10 SEMICONDUCTOR 
DIODES 



Donor ions 




Majority 

carriers 



Minority 

carrier 



(a) 



Majority 

carriers 



Acceptor ions 




FIG. 1.11 

(a) n-type material; (b) p-type material. 



The n- and p-type materials represent the basic building blocks of semiconductor devices. 
We will find in the next section that the “joining” of a single n- type material with a p-type ma- 
terial will result in a semiconductor element of considerable importance in electronic systems. 

1 .6 SEMICONDUCTOR DIODE ^ 

Now that both n- and p- type materials are available, we can construct our first solid-state 
electronic device: The semiconductor diode , with applications too numerous to mention, is 
created by simply joining an 72 -type and a p- type material together, nothing more, just the 
joining of one material with a majority carrier of electrons to one with a majority carrier of 
holes. The basic simplicity of its construction simply reinforces the importance of the 
development of this solid-state era. 

No Applied Bias (17 = 0 V) 

At the instant the two materials are “joined” the electrons and the holes in the region of the 
junction will combine, resulting in a lack of free carriers in the region near the junction, as 
shown in Fig. 1.12a. Note in Fig. 1.12a that the only particles displayed in this region are 
the positive and the negative ions remaining once the free carriers have been absorbed. 

This region of uncovered positive and negative ions is called the depletion region due 
to the “depletion” of free carriers in the region . 

If leads are connected to the ends of each material, a two-terminal device results, as 
shown in Figs. 1.12a and 1.12b. Three options then become available: no bias, forward 
bias , and reverse bias. The term bias refers to the application of an external voltage across 
the two terminals of the device to extract a response. The condition shown in Figs. 1.12a 
and 1.12b is the no-bias situation because there is no external voltage applied. It is simply 
a diode with two leads sitting isolated on a laboratory bench. In Fig. 1.12b the symbol for 
a semiconductor diode is provided to show its correspondence with the p-n junction. In 
each figure it is clear that the applied voltage is 0 V (no bias) and the resulting current is 
0 A, much like an isolated resistor. The absence of a voltage across a resistor results in 
zero current through it. Even at this early point in the discussion it is important to note the 
polarity of the voltage across the diode in Fig. 1.12b and the direction given to the current. 
Those polarities will be recognized as the defined polarities for the semiconductor diode. 
If a voltage applied across the diode has the same polarity across the diode as in Fig. 1.12b, 
it will be considered a positive voltage. If the reverse, it is a negative voltage. The same 
standards can be applied to the defined direction of current in Fig. 1.12b. 

Under no-bias conditions, any minority carriers (holes) in the n- type material that find 
themselves within the depletion region for any reason whatsoever will pass quickly into the 
/7-type material. The closer the minority carrier is to the junction, the greater is the attraction 
for the layer of negative ions and the less is the opposition offered by the positive ions in 
the depletion region of the 72-type material. We will conclude, therefore, for future discus- 
sions, that any minority carriers of the n- type material that find themselves in the depletion 
region will pass directly into the /7-type material. This carrier flow is indicated at the top of 
Fig. 1.12c for the minority carriers of each material. 





Depletion region 



SEMICONDUCTOR DIODE H 




(a) 



+ y D = ov - 

(no bias) 

O - ►! o 

I D = 0 mA 




Minority carrier flow 

I hole 



1 hole 



Majority carrier flow 



(b) 



(c) 



FIG. 1.12 

A p-n junction with no external bias: (a) an internal distribution of charge; (b) a diode symbol, 
with the defined polarity and the current direction ; (c) demonstration that the net carrier 
flow is zero at the external terminal of the device when V D = 0 V. 

The majority carriers (electrons) of the /7-type material must overcome the attractive 
forces of the layer of positive ions in the ft-type material and the shield of negative ions in 
the p- type material to migrate into the area beyond the depletion region of the /7-type mate- 
rial. However, the number of majority carriers is so large in the n- type material that there 
will invariably be a small number of majority carriers with sufficient kinetic energy to pass 
through the depletion region into the /7-type material. Again, the same type of discussion 
can be applied to the majority carriers (holes) of the /7-type material. The resulting flow due 
to the majority carriers is shown at the bottom of Fig. 1.12c. 

A close examination of Fig. 1.12c will reveal that the relative magnitudes of the flow 
vectors are such that the net flow in either direction is zero. This cancellation of vectors 
for each type of carrier flow is indicated by the crossed lines. The length of the vector 
representing hole flow is drawn longer than that of electron flow to demonstrate that the 
two magnitudes need not be the same for cancellation and that the doping levels for each 
material may result in an unequal carrier flow of holes and electrons. In summary, therefore: 

In the absence of an applied bias across a semiconductor diode, the net flow of charge 
in one direction is zero . 

In other words, the current under no-bias conditions is zero, as shown in Figs. 1.12a 
and 1.12b. 

Reverse-Bias Condition (V D < 0 V) 

If an external potential of V volts is applied across the p-n junction such that the positive 
terminal is connected to the n- type material and the negative terminal is connected to the 
/7-type material as shown in Fig. 1.13, the number of uncovered positive ions in the deple- 
tion region of the n- type material will increase due to the large number of free electrons 
drawn to the positive potential of the applied voltage. For similar reasons, the number of 
uncovered negative ions will increase in the /7-type material. The net effect, therefore, is a 




12 



SEMICONDUCTOR 

DIODES 



I s Minority- carrier flow 
~ oa 

1 majority 




O 



v D 

>1 



+ 

-o 



±-4 



(Opposite) 



-O 

+ 



(b) 



FIG. 1.13 

Reverse-biased p-n junction: (a) internal distribution of charge under 
reverse-bias conditions; (b) reverse-bias polarity and direction of reverse 
saturation current. 

widening of the depletion region. This widening of the depletion region will establish too 
great a barrier for the majority carriers to overcome, effectively reducing the majority car- 
rier flow to zero, as shown in Fig. 1.13a. 

The number of minority carriers, however, entering the depletion region will not change, 
resulting in minority-carrier flow vectors of the same magnitude indicated in Fig. 1.12c 
with no applied voltage. 

The current that exists under reverse-bias conditions is called the reverse saturation 
current and is represented by I s . 

The reverse saturation current is seldom more than a few microamperes and typically in 
nA, except for high-power devices. The term saturation comes from the fact that it reaches its 
maximum level quickly and does not change significantly with increases in the reverse-bias 
potential, as shown on the diode characteristics of Fig. 1.15 for V D < 0 V. The reverse-biased 
conditions are depicted in Fig. 1.13b for the diode symbol and p-n junction. Note, in particu- 
lar, that the direction of I s is against the arrow of the symbol. Note also that the negative side of 
the applied voltage is connected to the p-type material and the positive side to the n - type ma- 
terial, the difference in underlined letters for each region revealing a reverse-bias condition. 

Forward-Bias Condition (V D > 0 V) 

A forward-bias or “on” condition is established by applying the positive potential to the 
p - type material and the negative potential to the ft-type material as shown in Fig. 1.14. 

The application of a forward-bias potential V D will “pressure” electrons in the n - type mate- 
rial and holes in the p - type material to recombine with the ions near the boundary and reduce 
the width of the depletion region as shown in Fig. 1.14a. The resulting minority-carrier flow 



majorily J 



\l 0 = l 



majority 







p ^ n 

Depletion region 




(a) 





(Similar) 

(b) 



FIG. 1.14 

Forward-biased p-n junction: (a) internal distribution of charge under forward-bias 
conditions; (b) forward-bias polarity and direction of resulting current. 



of electrons from the p - type material to the n - type material (and of holes from the n - type 
material to the /7-type material) has not changed in magnitude (since the conduction level is 
controlled primarily by the limited number of impurities in the material), but the reduction 
in the width of the depletion region has resulted in a heavy majority flow across the junc- 
tion. An electron of the ft-type material now “sees” a reduced barrier at the junction due to 
the reduced depletion region and a strong attraction for the positive potential applied to the 
/7-type material. As the applied bias increases in magnitude, the depletion region will con- 
tinue to decrease in width until a flood of electrons can pass through the junction, resulting 
in an exponential rise in current as shown in the forward-bias region of the characteristics 
of Fig. 1.15. Note that the vertical scale of Fig. 1.15 is measured in milliamperes (although 
some semiconductor diodes have a vertical scale measured in amperes), and the horizontal 
scale in the forward-bias region has a maximum of 1 V. Typically, therefore, the voltage 
across a forward-biased diode will be less than 1 V. Note also how quickly the current rises 
beyond the knee of the curve. 

It can be demonstrated through the use of solid-state physics that the general charac- 
teristics of a semiconductor diode can be defined by the following equation, referred to as 
Shockley’s equation, for the forward- and reverse-bias regions: 



I D = I s (e v °/ nV r - 1) 



(A) 



( 1 . 2 ) 



SEMICONDUCTOR DIODE 



13 



where I s is the reverse saturation current 

V D is the applied forward-bias voltage across the diode 

n is an ideality factor, which is a function of the operating conditions and physi- 
cal construction; it has a range between 1 and 2 depending on a wide variety of 
factors (n = 1 will be assumed throughout this text unless otherwise noted). 

The voltage V T in Eq. (1.1) is called the thermal voltage and is determined by 



where 




(V) 



kis Boltzmann’s constant = 1.38 X 10 -23 J/K 

T k is the absolute temperature in kelvins = 273 + the temperature in °C 
q is the magnitude of electronic charge = 1.6 X 10 -19 C 



( 1 . 3 ) 



EXAMPLE 1.1 At a temperature of 27°C (common temperature for components in an 
enclosed operating system), determine the thermal voltage V T . 

Solution ; Substituting into Eq. (1.3), we obtain 

T = 273 + °C = 273 + 27 = 300 K 
_kTx_ (1.38 X 10~ 23 J/K)(30 K) 

T ~ q 1.6 x io -19 c 

= 25.875 mV s 26 mV 

The thermal voltage will become an important parameter in the analysis to follow in this 
chapter and a number of those to follow. 



Initially, Eq. (1.2) with all its defined quantities may appear somewhat complex. How- 
ever, it will not be used extensively in the analysis to follow. It is simply important at this 
point to understand the source of the diode characteristics and which factors affect its shape. 

A plot of Eq. (1.2) with I s = 10 pA is provided in Fig. 1.15 as the dashed line. If we 
expand Eq. (1.2) into the following form, the contributing component for each region of 
Fig. 1.15 can be described with increased clarity: 

I D = I s e VD/nVT ~ I s 

For positive values of V D the first term of the above equation will grow very quickly and 
totally overpower the effect of the second term. The result is the following equation, which 
only has positive values and takes on the exponential format e x appearing in Fig. 1.16: 

I D = I s e Vl> l nV T (V^ positive) 



14 SEMICONDUCTOR 
DIODES 




The exponential curve of Fig. 1.16 increases very rapidly with increasing values of x. 
At x = 0, e° = 1, whereas at x = 5, it jumps to greater than 148. If we continued to x = 10, 
the curve jumps to greater than 22,000. Clearly, therefore, as the value of x increases, the 
curve becomes almost vertical, an important conclusion to keep in mind when we examine 
the change in current with increasing values of applied voltage. 




FIG. 1.16 

Plot of e x . 



For negative values of V D the exponential term drops very quickly below the level of/, SEMICONDUCTOR DIODE 15 
and the resulting equation for I D is simply 

In = -I s (V D negative) 

Note in Fig. 1.15 that for negative values of Vp the current is essentially horizontal at 
the level of —I s . 

At V = 0 V, Eq. (1.2) becomes 

Id = Is(e° - 1) = U 1 - 1) = OmA 
as confirmed by Fig. 1.15. 

The sharp change in direction of the curve at V D = 0 V is simply due to the change in 
current scales from above the axis to below the axis. Note that above the axis the scale is in 
milliamperes (mA), whereas below the axis it is in picoamperes (pA). 

Theoretically, with all things perfect, the characteristics of a silicon diode should appear 
as shown by the dashed line of Fig. 1.15. However, commercially available silicon diodes 
deviate from the ideal for a variety of reasons including the internal “body” resistance and the 
external “contact” resistance of a diode. Each contributes to an additional voltage at the same 
current level, as determined by Ohm’ s law, causing the shift to the right witnessed in Fig. 1.15. 

The change in current scales between the upper and lower regions of the graph was noted 
earlier. For the voltage V D there is also a measurable change in scale between the right-hand 
region of the graph and the left-hand region. For positive values of V D the scale is in tenths 
of volts, and for the negative region it is in tens of volts. 

It is important to note in Fig. 1.14b how: 

The defined direction of conventional current for the positive voltage region matches 
the arrowhead in the diode symbol. 

This will always be the case for a forward-biased diode. It may also help to note that the 
forward-bias condition is established when the bar representing the negative side of the 
applied voltage matches the side of the symbol with the vertical bar. 

Going back a step further by looking at Fig. 1.14b, we find a forward-bias condition is 
established across a p-n junction when the positive side of the applied voltage is applied to 
the p- type material (noting the correspondence in the letter p) and the negative side of the 
applied voltage is applied to the n-type material (noting the same correspondence). 

It is particularly interesting to note that the reverse saturation current of the commercial 
unit is significantly larger than that of I s in Shockley’s equation. In fact, 

The actual reverse saturation current of a commercially available diode will normally 
be measurably larger than that appearing as the reverse saturation current in 
Shockley’s equation. 

This increase in level is due to a wide range of factors that include 

- leakage currents 

- generation of carriers in the depletion region 

- higher doping levels that result in increased levels of reverse current 

- sensitivity to the intrinsic level of carriers in the component materials by a squared 
factor — double the intrinsic level, and the contribution to the reverse current could 
increase by a factor of four. 

- a direct relationship with the junction area — double the area of the junction, and 
the contribution to the reverse current could double. High-power devices that have 
larger junction areas typically have much higher levels of reverse current. 

- temperature sensitivity — for every 5°C increase in current, the level of reverse sat- 
uration current in Eq. 1.2 will double, whereas a 10°C increase in current will result 
in doubling of the actual reverse current of a diode. 

Note in the above the use of the terms reverse saturation current and reverse current. The 
former is simply due to the physics of the situation, whereas the latter includes all the other 
possible effects that can increase the level of current. 

We will find in the discussions to follow that the ideal situation is for I s to be 0 A in the 
reverse-bias region. The fact that it is typically in the range of 0.01 pA to 10 pA today as 
compared to 0.1 piA to 1 piA a few decades ago is a credit to the manufacturing industry. 

Comparing the common value of 1 nA to the 1-piA level of years past shows an improve- 
ment factor of 100,000. 



16 semiconductor Breakdown Region 

DIODES 

Even though the scale of Fig. 1.15 is in tens of volts in the negative region, there is a point 
where the application of too negative a voltage with the reverse polarity will result in a 
sharp change in the characteristics, as shown in Fig. 1.17. The current increases at a very 
rapid rate in a direction opposite to that of the positive voltage region. The reverse-bias 
potential that results in this dramatic change in characteristics is called the breakdown 
potential and is given the label V BV . 




FIG. 1.17 

Breakdown region. 

As the voltage across the diode increases in the reverse-bias region, the velocity of the 
minority carriers responsible for the reverse saturation current I s will also increase. Eventu- 
ally, their velocity and associated kinetic energy (W K = \ mv 2 ) will be sufficient to release 
additional carriers through collisions with otherwise stable atomic structures. That is, an 
ionization process will result whereby valence electrons absorb sufficient energy to leave the 
parent atom. These additional carriers can then aid the ionization process to the point where 
a high avalanche current is established and the avalanche breakdown region determined. 

The avalanche region iV B y) can be brought closer to the vertical axis by increasing the 
doping levels in the p- and zz-type materials. However, as V BV decreases to very low levels, 
such as —5 V, another mechanism, called Zener breakdown , will contribute to the sharp 
change in the characteristic. It occurs because there is a strong electric field in the region 
of the junction that can disrupt the bonding forces within the atom and “generate” carriers. 
Although the Zener breakdown mechanism is a significant contributor only at lower levels 
of V BV , this sharp change in the characteristic at any level is called the Zener region , and 
diodes employing this unique portion of the characteristic of a p-n junction are called Zener 
diodes. They are described in detail in Section 1.15. 

The breakdown region of the semiconductor diode described must be avoided if the 
response of a system is not to be completely altered by the sharp change in characteristics 
in this reverse-voltage region. 

The maximum reverse-bias potential that can be applied before entering the break- 
down region is called the peak inverse voltage (referred to simply as the PIV rating) or 
the peak reverse voltage ( denoted the PRV rating). 

If an application requires a PIV rating greater than that of a single unit, a number of 
diodes of the same characteristics can be connected in series. Diodes are also connected in 
parallel to increase the current-carrying capacity. 

In general, the breakdown voltage of GaAs diodes is about 10% higher those for silicon 
diodes but after 200% higher than levels for Ge diodes. 

Ge, Si, and GaAs 

The discussion thus far has solely used Si as the base semiconductor material. It is now impor- 
tant to compare it to the other two materials of importance: GaAs and Ge. A plot comparing 
the characteristics of Si, GaAs, and Ge diodes is provided in Fig. 1.18. The curves are not 



SEMICONDUCTOR DIODE 17 




FIG. 1.18 

Comparison of Ge, Si, and GaAs commercial diodes. 



simply plots of Eq. 1 .2 but the actual response of commercially available units. The total reverse 
current is shown and not simply the reverse saturation current. It is immediately obvious that 
the point of vertical rise in the characteristics is different for each material, although the general 
shape of each characteristic is quite similar. Germanium is closest to the vertical axis and GaAs 
is the most distant. As noted on the curves, the center of the knee (hence the K is the notation 
V K ) of the curve is about 0.3 V for Ge, 0.7 V for Si, and 1.2 V for GaAs (see Table 1.3). 

The shape of the curve in the reverse-bias region is also quite similar for each material, 
but notice the measurable difference in the magnitudes of the typical reverse saturation 
currents. For GaAs, the reverse saturation current is typically about 1 pA, compared to 10 pA 
for Si and 1 fiA for Ge, a significant difference in levels. 

Also note the relative magnitudes of the reverse breakdown voltages for each material. 
GaAs typically has maximum breakdown levels that exceed those of Si devices of the same 
power level by about 10%, with both having breakdown voltages that typically extend be- 
tween 50 V and 1 kV. There are Si power diodes with breakdown voltages as high as 20 kV. 
Germanium typically has breakdown voltages of less than 100 V, with maximums around 
400 V. The curves of Fig. 1.18 are simply designed to reflect relative breakdown voltages 
for the three materials. When one considers the levels of reverse saturation currents and 
breakdown voltages, Ge certainly sticks out as having the least desirable characteristics. 

A factor not appearing in Fig. 1.18 is the operating speed for each material — an impor- 
tant factor in today’s market. For each material, the electron mobility factor is provided 
in Table 1.4. It provides an indication of how fast the carriers can progress through the 
material and therefore the operating speed of any device made using the materials. Quite 
obviously, GaAs stands out, with a mobility factor more than five times that of silicon and 
twice that of germanium. The result is that GaAs and Ge are often used in high-speed ap- 
plications. However, through proper design, careful control of doping levels, and so on, 
silicon is also found in systems operating in the gigahertz range. Research today is also 
looking at compounds in groups III-V that have even higher mobility factors to ensure that 
industry can meet the demands of future high-speed requirements. 



TABLE 1.3 

Knee Voltages V% 



Semiconductor 


Va-(V) 


Ge 


0.3 


Si 


0.7 


GaAs 


1.2 



TABLE 1.4 



Electron Mobility p n 



Semiconductor 


im n ( cm 2 /V • s) 


Ge 


3900 


Si 


1500 


GaAs 


8500 



18 SEMICONDUCTOR 

DI0DES EXAMPLE 1.2 Using the curves of Fig 1.18: 

a. Determine the voltage across each diode at a current of 1 mA. 

b. Repeat for a current of 4 mA. 

c. Repeat for a current of 30 mA. 

d. Determine the average value of the diode voltage for the range of currents listed above. 

e. How do the average values compare to the knee voltages listed in Table 1.3? 

Solution: 

a. V D (Ge) = 0.2 V, V D (Si) = 0.6 V, V D (GaAs) = 1.1 V 

b. V D (Ge) = 0.3 V, V D (Si) = 0.7 V, V D (GaAs) = 1.2 V 

c. V D (Ge) = 0.42 V, Vb(Si) = 0.82 V, V D (GaAs) = 1.33 V 

d. Ge: V av = (0.2 V + 0.3 V + 0.42 V)/3 = 0.307 V 
Si: V av = (0.6 V + 0.7 V + 0.82 V)/3 = 0.707 V 
GaAs: V av = (1.1 V + 1.2 V + 1.33 V)/3 = 1.21 V 

e. Very close correspondence. Ge: 0.307 V vs. 0.3, V, Si: 0.707 V vs. 0.7 V, GaAs: 1.21 V 
vs. 1.2 V. 



Temperature Effects 

Temperature can have a marked effect on the characteristics of a semiconductor diode, as 
demonstrated by the characteristics of a silicon diode shown in Fig. 1.19: 

In the forward-bias region the characteristics of a silicon diode shift to the left at a rate 
of 2.5 mV per centigrade degree increase in temperature. 





































































































































































































































































































































































































































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FIG. 1.19 

Variation in Si diode characteristics with temperature change. 



An increase from room temperature (20°C) to 100°C (the boiling point of water) results 
in a drop of 80(2.5 mV) = 200 mV, or 0.2 V, which is significant on a graph scaled in 
tenths of volts. A decrease in temperature has the reverse effect, as also shown in the figure: 

In the reverse-bias region the reverse current of a silicon diode doubles for every 10° C 
rise in temperature. 

For a change from 20°C to 100°C, the level of I s increases from 10 nA to a value of 
2.56 /JL A, which is a significant, 256-fold increase. Continuing to 200°C would result in a 
monstrous reverse saturation current of 2.62 mA. For high-temperature applications one 
would therefore look for Si diodes with room- temperature I s closer to 10 pA, a level com- 
monly available today, which would limit the current to 2.62 pA. It is indeed fortunate that 
both Si and GaAs have relatively small reverse saturation currents at room temperature. 
GaAs devices are available that work very well in the — 200°C to +200°C temperature 
range, with some having maximum temperatures approaching 400°C. Consider, for a mo- 
ment, how huge the reverse saturation current would be if we started with a Ge diode with 
a saturation current of 1 /mA and applied the same doubling factor. 

Finally, it is important to note from Fig. 1.19 that: 

The reverse breakdown voltage of a semiconductor diode will increase or 
decrease with temperature. 

However, if the initial breakdown voltage is less than 5 V, the breakdown voltage may 
actually decrease with temperature. The sensitivity of the breakdown potential to changes 
of temperature will be examined in more detail in Section 1.15. 

Summary 

A great deal has been introduced in the foregoing paragraphs about the construction of a 
semiconductor diode and the materials employed. The characteristics have now been pre- 
sented and the important differences between the response of the materials discussed. It is 
now time to compare the p-n junction response to the desired response and reveal the pri- 
mary functions of a semiconductor diode. 

Table 1.5 provides a synopsis of material regarding the three most frequently used semi- 
conductor materials. Figure 1.20 includes a short biography of the first research scientist to 
discover the p-n junction in a semiconductor material. 



TABLE 1.5 

The Current Commercial Use ofGe, Si, and GaAs 



Ge: Germanium is in limited production due to its temperature sensitivity and high 

reverse saturation current. It is still commercially available but is limited to 
some high-speed applications (due to a relatively high mobility factor) and 
applications that use its sensitivity to light and heat such as photodetectors 
and security systems. 

Si: Without question the semiconductor used most frequently for the full range of 

electronic devices. It has the advantage of being readily available at low cost 
and has relatively low reverse saturation currents, good temperature character- 
istics, and excellent breakdown voltage levels. It also benefits from decades of 
enormous attention to the design of large-scale integrated circuits and process- 
ing technology. 

GaAs: Since the early 1990s the interest in GaAs has grown in leaps and bounds, and it 

will eventually take a good share of the development from silicon devices, 
especially in very large scale integrated circuits. Its high-speed characteristics 
are in more demand every day, with the added features of low reverse satura- 
tion currents, excellent temperature sensitivities, and high breakdown voltages. 
More than 80% of its applications are in optoelectronics with the development 
of light-emitting diodes, solar cells, and other photodetector devices, but that 
will probably change dramatically as its manufacturing costs drop and its use 
in integrated circuit design continues to grow; perhaps the semiconductor 
material of the future. 



SEMICONDUCTOR DIODE 19 




Russell Ohl (1898-1987) 

American (Allentown, PA; 
Holmdel, NJ; Vista, CA) Army 
Signal Corps, University of 
Colorado, Westinghouse, AT&T, 
Bell Labs Fellow, Institute of 
Radio Engineers — 1955 
(Courtesy of AT&T Archives 
History Center.) 

Although vacuum tubes were 
used in all forms of communication 
in the 1930s, Russell Ohl was deter- 
mined to demonstrate that the future 
of the field was defined by semicon- 
ductor crystals. Germanium was not 
immediately available for his 
research, so he turned to silicon, and 
found a way to raise its level of 
purity to 99.8%, for which he 
received a patent. The actual discov- 
ery of the p-n junction, as often 
happens in scientific research, was 
the result of a set of circumstances 
that were not planned. On February 
23, 1940, Ohl found that a silicon 
crystal with a crack down the mid- 
dle would produce a significant rise 
in current when placed near a source 
of light. This discovery led to fur- 
ther research, which revealed that 
the purity levels on each side of the 
crack were different and that a 
barrier was formed at the junction 
that allowed the passage of current 
in only one direction — the first 
solid-state diode had been identified 
and explained. In addition, this sen- 
sitivity to light was the beginning of 
the development of solar cells. The 
results were quite instrumental in 
the development of the transistor in 
1945 by three individuals also work- 
ing at Bell Labs. 

FIG. 1.20 



20 



SEMICONDUCTOR 

DIODES 



1 .7 IDEAL VERSUS PRACTICAL 



In the previous section we found that a p-n junction will permit a generous flow of charge 
when forward-biased and a very small level of current when reverse-biased. Both condi- 
tions are reviewed in Fig. 1.21, with the heavy current vector in Fig. 1.21a matching the 
direction of the arrow in the diode symbol and the significantly smaller vector in the oppo- 
site direction in Fig. 1.21b representing the reverse saturation current. 

An analogy often used to describe the behavior of a semiconductor diode is a mechanical 
switch. In Fig. 1.21a the diode is acting like a closed switch permitting a generous flow of 
charge in the direction indicated. In Fig. 1.21b the level of current is so small in most cases 
that it can be approximated as 0 A and represented by an open switch. 











Is 






FIG. 1.21 

Ideal semiconductor diode: (a) forward- 
biased; (b) reverse-biased. 



In other words: 

The semiconductor diode behaves in a manner similar to a mechanical switch in that it 
can control whether current will flow between its two terminals . 

However, it is important to also be aware that: 

The semiconductor diode is different from a mechanical switch in the sense that when 
the switch is closed it will only permit current to flow in one direction . 

Ideally, if the semiconductor diode is to behave like a closed switch in the forward-bias 
region, the resistance of the diode should be 0 12. In the reverse-bias region its resistance 
should be to represent the open-circuit equivalent. Such levels of resistance in the forward- 

and reverse-bias regions result in the characteristics of Fig. 1.22. 




FIG. 1.22 

Ideal versus actual semiconductor characteristics. 



RESISTANCE LEVELS 



21 



The characteristics have been superimposed to compare the ideal Si diode to a real-world 
Si diode. First impressions might suggest that the commercial unit is a poor impression of 
the ideal switch. However, when one considers that the only major difference is that the 
commercial diode rises at a level of 0.7 V rather than 0 V, there are a number of similarities 
between the two plots. 

When a switch is closed the resistance between the contacts is assumed to be 0 ft. At 
the plot point chosen on the vertical axis the diode current is 5 mA and the voltage across 
the diode is 0 V. Substituting into Ohm’s law results in 



In fact: 



_Vd _ 0V 
I D 5 mA 



Oft 



(short-circuit equivalent) 



At any current level on the vertical line , the voltage across the ideal diode is 0 V and 
the resistance is 0 ft. 



For the horizontal section, if we again apply Ohm’s law, we find 
V D 20 V 

Rr = — = = 00 ft (open-circuit equivalent) 

I D 0 mA 

Again: 

Because the current is 0 mA anywhere on the horizontal line , the resistance is 
considered to he infinite ohms (an open-circuit ) at any point on the axis. 

Due to the shape and the location of the curve for the commercial unit in the forward-bias 
region there will be a resistance associated with the diode that is greater than 0 ft. However, 
if that resistance is small enough compared to other resistors of the network in series with 
the diode, it is often a good approximation to simply assume the resistance of the com- 
mercial unit is 0 ft. In the reverse-bias region, if we assume the reverse saturation current 
is so small it can be approximated as 0 mA, we have the same open-circuit equivalence 
provided by the open switch. 

The result, therefore, is that there are sufficient similarities between the ideal switch and 
the semiconductor diode to make it an effective electronic device. In the next section the 
various resistance levels of importance are determined for use in the next chapter, where 
the response of diodes in an actual network is examined. 



1.8 RESISTANCE LEVELS ^ 

As the operating point of a diode moves from one region to another the resistance of the 
diode will also change due to the nonlinear shape of the characteristic curve. It will be dem- 
onstrated in the next few paragraphs that the type of applied voltage or signal will define the 
resistance level of interest. Three different levels will be introduced in this section, which 
will appear again as we examine other devices. It is therefore paramount that their determi- 
nation be clearly understood. 



DC or Static Resistance 

The application of a dc voltage to a circuit containing a semiconductor diode will result in 
an operating point on the characteristic curve that will not change with time. The resistance 
of the diode at the operating point can be found simply by finding the corresponding levels 
of V D and I D as shown in Fig. 1.23 and applying the following equation: 



(i 



n -Yu 

K D — T 



The dc resistance levels at the knee and below will be greater than the resistance levels 
obtained for the vertical rise section of the characteristics. The resistance levels in the 
reverse-bias region will naturally be quite high. Since ohmmeters typically employ a rela- 
tively constant-current source, the resistance determined will be at a preset current level 
(typically, a few milliamperes). 



22 SEMICONDUCTOR 
DIODES 




Determining the dc resistance of a diode at a 
particular operating point. 



In general , therefore , the higher the current through a diode , the lower is the dc resis- 
tance level. 

Typically, the dc resistance of a diode in the active (most utilized) will range from about 

10 vt to so a 



i] 41V LE 1.3 Determine the dc resistance levels for the diode of Fig. 1.24 at 

a. I D = 2 mA (low level) 

b. I D = 20 mA (high level) 

c. V D = — 10 V (reverse-biased) 




Solution: 

a. At I D = 2 mA, V D = 0.5 V (from the curve) and 

y D 0.5 V _ 
Rd = ~T = = 250 

I D 2 mA 

b. At = 20 mA, V D = 0.8 V (from the curve) and 

Vd 0.8 V 
I D 20 mA 



Rd = — 



40 



SI 



SI 



RESISTANCE LEVELS 23 



c. At V D = — 10 V, I D = —I s = — 1 iulA (from the curve) and 



Rn = — 



Vp 

Id 



10V 
1 julA 



lOMil 



clearly supporting some of the earlier comments regarding the dc resistance levels of a 
diode. 



AC or Dynamic Resistance 

Eq. (1.4) and Example 1.3 reveal that 

the dc resistance of a diode is independent of the shape of the characteristic in the 
region surrounding the point of interest. 

If a sinusoidal rather than a dc input is applied, the situation will change completely. The 
varying input will move the instantaneous operating point up and down a region of the char- 
acteristics and thus defines a specific change in current and voltage as shown in Fig. 1.25. 
With no applied varying signal, the point of operation would be the g-point appearing on 
Fig. 1.25, determined by the applied dc levels. The designation Q-point is derived from the 
word quiescent , which means “still or unvarying.” 




FIG. 1.25 

Defining the dynamic or ac resistance. 



A straight line drawn tangent to the curve through the g-point as shown in Fig. 1.26 
will define a particular change in voltage and current that can be used to determine the ac 
or dynamic resistance for this region of the diode characteristics. An effort should be made 
to keep the change in voltage and current as small as possible and equidistant to either side 
of the g-point. In equation form, 



( 1 . 5 ) 



r d 



A Va 

AC 



where A signifies a finite change in the quantity. 

The steeper the slope, the lower is the value of AV d for the same change in A I d and the 
lower is the resistance. The ac resistance in the vertical-rise region of the characteristic is 
therefore quite small, whereas the ac resistance is much higher at low current levels. 

In general, therefore, the lower the Q-point of operation (smaller current or lower 
voltage), the higher is the ac resistance. 




FIG. 1.26 

Determining the ac resistance at a 
Q-point. 



24 



SEMICONDUCTOR 

DIODES 



EXAMPLE 1.4 



For the characteristics of Fig. 1.27: 



a. Determine the ac resistance at Id - 2 mA. 

b. Determine the ac resistance at I D = 25 mA. 

c. Compare the results of parts (a) and (b) to the dc resistances at each current level. 




FIG. 1.27 

Example 1.4. 



Solution: 

a. For I D = 2 mA, the tangent line at I D = 2 mA was drawn as shown in Fig. 1.27 and a 
swing of 2 mA above and below the specified diode current was chosen. At I D = 4 mA, 
V D = 0.76 V, and at I D = 0 mA, V D = 0.65 V. The resulting changes in current and 
voltage are, respectively, 

A I d = 4 mA - 0 mA = 4 mA 
and AV d = 0.76 V - 0.65 V = 0.11 V 

and the ac resistance is 

AV d 0.11 V 



r<i 



= 27.5 n 



A I d 4 mA 

b. For I D = 25 mA, the tangent line at I D = 25 mA was drawn as shown in Fig. 1.27 and 
a swing of 5 mA above and below the specified diode current was chosen. At I D = 30 mA, 
V D = 0.8 V, and at I D = 20 mA, V D = 0.78 V. The resulting changes in current and 
voltage are, respectively, 

A I d = 30 mA - 20 mA = 10 mA 
and AV d = 0.8 V - 0.78 V = 0.02 V 

and the ac resistance is 

AV d 0.02 V 



r<i 



Ah 



10 mA 



= 2il 



c. For I D = 2 mA, V D = 0.7 V and 



Rd = — 



Vd 
Id 

which far exceeds the r d of 27.5 12. 



0.7 V 
2 mA 



= 35012 



RESISTANCE LEVELS 



25 



For I D = 25 mA, V D = 0.79 V and 

_ Vd _ 0.79 V 
R ° ~ I D ~ 25 mA 
which far exceeds the r d of 2 ft. 



31.62 ft 



We have found the dynamic resistance graphically, but there is a basic definition in dif- 
ferential calculus that states: 



The derivative of a function at a point is equal to the slope of the tangent line drawn 
at that point . 

Equation (1.5), as defined by Fig. 1.26, is, therefore, essentially finding the derivative of 
the function at the g-point of operation. If we find the derivative of the general equation 
(1.2) for the semiconductor diode with respect to the applied forward bias and then invert 
the result, we will have an equation for the dynamic or ac resistance in that region. That is, 
taking the derivative of Eq. (1.2) with respect to the applied bias will result in 



d 

dV D 



(Ip) 



f-[Ue v ^ - 1 )] 

dV D 



and 



dip 

dVn 



= —(I D + /,) 
nVj 



after we apply differential calculus. In general, Ip » I s in the vertical- slope section of 
the characteristics and 



dip _ Ip 

dV D nV T 

Flipping the result to define a resistance ratio (R = VII) gives 

dV d YlVj 

dip I D 

Substituting n = 1 and Vj = 26 mV from Example 1 . 1 results in 



rd = 



26 mV 

Ip 



( 1 . 6 ) 



The significance of Eq. (1.6) must be clearly understood. It implies that 

the dynamic resistance can be found simply by substituting the quiescent value of the 
diode current into the equation. 

There is no need to have the characteristics available or to worry about sketching tangent 
lines as defined by Eq. (1.5). It is important to keep in mind, however, that Eq. (1.6) is 
accurate only for values of I D in the vertical-rise section of the curve. For lesser values of 
Ip > n = 2 (silicon) and the value of r d obtained must be multiplied by a factor of 2. For 
small values of I D below the knee of the curve, Eq. (1.6) becomes inappropriate. 

All the resistance levels determined thus far have been defined by the p-n junction and 
do not include the resistance of the semiconductor material itself (called body resistance) 
and the resistance introduced by the connection between the semiconductor material and the 
external metallic conductor (called contact resistance). These additional resistance levels 
can be included in Eq. (1.6) by adding a resistance denoted r B \ 



, 26 mV 

rd = — T + r B 

l D 



ohms 



( 1 . 7 ) 



The resistance r' d , therefore, includes the dynamic resistance defined by Eq. (1.6) and 
the resistance r B just introduced. The factor r B can range from typically 0.1 12 for high- 
power devices to 2 12 for some low-power, general-purpose diodes. For Example 1.4 the ac 
resistance at 25 mA was calculated to be 2 12. Using Eq. (1.6), we have 



26 mV 

Ip 



26 mV 
25 mA 



1.04 a 



rd = 



26 



SEMICONDUCTOR 

DIODES 



The difference of about 1 II could be treated as the contribution of r B . 

For Example 1.4 the ac resistance at 2 mA was calculated to be 27.5 12. Using Eq. (1.6) 
but multiplying by a factor of 2 for this region (in the knee of the curve n = 2), 

/ 26 mV \ / 26 mV \ 

* = <nr) = 2 Eii:J = 2<13n) = “ n 

The difference of 1.5 12 could be treated as the contribution due to r B . 

In reality, determining r d to a high degree of accuracy from a characteristic curve using Eq. 
(1 .5) is a difficult process at best and the results have to be treated with skepticism. At low lev- 
els of diode current the factor r B is normally small enough compared to r d to permit ignoring 
its impact on the ac diode resistance. At high levels of current the level of r B may approach that 
of r d , but since there will frequently be other resistive elements of a much larger magnitude in 
series with the diode, we will assume in this book that the ac resistance is determined solely 
by r d , and the impact of r B will be ignored unless otherwise noted. Technological improve- 
ments of recent years suggest that the level of r B will continue to decrease in magnitude and 
eventually become a factor that can certainly be ignored in comparison to r d . 

The discussion above centered solely on the forward-bias region. In the reverse-bias 
region we will assume that the change in current along the I s line is nil from 0 V to the 
Zener region and the resulting ac resistance using Eq. (1.5) is sufficiently high to permit 
the open-circuit approximation. 

Typically, the ac resistance of a diode in the active region will range from about 1 12 to 100 12. 

Average AC Resistance 

If the input signal is sufficiently large to produce a broad swing such as indicated in Fig. 
1.28, the resistance associated with the device for this region is called the average ac resis- 
tance. The average ac resistance is, by definition, the resistance determined by a straight 
line drawn between the two intersections established by the maximum and minimum values 
of input voltage. In equation form (note Fig. 1.28), 



SV d 




1 ^ 

<1 

II 


pt. to pt. 



For the situation indicated by Fig. 1.28, 

A I d = 17 mA — 2 mA = 15 mA 




FIG. 1.28 

Determining the average ac resistance between indicated limits. 



and 

with 



AV d = 0.725 V - 0.65 V = 0.075 V 



AV d 0.075 V 



= 5il 



dV M d 15 mA 

If the ac resistance (r d ) were determined at I D = 2 mA, its value would be more than 5 12, 
and if determined at 17 mA, it would be less. In between, the ac resistance would make the 
transition from the high value at 2 mA to the lower value at 17 mA. Equation (1.7) defines 
a value that is considered the average of the ac values from 2 mA to 17 mA. The fact that 
one resistance level can be used for such a wide range of the characteristics will prove quite 
useful in the definition of equivalent circuits for a diode in a later section. 



As with the dc and ac resistance levels , the lower the level of currents used to determine 
the average resistance , the higher is the resistance level. 



DIODE EQUIVALENT 27 
CIRCUITS 



Summary Table 

Table 1.6 was developed to reinforce the important conclusions of the last few pages and 
to emphasize the differences among the various resistance levels. As indicated earlier, the 
content of this section is the foundation for a number of resistance calculations to be per- 
formed in later sections and chapters. 



TABLE 1.6 

Resistance Levels 



Type 



Special Graphical 

Equation Characteristics Determination 



DC or static 



Rd = 



Vd 

Id 



Defined as a point on the 
characteristics 




/ 



V D 



AC or dynamic 




Average ac 



A Vd 
A h 



pt. to pt. 



Defined by a straight 
line between limits of 
operation 







1 .9 DIODE EQUIVALENT CIRCUITS ^ 

An equivalent circuit is a combination of elements properly chosen to best represent the 
actual terminal characteristics of a device or system in a particular operating region. 

In other words, once the equivalent circuit is defined, the device symbol can be removed 
from a schematic and the equivalent circuit inserted in its place without severely affecting 
the actual behavior of the system. The result is often a network that can be solved using 
traditional circuit analysis techniques. 



28 



SEMICONDUCTOR 

DIODES 



Piecewise-Linear Equivalent Circuit 

One technique for obtaining an equivalent circuit for a diode is to approximate the charac- 
teristics of the device by straight-line segments, as shown in Fig. 1.29. The resulting equiv- 
alent circuit is called a piecewise-linear equivalent circuit. It should be obvious from Fig. 
1.29 that the straight-line segments do not result in an exact duplication of the actual char- 
acteristics, especially in the knee region. However, the resulting segments are sufficiently 
close to the actual curve to establish an equivalent circuit that will provide an excellent first 
approximation to the actual behavior of the device. For the sloping section of the equiva- 
lence the average ac resistance as introduced in Section 1.8 is the resistance level appearing 
in the equivalent circuit of Fig. 1.28 next to the actual device. In essence, it defines the resis- 
tance level of the device when it is in the “on” state. The ideal diode is included to establish 
that there is only one direction of conduction through the device, and a reverse-bias condi- 
tion will result in the open-circuit state for the device. Since a silicon semiconductor diode 
does not reach the conduction state until V D reaches 0.7 V with a forward bias (as shown in 
Fig. 1.29), a battery V K opposing the conduction direction must appear in the equivalent 
circuit as shown in Fig. 1.30. The battery simply specifies that the voltage across the device 
must be greater than the threshold battery voltage before conduction through the device in 
the direction dictated by the ideal diode can be established. When conduction is established 
the resistance of the diode will be the specified value of r av . 




circuit using straight-line segments to approximate 
the characteristic curve. 




-jHI Hvw- 

0.7 V 10 n 



/Ideal diode 






FIG. 1.30 

Components of the piecewise-linear equivalent circuit. 



Keep in mind, however, that V K in the equivalent circuit is not an independent voltage 
source. If a voltmeter is placed across an isolated diode on the top of a laboratory bench, a 
reading of 0.7 V will not be obtained. The battery simply represents the horizontal offset of 
the characteristics that must be exceeded to establish conduction. 

The approximate level of r av can usually be determined from a specified operating 
point on the specification sheet (to be discussed in Section 1.10). For instance, for a sili- 
con semiconductor diode, if If — 10 mA (a forward conduction current for the diode) at 




29 



V D = 0.8 V, we know that for silicon a shift of 0.7 V is required before the characteristics 
rise, and we obtain 

_ A Va 
rav A l d 

as obtained for Fig. 1.29. 

If the characteristics or specification sheet for a diode is not available the resistance r av 
can be approximated by the ac resistance r d . 



0.8 V - 0.7 V 



0.1 V 



10 mA -0 mA 10 mA 



io a 



Simplified Equivalent Circuit 

For most applications, the resistance r av is sufficiently small to be ignored in comparison to 
the other elements of the network. Removing r av from the equivalent circuit is the same as 
implying that the characteristics of the diode appear as shown in Fig. 1.31. Indeed, this 
approximation is frequently employed in semiconductor circuit analysis as demonstrated in 
Chapter 2. The reduced equivalent circuit appears in the same figure. It states that a forward- 
biased silicon diode in an electronic system under dc conditions has a drop of 0.7 V across 
it in the conduction state at any level of diode current (within rated values, of course). 



■ Id 














+ 


Vd 


- 




^r av = 0 Q 




V K = 0.7 V 








o 




o 






Id 




^ Ideal diode 



0 V K = 0.7 V 



DIODE EQUIVALENT 
CIRCUITS 



FIG. 1.31 

Simplified equivalent circuit for the silicon semiconductor diode. 

Ideal Equivalent Circuit 

Now that r av has been removed from the equivalent circuit, let us take the analysis a step 
further and establish that a 0.7- V level can often be ignored in comparison to the applied 
voltage level. In this case the equivalent circuit will be reduced to that of an ideal diode as 
shown in Fig. 1.32 with its characteristics. In Chapter 2 we will see that this approximation 
is often made without a serious loss in accuracy. 

“ l D 




0 



Vd 



FIG. 1.32 

Ideal diode and its characteristics. 

In industry a popular substitution for the phrase “diode equivalent circuit” is diode model — 
a model by definition being a representation of an existing device, object, system, and so on. 
In fact, this substitute terminology will be used almost exclusively in the chapters to follow. 

Summary Table 

For clarity, the diode models employed for the range of circuit parameters and applications 
are provided in Table 1.7 with their piecewise-linear characteristics. Each will be investi- 
gated in greater detail in Chapter 2. There are always exceptions to the general rule, but it 





30 



SEMICONDUCTOR 

DIODES 



TABLE 1.7 

Diode Equivalent Circuits ( Models ) 



Type 


Conditions 


Model 


Characteristics 




Piecewise-linear model 




o-^iIf^vw — H — ? 

Ideal 

diode 






jr av 






0 


V K 


Vd 










h 






Simplified model 


^network '^ > ^av 


Mi b.i 










V K Idea] 

diode 


0 


\ 




Vd 










■ 4> 






Ideal device 


^network ■^ > ^av 
^network » VfC 














0 PI 3 

Ideal 

diode 


O' 





is fairly safe to say that the simplified equivalent model will be employed most frequently 
in the analysis of electronic systems, whereas the ideal diode is frequently applied in the 
analysis of power supply systems where larger voltages are encountered. 

1.10 TRANSITION AND DIFFUSION CAPACITANCE ^ 

It is important to realize that: 

Every electronic or electrical device is frequency sensitive. 

That is, the terminal characteristics of any device will change with frequency. Even the 
resistance of a basic resistor, as of any construction, will be sensitive to the applied fre- 
quency. At low to mid-frequencies most resistors can be considered fixed in value. How- 
ever, as we approach high frequencies, stray capacitive and inductive effects start to play a 
role and will affect the total impedance level of the element. 

For the diode it is the stray capacitance levels that have the greatest effect. At low frequen- 
cies and relatively small levels of capacitance the reactance of a capacitor, determined by 
X c = 1 / 2irfC , is usually so high it can be considered infinite in magnitude, represented by 
an open circuit, and ignored. At high frequencies, however, the level of X c can drop to the 
point where it will introduce a low-reactance “shorting” path. If this shorting path is across 
the diode, it can essentially keep the diode from affecting the response of the network. 

In the p-n semiconductor diode, there are two capacitive effects to be considered. Both 
types of capacitance are present in the forward- and reverse-bias regions, but one so out- 
weighs the other in each region that we consider the effects of only one in each region. 

Recall that the basic equation for the capacitance of a parallel-plate capacitor is defined by 
C = eA/d , where e is the permittivity of the dielectric (insulator) between the plates of area A 
separated by a distance d. In a diode the depletion region (free of carriers) behaves essentially 
like an insulator between the layers of opposite charge. Since the depletion width (d) will in- 
crease with increased reverse-bias potential, the resulting transition capacitance will decrease, 
as shown in Fig. 1.33. The fact that the capacitance is dependent on the applied reverse-bias 
potential has application in a number of electronic systems. In fact, in Chapter 16 the varactor 
diode will be introduced whose operation is wholly dependent on this phenomenon. 

This capacitance, called the transition ( C T ), barriers, or depletion region capacitance, is 
determined by 



C(0) 

(i + 1 v R /v K \r 



( 1 . 9 ) 




FIG. 1.33 

Transition and diffusion capacitance versus applied bias for a silicon diode. 



REVERSE RECOVERY 31 
TIME 



where C(0) is the capacitance under no-bias conditions and V R is the applied reverse bias 
potential. The power n is Vi or l A depending on the manufacturing process for the diode. 

Although the effect described above will also be present in the forward-bias region, it 
is overshadowed by a capacitance effect directly dependent on the rate at which charge is 
injected into the regions just outside the depletion region. The result is that increased levels 
of current will result in increased levels of diffusion capacitance (C D ) as demonstrated by 
the following equation: 




( 1 . 10 ) 



where r T is the minority carrier lifetime — the time is world take for a minority carrier such 
as a hole to recombine with an electron in the n-type material. However, increased levels 
of current result in a reduced level of associated resistance (to be demonstrated shortly), 
and the resulting time constant (t = RC), which is very important in high-speed applica- 
tions, does not become excessive. 

In general, therefore, 

the transition capacitance is the predominant capacitive effect in the reverse-bias 
region whereas the diffusion capacitance is the predominant capacitive effect in the 
forward-bias region . 

The capacitive effects described above are represented by capacitors in parallel with the 
ideal diode, as shown in Fig. 1.34. For low- or mid-frequency applications (except in the 
power area), however, the capacitor is normally not included in the diode symbol. 



o 




6 



FIG. 1.34 

Including the effect of the transition 
or diffusion capacitance on the 
semiconductor diode. 



1.11 REVERSE RECOVERY TIME ^ 

There are certain pieces of data that are normally provided on diode specification sheets 
provided by manufacturers. One such quantity that has not been considered yet is the 
reverse recovery time, denoted by t rr . In the forward-bias state it was shown earlier that 
there are a large number of electrons from the n-type material progressing through the 
/7-type material and a large number of holes in the n-type material — a requirement for con- 
duction. The electrons in the /7-type material and holes progressing through the n-type 
material establish a large number of minority carriers in each material. If the applied volt- 
age should be reversed to establish a reverse-bias situation, we would ideally like to see the 
diode change instantaneously from the conduction state to the nonconduction state. How- 
ever, because of the large number of minority carriers in each material, the diode current 
will simply reverse as shown in Fig. 1.35 and stay at this measurable level for the period of 
time t s (storage time) required for the minority carriers to return to their majority-carrier 
state in the opposite material. In essence, the diode will remain in the short-circuit state 
with a current / rev erse determined by the network parameters. Eventually, when this storage 
phase has passed, the current will be reduced in level to that associated with the nonconduc- 
tion state. This second period of time is denoted by t t (transition interval). The reverse recov- 
ery time is the sum of these two intervals: t rr = t s + t t . This is an important consideration in 



32 SEMICONDUCTOR 
DIODES 



^forward 


A) 


Change of state (on — ► off) 
/ applied at t = t\ 






i 

Desired response 


J 




h 


t 


reverse 




ts Hr* tf ► 
p Cr H 



FIG. 1.35 

Defining the reverse recovery time. 



high-speed switching applications. Most commercially available switching diodes have a 
t rr in the range of a few nanoseconds to 1 /jl s. Units are available, however, with a t rr of 
only a few hundred picoseconds (10 -12 s). 



1.12 DIODE SPECIFICATION SHEETS ^ 

Data on specific semiconductor devices are normally provided by the manufacturer in one 
of two forms. Most frequently, they give a very brief description limited to perhaps one 
page. At other times, they give a thorough examination of the characteristics using graphs, 
artwork, tables, and so on. In either case, there are specific pieces of data that must be 
included for proper use of the device. They include: 

1 . The forward voltage V F (at a specified current and temperature) 

2. The maximum forward current I F (at a specified temperature) 

3. The reverse saturation current I R (at a specified voltage and temperature) 

4. The reverse- voltage rating [PIV or PRV or V(BR), where BR comes from the term 
“breakdown” (at a specified temperature)] 

5. The maximum power dissipation level at a particular temperature 

6. Capacitance levels 

7. Reverse recovery time t rr 

8. Operating temperature range 

Depending on the type of diode being considered, additional data may also be provided, 
such as frequency range, noise level, switching time, thermal resistance levels, and peak 
repetitive values. For the application in mind, the significance of the data will usually be 
self-apparent. If the maximum power or dissipation rating is also provided, it is understood 
to be equal to the following product: 



P Dmax — Vd^D 



( 1 . 11 ) 



where Id and V D are the diode current and voltage, respectively, at a particular point of 
operation. 

If we apply the simplified model for a particular application (a common occurrence), we 
can substitute V D = V T = 0.7 V for a silicon diode in Eq. (1.11) and determine the resulting 
power dissipation for comparison against the maximum power rating. That is, 



^dissipated — (0-7 V)//) 



( 1 . 12 ) 



The data provided for a high-voltage/low-leakage diode appear in Figs. 1.36 and 1 .37. This 
example would represent the expanded list of data and characteristics. The term rectifier is 
applied to a diode when it is frequently used in a rectification process, described in Chapter 2. 

Specific areas of the specification sheet are highlighted in blue, with letters correspond- 
ing to the following description: 

A The data sheet highlights the fact that the silicon high-voltage diode has a minimum 
reverse-bias voltage of 125 V at a specified reverse-bias current. 



O ffi 



B Note the wide range of temperature operation. Always be aware that data sheets typi- DIODE SPECIFICATION 33 
cally use the centigrade scale, with 200°C = 392°F and -65°C = -85°F. SHEETS 

C The maximum power dissipation level is given by P D = V D I D — 500 mW = 0.5 W. 

The effect of the linear derating factor of 3.33 mW/°C is demonstrated in Fig. 1.37a. 

Once the temperature exceeds 25 °C the maximum power rating will drop by 3.33 mW 
for each 1°C increase in temperature. At a temperature of 100°C, which is the boiling 
point of water, the maximum power rating has dropped to one half of its original value. 

An initial temperature of 25 °C is typical inside a cabinet containing operating elec- 
tronic equipment in a low-power situation. 

D The maximum sustainable current is 500 mA. The plot of Fig. 1.37b reveals that the 
forward current at 0.5 V is about 0.01 mA, but jumps to 1 mA (100 times greater) at 
about 0.65 V. At 0.8 V the current is more than 10 mA, and just above 0.9 V it is close 



A 



B 



C 



D 



E 



F 



DIFFUSED SILICON PLANAR 



• BV ... 125 V (MIN) @ 100 pA (BAY73) 
ABSOLUTE MAXIMUM RATINGS (Note 1) 



Temperatures 



Storage Temperature Range 

Maximum Junction Operating Temperature 

Lead Temperature 


— 65°C to +200°C 
+175^ 
+260°C 


Power Dissipation (Note 2) 


Maximum Total Power Dissipation at 25°C Ambient 
Linear Power Derating Factor (from 25 °C) 


500 mW 
3.33 mW/'C 



Maximum Voltage and Currents 



WIV 


Working Inverse Voltage BAY73 


100 V 


lo 


Average Rectified Current 


200 mA 


h 


Continuous Forward Current 


500 mA 


if 


Peak Repetitive Forward Current 


600 mA 


*f (surge) 


Peak Forward Surge Current 
Pulse Width = 1 s 
Pulse Width = 1 ps 


1.0 A 

4.0 A 



DO-35 OUTLINE 



0 . 02 1 ( 0 . 533 ) 
0 . 019 ( 0 . 483 ) 



I 

I 






( 25.4 

1 



I 

I 



IU 



NOTES: 

Copper clad steel leads, tin plated 
Gold plated leads available 
Hermetically sealed glass package 
Package weight is 0. 1 4 gram 



ELECTRICAL CHARACTERISTICS (25°C Ambient Temperature unless otherwise noted) 



SYMBOL 



CHARACTERISTIC 



BAY73 



MIN 



MAX 



V 



Forward Voltage 



0.85 

0.81 

0.78 

0.69 

0.67 

0.60 



1.00 

0.94 

0.88 

0.80 

0.75 

0.68 



UNITS 



V 

V 

V 

V 

V 

V 



TEST CONDITIONS 



I F = 200 mA 
I F = 100 mA 
I F = 50 mA 
I F = 10 mA 
I F = 5.0 mA 
I F = 1.0 mA 



I R Reverse Current 



500 

1.0 

0.2 

0.5 



nA 

gA 

nA 

nA 



V R = 20 V,T a = 125°C 
V R = 100 V, T a = 125°C 
V R = 20 V, T a = 25°C 
V R = 100 V, T a = 25°C 



BV Breakdown Voltage 

- C Capac i t ance 

-t^ Reverse Recovery Time 



125 



5.0 

TO 



pF 

ps 



I R = 100 pA 

V R = 0, f = 1.0 MHz 

I F - 10 mA, V R - 35 V 
R L = 1.0 to 100 kQ 
C L = lOpF, JAN 256 



NOTES 

1 These ratings are limiting values above which the serviceability of the diode may be impaired. 

2 These are steady state limits. The factory should be consulted on applications involving pulses or low duty-cycle operation. 



FIG. 1.36 

Electrical characteristics of a high-voltage, low-leakage diode. 




Reverse current - nA P D - Power dissipation - mW 



POWER DERATING CURVE 




T a - Ambient temperature - °C 

(a) 



FORWARD VOLTAGE VERSUS 
FORWARD CURRENT 




(b) 



REVERSE VOLTAGE VERSUS 
REVERSE CURRENT 




(c) 



REVERSE CURRENT VERSUS 
TEMPERATURE 




T a - Ambient temperature - °C 

(d) 



CAPACITANCE VERSUS 
REVERSE VOLTAGE 




& 

U 

I 

U 



Vr- Reverse voltage - volts 
(e) 



DYNAMIC IMPEDANCE VERSUS 
FORWARD CURRENT 




(f) 



FIG. 1.37 

Terminal characteristics of a high-voltage diode. 



to 100 mA. The curve of Fig. 1.37b certainly looks nothing like the characteristic 
curves appearing in the last few sections. This is a result of using a log scale for the 
current and a linear scale for the voltage. 

Log scales are often used to provide a broader range of values for a variable in a 
limited amount of space. 

If a linear scale was used for the current, it would be impossible to show a range 
of values from 0.01 mA to 1000 mA. If the vertical divisions were in 0.01-mA incre- 
ments, it would take 100,000 equal intervals on the vertical axis to reach 1000 mA. For 
the moment recognize that the voltage level at given levels of current can be found by 
using the intersection with the curve. For vertical values above a level such as 1.0 mA, 
the next level is 2 mA, followed by 3 mA, 4 mA, and 5 mA. The levels of 6 mA to 10 mA 
can be determined by simply dividing the distance into equal intervals (not the true 
distribution, but close enough for the provided graphs). For the next level it would be 
10 mA, 20 mA, 30 mA, and so on. The graph of Fig. 1.37b is called a semi-log plot to 
reflect the fact that only one axis uses a log scale. A great deal more will be said about 
log scales in Chapter 9. 

E The data provide a range of V F (forward-bias voltages) for each current level. The 
higher the forward current, the higher is the applied forward bias. At 1 mA we find V F 
can range from 0.6 V to 0.68 V, but at 200 mA it can be as high as 0.85 V to 1.00 V. 
For the full range of current levels with 0.6 V at 1 mA and 0.85 V at 200 mA it is cer- 
tainly a reasonable approximation to use 0.7 V as the average value. 

F The data provided clearly reveal how the reverse saturation current increases with 
applied reverse bias at a fixed temperature. At 25 °C the maximum reverse-bias cur- 
rent increases from 0.2 nA to 0.5 nA due to an increase in reverse-bias voltage by the 
same factor of 5. At 125°C it jumps by a factor of 2 to the high level of 1 pi A. Note the 



extreme change in reverse saturation current with temperature as the maximum cur- 
rent rating jumps from 0.2 nA at 25 °C to 500 nA at 125°C (at a fixed reverse-bias 
voltage of 20 V). A similar increase occurs at a reverse-bias potential of 100 V. The 
semi-log plots of Figs. 1.37c and 1.37d provide an indication of how the reverse satu- 
ration current changes with changes in reverse voltage and temperature. At first 
glance Fig. 1.37c might suggest that the reverse saturation current is fairly steady for 
changes in reverse voltage. However, this can sometimes be the effect of using a log 
scale for the vertical axis. The current has actually changed from a level of 0.2 nA to 
a level of 0.7 nA for the range of voltages representing a change of almost 6 to 1 . The 
dramatic effect of temperature on the reverse saturation current is clearly displayed in 
Fig. 1.37d. At a reverse-bias voltage of 125 V the reverse-bias current increases from 
a level of about 1 nA at 25°C to about 1 /iA at 150°C, an increase of a factor of 1000 
over the initial value. 

Temperature and applied reverse bias are very important factors in designs sensitive 
to the reverse saturation current. 

G As shown in the data listing and on Fig. 1.37e, the transition capacitance at a reverse- 
bias voltage of 0 V is 5 pF at a test frequency of 1 MHz. Note the severe change in 
capacitance level as the reverse-bias voltage is increased. As mentioned earlier, this 
sensitive region can be put to good use in the design of a device (Varactor; Chapter 16) 
whose terminal capacitance is sensitive to the applied voltage. 

H The reverse recovery time is 3 /is for the test conditions shown. This is not a fast time 
for some of the current high-performance systems in use today. However, for a variety 
of low- and mid-frequency applications it is acceptable. 

The curves of Fig. 1 .37f provide an indication of the magnitude of the ac resistance of the 
diode versus forward current. Section 1.8 clearly demonstrated that the dynamic resistance 
of a diode decreases with increase in current. As we go up the current axis of Fig. 1.37f it 
is clear that if we follow the curve, the dynamic resistance will decrease. At 0.1 mA it is 
close to 1 kfl; at 10 mA, 10 12; and at 100 mA, only 1 12; this clearly supports the earlier 
discussion. Unless one has had experience reading log scales, the curve is challenging to 
read for levels between those indicated because it is a log-log plot. Both the vertical axis 
and the horizontal axis employ a log scale. 

The more one is exposed to specification sheets, the “friendlier” they will become, es- 
pecially when the impact of each parameter is clearly understood for the application under 
investigation. 



1.11 SEMICONDUCTOR DIODE NOTATION ^ 

The notation most frequently used for semiconductor diodes is provided in Fig. 1.38. For 
most diodes any marking such as a dot or band, as shown in Fig. 1.38, appears at the cath- 
ode end. The terminology anode and cathode is a carryover from vacuum-tube notation. 
The anode refers to the higher or positive potential, and the cathode refers to the lower or 
negative terminal. This combination of bias levels will result in a forward-bias or “on” 
condition for the diode. A number of commercially available semiconductor diodes appear 
in Fig. 1.39. 



Anode 

P_ 

n 

Cathode 



3E 




/Or •, K, etc. 



. 



SEMICONDUCTOR DIODE 
NOTATION 




FIG. 1.38 

Semiconductor diode notation. 










Flat chip surface mount diode 




Power diode 



FIG. 1.39 

Various types of junction diodes. 




Power (disc, puck) diode 




FIG. 1.40 

Digital display meter. ( Courtesy of 
B&K Precision Corporation .) 



1-14 DIODE TESTING ^ 

The condition of a semiconductor diode can be determined quickly using (1) a digital dis- 
play meter (DDM) with a diode checking function, (2) the ohmmeter section of a multime- 
ter, or (3) a curve tracer. 

Diode Checking Function 

A digital display meter with a diode checking capability appears in Fig. 1.40. Note the 
small diode symbol at the top right of the rotating dial. When set in this position and 
hooked up as shown in Fig. 1.41a, the diode should be in the “on” state and the display will 
provide an indication of the forward-bias voltage such as 0.67 V (for Si). The meter has an 
internal constant-current source (about 2 mA) that will define the voltage level as indicated 
in Fig. 1.41b. An OL indication with the hookup of Fig. 1.41a reveals an open (defective) 
diode. If the leads are reversed, an OL indication should result due to the expected open- 
circuit equivalence for the diode. In general, therefore, an OL indication in both directions 
is an indication of an open or defective diode. 



Red lead 
(VQ) 



I Black lead 
(COM) 



(a) 




FIG. 1.41 

Checking a diode in the forward-bias state. 



36 



Ohmmeter Testing 

In Section 1.8 we found that the forward-bias resistance of a semiconductor diode is quite 
low compared to the reverse-bias level. Therefore, if we measure the resistance of a diode 



using the connections indicated in Fig. 1.42, we can expect a relatively low level. The result- 
ing ohmmeter indication will be a function of the current established through the diode by the 
internal battery (often 1.5 V) of the ohmmeter circuit. The higher the current, the lower is the 
resistance level. For the reverse-bias situation the reading should be quite high, requiring a 
high resistance scale on the meter, as indicated in Fig. 1.42b. A high resistance reading in 
both directions indicates an open (defective-device) condition, whereas a very low resis- 
tance reading in both directions will probably indicate a shorted device. 

Curve Tracer 



DIODE TESTING 37 



Red lead 
(VO) 

+ 



(Ohmmeter) 
Relatively low R 

L 



Black lead 
(COM) 



(a) 



The curve tracer of Fig. 1.43 can display the characteristics of a host of devices, including 
the semiconductor diode. By properly connecting the diode to the test panel at the bottom 
center of the unit and adjusting the controls, one can obtain the display of Fig. 1.44. Note 
that the vertical scaling is 1 mA/div, resulting in the levels indicated. For the horizontal axis 
the scaling is 100 mV/div, resulting in the voltage levels indicated. For a 2-mA level as 
defined for a DDM, the resulting voltage would be about 625 mV = 0.625 V. Although the 
instrument initially appears quite complex, the instruction manual and a few moments of 
exposure will reveal that the desired results can usually be obtained without an excessive 
amount of effort and time. The display of the instrument will appear on more than one occa- 
sion in the chapters to follow as we investigate the characteristics of the variety of devices. 



Black lead 
(COM) 



Relatively high R 



:k lead I 
OM) 

- H — 



Red lead 
(VO) 

+ 



(b) 



FIG. 1.42 

Checking a diode with an 
ohmmeter. 




FIG. 1.43 

Curve tracer. ( © Agilent Technologies , Inc. Reproduced with 
Permission , Courtesy of Agilent Technologies, Inc.) 




0V 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V 



Vertical 
per div. 

1 

mA 



Horizontal 
per div. 

100 

mV 



Per Step 



G°rs m 

per div. 



FIG. 1.44 

Curve tracer response to IN4007 silicon diode. 



38 



SEMICONDUCTOR 

DIODES 



1.15 ZENER DIODES 



The Zener region of Fig. 1.45 was discussed in some detail in Section 1.6. The characteristic 
drops in an almost vertical manner at a reverse-bias potential denoted V z . The fact that 
the curve drops down and away from the horizontal axis rather than up and away for the 
positive- Vo region reveals that the current in the Zener region has a direction opposite to 
that of a forward-biased diode. The slight slope to the curve in the Zener region reveals that 
there is a level of resistance to be associated with the Zener diode in the conduction mode. 

This region of unique characteristics is employed in the design of Zener diodes , which 
have the graphic symbol appearing in Fig. 1.46a. The semiconductor diode and the Zener 
diode are presented side by side in Fig. 1.46 to ensure that the direction of conduction of 
each is clearly understood together with the required polarity of the applied voltage. For 
the semiconductor diode the “on” state will support a current in the direction of the arrow 
in the symbol. For the Zener diode the direction of conduction is opposite to that of the 
arrow in the symbol, as pointed out in the introduction to this section. Note also that the 
polarity of V D and V z are the same as would be obtained if each were a resistive element 
as shown in Fig. 1.46c. 



b 






0 






FIG. 1.45 

Reviewing the Zener region. 




(a) (b) (c) 

FIG. 1.46 

Conduction direction: (a) Zener diode; 
(b) semiconductor diode; 

(c) resistive element. 



The location of the Zener region can be controlled by varying the doping levels. An in- 
crease in doping that produces an increase in the number of added impurities, will decrease 
the Zener potential. Zener diodes are available having Zener potentials of 1.8 V to 200 V 
with power ratings from % W to 50 W. Because of its excellent temperature and current 
capabilities, silicon is the preferred material in the manufacture of Zener diodes. 

It would be nice to assume the Zener diode is ideal with a straight vertical line at the 
Zener potential. However, there is a slight slope to the characteristics requiring the piece- 
wise equivalent model appearing in Fig. 1.47 for that region. For most of the applications 
appearing in this text the series resistive element can be ignored and the reduced equivalent 
model of just a dc battery of V z volts employed. Since some applications of Zener diodes 
swing between the Zener region and the forward-bias region, it is important to understand 
the operation of the Zener diode in all regions. As shown in Fig. 1.47, the equivalent model 
for a Zener diode in the reverse-bias region below V z is a very large resistor (as for the 
standard diode). For most applications this resistance is so large it can be ignored and the 
open-circuit equivalent employed. For the forward-bias region the piecewise equivalent is 
the same as described in earlier sections. 

The specification sheet for a 10-V, 500-mW, 20% Zener diode is provided as Table 1.8, 
and a plot of the important parameters is given in Fig. 1.48. The term nominal used in the 
specification of the Zener voltage simply indicates that it is a typical average value. Since this 
is a 20% diode, the Zener potential of the unit one picks out of a lot (a term used to describe a 
package of diodes) can be expected to vary as 10 V + 20%, or from 8 V to 12 V. Both 10% 
and 50% diodes are also readily available. The test current I ZT is the current defined by the 



Temperature coefficient - T c (%/°C) 




FIG. 1.47 

Zener diode characteristics with the equivalent model for each region. 



TABLE 1.8 

Electrical Characteristics (25° C Ambient Temperature ) 



Zener 




Maximum 


Maximum 


Maximum 




Maximum 




Voltage 


Test 


Dynamic 


Knee 


Reverse 


Test 


Regulator 


Typical 


Nominal 


Current 


Impedance 


Impedance 


Current 


Voltage 


Current 


Temperature 


V z 


IzT 


Z Z t at I Z t 


Z/a at I/k 


I R at V R 


Vr 


IzM 


Coefficient 


(V) 


(mA) 


m 


(fl) (mA) 


(M A) 


(V) 


(mA) 


(%/°C) 


10 


12.5 


8.5 


700 0.25 


10 


7.2 


32 


+0.072 



Temperature coefficient ( T c ) 
versus Zener current 



Dynamic impedance (r z ) 
versus Zener current 





I L - L - LJ LJ ^ 

0.1 0.2 0.5 1 2 5 10 20 50 100 

Zener current 7 Z - (mA) 

(b) 



FIG. 1.48 

Electrical characteristics for a 10-V, 500-mW Zener diode. 



39 



40 



SEMICONDUCTOR 

DIODES 



M-power level. It is the current that will define the dynamic resistance Zzr and appears in 
the general equation for the power rating of the device. That is, 



4/ zr y z 



( 1 . 13 ) 



Substituting / ZT into the equation with the nominal Zener voltage results in 
P Zmax = 4/ zr V z = 4(12.5 mA)(10 V) = 500 mW 

which matches the 500-mW label appearing above. For this device the dynamic resistance 
is 8.5 12, which is usually small enough to be ignored in most applications. The maximum 
knee impedance is defined at the center of the knee at a current of / ZK = 0.25 mA. Note 
that in all the above the letter T is used in subscripts to indicate test values and the letter K 
to indicate knee values. For any level of current below 0.25 mA the resistance will only get 
larger in the reverse-bias region. The knee value therefore reveals when the diode will start 
to show very high series resistance elements that one may not be able to ignore in an appli- 
cation. Certainly 500 12 = 0.5 kI2 may be a level that can come into play. At a reverse-bias 
voltage the application of a test voltage of 7.2 V results in a reverse saturation current of 
10 1 ± A, a level that could be of some concern in some applications. The maximum regulator 
current is the maximum continuous current one would want to support in the use of the 
Zener diode in a regulator configuration. Finally, we have the temperature coefficient 
(T c ) in percent per degree centigrade. 

The Zener potential of a Zener diode is very sensitive to the temperature of operation. 

The temperature coefficient can be used to find the change in Zener potential due to a 
change in temperature using the following equation: 



T C = 



A Vz/Vz 
n - t 0 



x ioo%/°c 



(%/° C) 



( 1 . 14 ) 



where T\ is the new temperature level 

Tq is room temperature in an enclosed cabinet (25 °C) 

T c is the temperature coefficient 
and V z is the nominal Zener potential at 25 °C. 

To demonstrate the effect of the temperature coefficient on the Zener potential, consider 
the following example. 



EXAMPLE 1.5 Analyze the 10-V Zener diode described by Table 1.7 if the temperature is 
increased to 100°C (the boiling point of water). 



Solution: 



Substituting into Eq. (1.14), we obtain 
T C V Z 

A V z = -^(74 - Tn) 
z 100% 1 0 

_ (0.072%/°C)(10 V) 

100% 



(100°C 



25°C) 



and AV Z = 0.54 V 

The resulting Zener potential is now 

Vz' = Vz + 0.54 V = 10.54 V 



which is not an insignificant change. 



It is important to realize that in this case the temperature coefficient was positive. For Zener 
diodes with Zener potentials less than 5 V it is very common to see negative temperature 
coefficients, where the Zener voltage drops with an increase in temperature. Figure 1.48a 
provides a plot of T versus Zener current for three different levels of diodes. Note that the 
3.6-V diode has a negative temperature coefficient, whereas the others have positive values. 

The change in dynamic resistance with current for the Zener diode in its avalanche re- 
gion is provided in Fig. 1 .48b. Again, we have a log-log plot, which has to be carefully read. 



Initially it would appear that there is an inverse linear relationship between the dynamic LIGHT- EMITTING DIODES 41 

resistance because of the straight line. That would imply that if one doubles the current, one 

cuts the resistance in half. However, it is only the log-log plot that gives this impression, 

because if we plot the dynamic resistance for the 24-V Zener diode versus current using 

linear scales we obtain the plot of Fig. 1.49, which is almost exponential in appearance. 

Note on both plots that the dynamic resistance at very low currents that enter the knee of 
the curve is fairly high at about 200 12. However, at higher Zener currents, away from the 
knee, at, say 10 mA, the dynamic resistance drops to about 5 12. 




FIG. 1.49 

Zener terminal identification and symbols. 



The terminal identification and the casing for a variety of Zener diodes appear in Fig. 
1.49. Their appearance is similar in many ways to that of the standard diode. Some areas of 
application for the Zener diode will be examined in Chapter 2. 



1.16 LIGHT-EMITTING DIODES ^ 

The increasing use of digital displays in calculators, watches, and all forms of instrumenta- 
tion has contributed to an extensive interest in structures that emit light when properly 
biased. The two types in common use to perform this function are the light-emitting diode 
(LED) and the liquid-crystal display (LCD). Since the LED falls within the family of p-n 
junction devices and will appear in some of the networks of the next few chapters, it will 
be introduced in this chapter. The LCD display is described in Chapter 16. 

As the name implies, the light-emitting diode is a diode that gives off visible or invis- 
ible (infrared) light when energized. In any forward-biased p-n junction there is, within the 
structure and primarily close to the junction, a recombination of holes and electrons. This 
recombination requires that the energy possessed by the unbound free electrons be trans- 
ferred to another state. In all semiconductor p-n junctions some of this energy is given off 
in the form of heat and some in the form of photons. 

In Si and Ge diodes the greater percentage of the energy converted during recombina- 
tion at the junction is dissipated in the form of heat within the structure , and the emitted 
light is insignificant. 

For this reason, silicon and germanium are not used in the construction of LED devices. 
On the other hand: 

Diodes constructed of GaAs emit light in the infrared ( invisible ) zone during the 
recombination process at the p-n junction. 

Even though the light is not visible, infrared LEDs have numerous applications where 
visible light is not a desirable effect. These include security systems, industrial processing, 
optical coupling, safety controls such as on garage door openers, and in home entertainment 
centers, where the infrared light of the remote control is the controlling element. 

Through other combinations of elements a coherent visible light can be generated. Table 1.9 
provides a list of common compound semiconductors and the light they generate. In addi- 
tion, the typical range of forward bias potentials for each is listed. 

The basic construction of an LED appears in Fig. 1.50 with the standard symbol used 
for the device. The external metallic conducting surface connected to the /7-type material is 
smaller to permit the emergence of the maximum number of photons of light energy when 
the device is forward-biased. Note in the figure that the recombination of the injected carri- 
ers due to the forward-biased junction results in emitted light at the site of the recombination. 



42 



SEMICONDUCTOR 

DIODES 



TABLE 1.9 

Light-Emitting Diodes 



Color 


Construction 


Typical Forward 
Voltage (V) 


Amber 


AlInGaP 


2.1 


Blue 


GaN 


5.0 


Green 


GaP 


2.2 


Orange 


GaAsP 


2.0 


Red 


GaAsP 


1.8 


White 


GaN 


4.1 


Yellow 


AlInGaP 


2.1 



There will, of course, be some absorption of the packages of photon energy in the structure 
itself, but a very large percentage can leave, as shown in the figure. 





-o 



(a) 



FIG. 1.50 

(a) Process of electroluminescence in the LED; (b) graphic symbol. 



Just as different sounds have different frequency spectra (high-pitched sounds generally 
have high-frequency components, and low sounds have a variety of low-frequency compo- 
nents), the same is true for different light emissions. 

The frequency spectrum for infrared light extends from about 100 THz (T — tera = 
10 12 ) to 400 THz, with the visible light spectrum extending from about 400 to 750 THz . 

It is interesting to note that invisible light has a lower frequency spectrum than visible 
light. 

In general, when one talks about the response of electroluminescent devices, one refer- 
ences their wavelength rather than their frequency. 

The two quantities are related by the following equation: 




( 1 . 15 ) 



where c = 3 X 10 8 m/s (the speed of light in a vacuum) 
/ = frequency in Hertz 
A = wavelength in meters. 



LIGHT-EMITTING DIODES 



43 



EXAMPLE 1.6 Using Eq. (1.15), find the range of wavelength for the frequency range of 
visible light (400 THz-750 THz). 



Solution: 



oHif 10 9 nm 
c = 3 X 10 8 — 

S HI 

c 3 X 10 17 nm/s 

A = - = 

/ 400 THz 

_ c _ 3 X 10 17 nm/s 

~ f~ 750 THz 

400 nm to 750 nm 



3 X 10 17 nm/s 



3 X 10 17 nm/s 
400 X 10 12 Hz 
3 X 10 17 nm/s 
750 X 10 12 Hz 



750 nm 



400 nm 



Note in the above example the resulting inversion from higher frequency to smaller wave- 
length. That is, the higher frequency results in the smaller wavelength. Also, most charts 
use either nanometers (nm) or angstrom (A) units. One angstrom unit is equal to 10 -10 m. 

The response of the average human eye as provided in Fig. 1.51 extends from about 
350 nm to 800 nm with a peak near 550 nm. 

It is interesting to note that the peak response of the eye is to the color green, with red and 
blue at the lower ends of the bell curve. The curve reveals that a red or a blue LED must 
have a much stronger efficiency than a green one to be visible at the same intensity. In other 
words, the eye is more sensitive to the color green than to other colors. Keep in mind that 
the wavelengths shown are for the peak response of each color. All the colors indicated on 
the plot will have a bell-shaped curve response, so green, for example, is still visible at 600 
nm, but at a lower intensity level. 




FIG. 1.51 

Standard response curve of the human eye, showing the eye’s response to light energy 
peaks at green and falls off for blue and red. 

In Section 1 .4 it was mentioned briefly that GaAs with its higher energy gap of 1 .43 eV 
made it suitable for electromagnetic radiation of visible light, whereas Si at 1 . 1 eV resulted pri- 
marily in heat dissipation on recombination. The effect of this difference in energy gaps can be 



44 



SEMICONDUCTOR 

DIODES 



explained to some degree by realizing that to move an electron from one discrete energy level 
to another requires a specific amount of energy. The amount of energy involved is given by 




( 1 . 16 ) 



with E g = joules (J) [1 eV = 1.6 X 10“ 19 J] 

h = Planck’s constant = 6.626 X 10 -34 J • s. 
c = 3 X 10 8 m/s 
A = wavelength in meters 



If we substitute the energy gap level of 1 .43 eV for GaAs into the equation, we obtain the 
following wavelength: 



and 



1.43 eV 



1.6 X 1 0 1 9 J 
1 eV 



= 2.288 X 10“ 19 J 



hc_ _ (6.626 X 10~ 34 J • s)(3 X 10 8 m/s) 
E s 2.288 X 10" 19 J 



= 869 nm 



For silicon, with E g = 1 . 1 eV 



A = 1130 nm 



which is well beyond the visible range of Fig. 1.51. 

The wavelength of 869 nm places GaAs in the wavelength zone typically used in infrared 
devices. For a compound material such as GaAsP with a band gap of 1.9 eV the resulting 
wavelength is 654 nm, which is in the center of the red zone, making it an excellent com- 
pound semiconductor for LED production. In general, therefore: 



The wavelength and frequency of light of a specific color are directly related to the 
energy hand gap of the material. 



A first step, therefore, in the production of a compound semiconductor that can be used 
to generate light is to come up with a combination of elements that will generate the desired 
energy band gap. 

The appearance and characteristics of a subminiature high-efficiency red LED manufac- 
tured by Hewlett-Packard are given in Fig. 1.52. Note in Fig. 1.52b that the peak forward 
current is 60 mA, with 20 mA the typical average forward current. The text conditions 
listed in Fig. 1.52c, however, are for a forward current of 10 mA. The level of V D under 
forward-bias conditions is listed as V F and extends from 2.2 V to 3 V. In other words, one 
can expect a typical operating current of about 10 mA at 2.3 V for good light emission, as 
shown in Fig. 1.52e. In particular, note the typical diode characteristics for an LED, permit- 
ting similar analysis techniques to be described in the next chapter. 

Two quantities yet undefined appear under the heading Electrical/Optical Characteristics 
at T a = 25 °C. They are the axial luminous intensity ( I v ) and the luminous efficacy (r/y). Light 
intensity is measured in candelas. One candela (cd) corresponds to a light flux of 47 t lumens 
(lm) and is equivalent to an illumination of 1 footcandle on a 1-ft 2 area 1 ft from the light 
source. Even if this description may not provide a clear understanding of the candela as a unit of 
measure, it should be enough to allow its level to be compared between similar devices. Figure 
1.52f is a normalized plot of the relative luminous intensity versus forward current. The term 
normalized is used frequently on graphs to give comparisons of response to a particular level. 

A normalized plot is one where the variable of interest is plotted with a specific level 
defined as the reference value with a magnitude of one. 



In Fig. 1.52f the normalized level is taken at I F = 10 mA. Note that the relative lumi- 
nous intensity is 1 at I F = 10 mA. The graph quickly reveals that the intensity of the light 
is almost doubled at a current of 15 mA and is almost three times as much at a current of 
20 mA. It is important to therefore note that: 

The light intensity of an LED will increase with forward current until a point of 
saturation arrives where any further increase in current will not effectively increase 
the level of illumination. 




Absolute Maximum Ratings at T A = 25°C 



Parameter 


High-Efficiency Red 
4160 


Units 


Power dissipation 


120 


mW 


Average forward current 


20^ 


mA 


Peak forward current 


60 


mA 


Operating and storage temperature range 


— 55°C to 100°C 




Lead soldering temperature 
[1.6 mm (0.063 in.) from body] 


230°C for 3 s 





NOTE: 1. Derate from 50°C at 0.2 mV/°C. 



(b) 



Electrical/Optical Characteristics at T A = 25°C 







High-Efficiency Red 










4160 








Symbol 


Description 


Min. Typ. 


Max. 


Units 


Test Conditions 












I F = 10 mA 


h 


Axial luminous 












intensity 


1.0 3.0 




mcd 




201/2 


Included angle 












between half 
luminous intensity 
points 


80 




degree 


Note 1 


■^•peak 


Peak wavelength 


635 




nm 


Measurement 












at peak 


kd 


Dominant wavelength 


628 




nm 


Note 2 


T s 


Speed of response 


90 




ns 




c 


Capacitance 


11 




pF 


V F = 0;/= 1 Mhz 


Ojc 


Thermal resistance 


120 




°CAV 


Junction to 












cathode lead at 
0.79 mm (0.031 
in.) from body 


Vf 


Forward voltage 


2.2 


3.0 


V 


Ip = 10 mA 


BV r 


Reverse breakdown 












voltage 


5.0 




V 


7r = 100 /jlA 


Vv 


Luminous efficacy 


147 




ImAV 


Note 3 



NOTES: 



1. 0 i /2 is the off-axis angle at which the luminous intensity is half the axial luminous intensity. 

2. The dominant wavelength, X d , is derived from the CIE chromaticity diagram and represents the single 
wavelength that defines the color of the device. 

3. Radiant intensity, I e , in watts/steradian, may be found from the equation I e = I v /r] v , where I v is the 
luminous intensity in candelas and r\ v is the luminous efficacy in lumens/watt. 



FIG. 1.52 

Hewlett-Packard subminiature high- efficiency red solid-state lamp: (a) appearance; (b) absolute maximum ratings; (c) electrical/optical 
characteristics; (d) relative intensity versus wavelength; (e) forward current versus forward voltage; (f) relative luminous intensity 
versus forward current; (g) relative efficiency versus peak current; (h) relative luminous intensity versus angular displacement. 



For instance, note in Fig. 1.52 g that the increase in relative efficiency starts to level off 
as the current exceeds 50 mA. 

The term efficacy is, by definition, a measure of the ability of a device to produce the 
desired effect. For the LED this is the ratio of the number of lumens generated per applied 
watt of electrical power. 

The plot of Fig. 1.52d supports the information appearing on the eye-response curve of 
Fig. 1.51. As indicated above, note the bell-shaped curve for the range of wavelengths that 
will result in each color. The peak value of this device is near 630 nm, very close to the 
peak value of the GaAsP red LED. The curves of green and yellow are only provided for 
reference purposes. 



45 



Relative luminous intensity 
(normalized at 10 mA) 





FIG. 1.52 

Continued. 



Figure 1.52h is a graph of light intensity versus angle measured from 0° (head on) 
to 90° (side view). Note that at 40° the intensity has already dropped to 50% of the 
head-on intensity. 

One of the major concerns when using an LED is the reverse-bias breakdown voltage, 
which is typically between 3 V and 5 V (an occasional device has a 10-V level). 

This range of values is significantly less than that of a standard commercial diode, 
where it can extend to thousands of volts. As a result one has to be acutely aware of this 
severe limitation in the design process. In the next chapter one protective approach will be 
introduced. 

In the analysis and design of networks with LEDs it is helpful to have some idea of the 
voltage and current levels to be expected. 

For many years the only colors available were green, yellow, orange, and red, permitting 
the use of the average values ofVp = 2V and I F = 20 mA for obtaining an approximate 
operating level. 

However, with the introduction of blue in the early 1990s and white in the late 1990s the 
magnitude of these two parameters has changed. For blue the average forward bias voltage 
can be as high as 5 V, and for white about 4.1 V, although both have a typical operating 
current of 20 mA or more. In general, therefore: 

Assume an average forward-bias voltage of 5 V for blue and 4 V for white LEDs at 
currents of 20 mA to initiate an analysis of networks with these types of LEDs. 

Every once in a while a device is introduced that seems to open the door to a slue of 
possibilities. Such is the case with the introduction of white LEDs. The slow start for white 
LEDs is primarily due to the fact that it is not a primary color like green, blue, and red. 
Every other color that one requires, such as on a TV screen, can be generated from these 
three colors (as in virtually all monitors available today). Yes, the right combination of 
these three colors can give white — hard to believe, but it works. The best evidence is the 



46 



human eye, which only has cones sensitive to red, green, and blue. The brain is responsible LIGHT-EMITTING DIODES 47 

for processing the input and perceiving the “white” light and color we see in our everyday 

lives. The same reasoning was used to generate some of the first white LEDs, by combining 

the right proportions of a red, a green, and a blue LED in a single package. Today, however, 

most white LEDs are constructed of a blue gallium nitride LED below a film of yttrium- 

aluminum garnet (YAG) phosphor. When the blue light hits the phosphor, a yellow light is 

generated. The mix of this yellow emission with that of the central blue LED forms a white 

light — incredible, but true. 

Since most of the lighting for homes and offices is white light, we now have another 
option to consider versus incandescent and fluorescent lighting. The rugged characteristics 
of LED white light along with lifetimes that exceed 25,000 hours, clearly suggest that 
this will be a true competitor in the near future. Various companies are now providing 
replacement LED bulbs for almost every possible application. Some have efficacy ratings 
as high as 135.7 lumens per watt, far exceeding the 25 lumens per watt of a few years 
ago. It is forecast that 7 W of power will soon be able to generate 1,000 lm of light, which 
exceeds the illumination of a 60 W bulb and can run off four D cell batteries. Imagine 
the same lighting with less than 1/8 the power requirement. At the present time entire of- 
fices, malls, street lighting, sporting facilities, and so on are being designed using solely 
LED lighting. Recently, LEDs are the common choice for flashlights and many high-end 
automobiles due to the sharp intensity at lower dc power requirements. The tube light of 
Fig. 1.53a replaces the standard fluorescent bulb typically found in the ceiling fixtures of 
both the home and industry. Not only do they draw 20% less energy while providing 25% 
additional light but they also last twice as long as a standard fluorescent bulb. The flood 
light of Fig. 1.53b draws 1.7 watts for each 140 lumens of light resulting in an enormous 
90% savings in energy compared to the incandescent variety. The chandelier bulbs of Fig. 

1.53c have a lifetime of 50,000 hours and only draw 3 watts of power while generating 
200 lumens of light. 




FIG. 1.53 

LED residential and commercial lighting. 



Before leaving the subject, let us look at a seven- segment digital display housed in a 
typical dual in-line integrated circuit package as shown in Fig. 1.54. By energizing the 
proper pins with a typical 5-V dc level, a number of the LEDs can be energized and the 
desired numeral displayed. In Fig. 1.54a the pins are defined by looking at the face of 
the display and counting counterclockwise from the top left pin. Most seven-segment 
displays are either common-anode or common-cathode displays, with the term anode 
referring to the defined positive side of each diode and the cathode referring to the nega- 
tive side. For the common-cathode option the pins have the functions listed in Fig. 1.54b 
and appear as in Fig. 1.54c. In the common-cathode configuration all the cathodes are 
connected together to form a common point for the negative side of each LED. Any LED 
with a positive 5 V applied to the anode or numerically numbered pin side will turn on 
and produce light for that segment. In Fig. 1.54c, 5 V has been applied to the terminals 
that generate the numeral 5. For this particular unit the average forward turn-on voltage 
is 2.1 V at a current of 10 mA. 

Various LED configurations are examined in the next chapter. 



48 SEMICONDUCTOR 
DIODES 




COMMON CATHODE 
PIN # FUNCTION 

1 . Anode f 

2. ANODE g 

3. NO PIN 

4. COMMON CATHODE 

5. NO PIN 

6. ANODE e 

7. ANODE d 

8. ANODE c 

9. ANODE d 

10. NO PIN 

11. NO PIN 

12. COMMON CATHODE 

13. ANODE b 

14. ANODE a 



(a) 



(b) 




(c) 

FIG. 1.54 

Seven-segment display: (a) face with pin idenfication; (b) pin function; (c) displaying the numeral 5. 



I. 17 SUMMARY ^ 

Important Conclusions and Concepts 

1 . The characteristics of an ideal diode are a close match with those of a simple switch 
except for the important fact that an ideal diode can conduct in only one direction. 

2. The ideal diode is a short in the region of conduction and an open circuit in the 
region of nonconduction. 

3. A semiconductor is a material that has a conductivity level somewhere between that 
of a good conductor and that of an insulator. 

4. A bonding of atoms, strengthened by the sharing of electrons between neighboring 
atoms, is called covalent bonding. 

5. Increasing temperatures can cause a significant increase in the number of free elec- 
trons in a semiconductor material. 

6. Most semiconductor materials used in the electronics industry have negative tem- 
perature coefficients; that is, the resistance drops with an increase in temperature. 

7. Intrinsic materials are those semiconductors that have a very low level of impurities, 
whereas extrinsic materials are semiconductors that have been exposed to a doping 
process. 

8. An n - type material is formed by adding donor atoms that have five valence electrons 
to establish a high level of relatively free electrons. In an ft-type material, the electron 
is the majority carrier and the hole is the minority carrier. 

9. A /7-type material is formed by adding acceptor atoms with three valence electrons to 
establish a high level of holes in the material. In a /7-type material, the hole is the 
majority carrier and the electron is the minority carrier. 

10. The region near the junction of a diode that has very few carriers is called the deple- 
tion region. 

II. In the absence of any externally applied bias, the diode current is zero. 

12. In the forward-bias region the diode current increases exponentially with increase in 
voltage across the diode. 






13. In the reverse-bias region the diode current is the very small reverse saturation cur- COMPUTER ANALYSIS 49 
rent until Zener breakdown is reached and current will flow in the opposite direction 

through the diode. 

14. The reverse saturation current I s will just about double in magnitude for every 10-fold 
increase in temperature. 

15. The dc resistance of a diode is determined by the ratio of the diode voltage and cur- 
rent at the point of interest and is not sensitive to the shape of the curve. The dc resis- 
tance decreases with increase in diode current or voltage. 

16. The ac resistance of a diode is sensitive to the shape of the curve in the region of inter- 
est and decreases for higher levels of diode current or voltage. 

17. The threshold voltage is about 0.7 V for silicon diodes and 0.3 V for germanium diodes. 

18. The maximum power dissipation level of a diode is equal to the product of the diode 
voltage and current. 

19. The capacitance of a diode increases exponentially with increase in the forward-bias 
voltage. Its lowest levels are in the reverse-bias region. 

20. The direction of conduction for a Zener diode is opposite to that of the arrow in the 
symbol, and the Zener voltage has a polarity opposite to that of a forward-biased diode. 

21. Light emitting diodes (LEDs) emit light under forward-bias conditions but require 2 
V to 4 V for good emission. 



Equations 

b = Ue VD/nVT ~ 1 ) 



V K = 0.7 V (Si) 

V K = 1.2 V (GaAs) 

V K = 0.3 V (Ge) 

V D 

r d = y 

AVg _ 26 mV 

~Afd~ h 

AVd 

Al d 
V D I D 



>'d 



r av 



pt. to pt. 




T K = T c + 273° 



k = 1.38 X 10 _23 J/K 



1.18 COMPUTER ANALYSIS ^ 

Two software packages designed to analyze electronic circuits will be introduced and applied 
throughout the text. They include Cadence OrCAD, version 16.3 (Fig. 1.55), and Multi- 
sim, version 11.0.1 (Fig. 1.56). The content was written with sufficient detail to ensure that 
the reader will not need to reference any other computer literature to apply both programs. 




FIG. 1.55 

Cadence OrCAD Design package version 16.3. 
(Photo by Dan Trudden/Pearson.) 



FIG. 1.56 

Multisim 11.0.1. 

(Photo by Dan Trudden/Pearson.) 





50 SEMICONDUCTOR 
DIODES 


Those of you who have used either program in the past will find that the changes are minor 
and appear primarily in the front end and in the generation of specific data and plots. 

The reason for including two programs stems from the fact that both are used throughout 
the educational community. You will find that the OrCAD software has a broader area of 
investigation but the Multisim software generates displays that are a better match to the 
actual laboratory experience. 

The demo version of OrCAD is free from Cadence Design Systems, Inc., and can be 
downloaded directly from the EM A Design Automation, Inc., web site, info@emaeda.com. 
Multisim must be purchased from the National Instruments Corporation using their web 

site, ni.com/multisim. 

In previous editions, the OrCAD package was referred to as a PSpice program primarily 
because it is a subset of a more sophisticated version used extensively in industry called 
SPICE. The result is the use of the term PSpice in the descriptions to follow when initiating 
an analysis using the OrCAD software. 

The downloading process for each software package will now be introduced along with 
the general appearance of the resulting screen. 

OrCAD 

Installation: 

Insert the OrCAD Release 16.3 DVD into the disk drive to open the Cadence OrCAD 
16.3 software screen. 

Select Demo Installation and the Preparing Setup dialog box will open, followed by 
the message Welcome to the Installation Wizard for OrCAD 16.3 Demo. Select 
Next, and the License Agreement dialog box opens. Choose I accept and select 
Next, and the Choose Destination dialog box will open with Install OrCAD 16.3 
Demo Accept C:\OrCAD\OrCAD_16.3 Demo. 

Select Next, and the Start Copying Files dialog box opens. Choose Select again, and 
the Ready to Install Program dialog box opens. Click Install, and the Installing 
Crystal Report Xii box will appear. The Setup dialog box opens with the prompt: 
Setup status installs program. The Install Wizard is now installing the OrCAD 
16.3 Demo. 

At completion, a message will appear: Searching for and adding programs to the 
Windows firewall exception list. Generating indexes for Cadence Help. This 
may take some time. 

When the process has completed, select Finish and the Cadence OrCAD 16.3 screen 
will appear. The software has been installed. 

Screen Icon: The screen icon can be established (if it does not appear automatically) by 

applying the following sequence. START- All Programs-Cadence-OrCAD 16.3 Demo- 
OrCAD Capture CIS Demo, followed by a right-click of the mouse to obtain a listing 
where Send to is chosen, followed by Desktop (create shortcut). The OrCAD icon will 
then appear on the screen and can be moved to the appropriate location. 

Folder Creation: Starting with the OrCAD opening screen, right-click on the Start 

option at the bottom left of the screen. Then choose Explore followed by Hard Drive 
(C:). Then place the mouse on the folder listing, and a right-click will result in a listing in 
which New is an option. Choose New followed by Folder, and then type in OrCAD 11.3 
in the provided area of the screen, followed by a right-click of the mouse. A location for all 
the files generated using OrCAD has now been established. 




Multisim 

Installation: 

Insert the Multisim disk into the DVD disk drive to obtain the Autoplay dialog box. 

Then select Always do this for software and games, followed by the selection of 
Auto-run to open the NI Circuit Design Suite 11.0 dialog box. 



Enter the full name to be used and provide the serial number. (The serial number 
appears in the Certificate of Ownership document that came with the NI Circuit 
Design Suite packet.) 

Selecting Next will result in the Destination Directory dialog box from which one will 
Accept the following: C:\Program Files(X86) National InstrumentsY Select Next 
to open the Features dialog box and then select NI Circuit Design Suite 11.0.1 
Education. 

Selecting Next will result in the Product Notification dialog box with a succeeding 
Next resulting in the License Agreement dialog box. A left-click of the mouse on I 
accept can then be followed by choosing Next to obtain the Start Installation dialog 
box. Another left-click and the installation process begins, with the progress being 
displayed. The process takes between 15 and 20 minutes. 

At the conclusion of the installation, you will be asked to install the NI Elvismx driver 
DVD. This time Cancel will be selected, and the NI Circuit Design Suite 11.0.1 
dialog box will appear with the following message: NI Circuit Design Suite 11.0.1 
has been installed. Click Finish, and the response will be to restart the computer to 
complete the operation. Select Restart, and the computer will shut down and start up 
again, followed by the appearance of the Multisim Screen dialog box. 

Select Activate and then Activate through secure Internet connection, and the Acti- 
vation Wizard dialog box will open. Enter the serial number followed by Next to 
enter all the information into the NI Activation Wizard dialog box. Selecting Next 
will result in the option of Send me an email confirmation of this activation. Select 
this option and the message Product successfully activated will appear. Selecting 
Finish will complete the process. 

Screen Icon: The process described for the OrCAD program will produce the same 

results for Multisim. 

Folder Creation: Following the procedure introduced above for the OrCAD program, a 

folder labeled OrCAD 16.3 was established for the Multisim files. 

The computer section of the next chapter will cover the details of opening both the 
OrCAD and Multisim analysis packages, setting up a specific circuit, and generating a 
variety of results. 

PROBLEMS ^ 

*Note: Asterisks indicate more difficult problems. 

1 .3 Covalent Bonding and Intrinsic Materials 

1. Sketch the atomic structure of copper and discuss why it is a good conductor and how its struc- 
ture is different from that of germanium, silicon, and gallium arsenide. 

2. In your own words, define an intrinsic material, a negative temperature coefficient, and cova- 
lent bonding. 

3. Consult your reference library and list three materials that have a negative temperature coeffi- 
cient and three that have a positive temperature coefficient. 

1.4 Energy Levels 

4. a. How much energy in joules is required to move a charge of 12 /iC through a difference in 

potential of 6 V? 

b. For part (a), find the energy in electron-volts. 

5. If 48 eV of energy is required to move a charge through a potential difference of 3.2 V, deter- 
mine the charge involved. 

6. Consult your reference library and determine the level of E g for GaP, ZnS, and GaAsP, three semi- 
conductor materials of practical value. In addition, determine the written name for each material. 

5 n-Type and p-Type Materials 

7. Describe the difference between n-type and p-type semiconductor materials. 

8. Describe the difference between donor and acceptor impurities. 

9. Describe the difference between majority and minority carriers. 











SEMICONDUCTOR 

DIODES 



10. Sketch the atomic structure of silicon and insert an impurity of arsenic as demonstrated for 
silicon in Fig. 1.7. 

11. Repeat Problem 10, but insert an impurity of indium. 

12. Consult your reference library and find another explanation of hole versus electron flow. Using 
both descriptions, describe in your own words the process of hole conduction. 

1 .6 Semiconductor Diode 

13. Describe in your own words the conditions established by forward- and reverse-bias conditions 
on a p-n junction diode and how the resulting current is affected. 

14. Describe how you will remember the forward- and reverse-bias states of the p-n junction 
diode. That is, how will you remember which potential (positive or negative) is applied to 
which terminal? 

15. a. Determine the thermal voltage for a diode at a temperature of 20°C. 

b. For the same diode of part (a), find the diode current using Eq. 1.2 if I s = 40 nA, n = 2 (low 
value of V D ), and the applied bias voltage is 0.5 V. 

16. Repeat Problem 15 for T = 100°C (boiling point of water). Assume that I s has increased to 5.0 pA. 

17. a. Using Eq. (1.2), determine the diode current at 20°C for a silicon diode with n = 2, I s = 

0.1 piA at a reverse-bias potential of -10 V. 
b. Is the result expected? Why? 

18. Given a diode current of 8 mA and n = 1, find I s if the applied voltage is 0.5 V and the tem- 
perature is room temperature (25 °C). 

*19. Given a diode current of 6 mA, V T = 26 mV, n = 1, and I s = 1 nA, find the applied voltage V D . 

20. a. Plot the function y = e x for v from 0 to 10. Why is it difficult to plot? 

b. What is the value of y = e x at x = 0? 

c. Based on the results of part (b), why is the factor — 1 important in Eq. (1.2)? 

21. In the reverse-bias region the saturation current of a silicon diode is about 0.1 p,A ( T = 20°C). 
Determine its approximate value if the temperature is increased 40°C. 

22. Compare the characteristics of a silicon and a germanium diode and determine which you would 
prefer to use for most practical applications. Give some details. Refer to a manufacturer’s listing 
and compare the characteristics of a germanium and a silicon diode of similar maximum ratings. 

23. Determine the forward voltage drop across the diode whose characteristics appear in Fig. 1.19 at 
temperatures of -75°C, 25°C, 125°C and a current of 10 mA. For each temperature, determine the 
level of saturation current. Compare the extremes of each and comment on the ratio of the two. 

7 Ideal versus Practical 

24. Describe in your own words the meaning of the word ideal as applied to a device or a system. 

25. Describe in your own words the characteristics of the ideal diode and how they determine the 
on and off states of the device. That is, describe why the short-circuit and open-circuit equiva- 
lents are appropriate. 

26. What is the one important difference between the characteristics of a simple switch and those 
of an ideal diode? 

1.8 Resistance Levels 

27. Determine the static or dc resistance of the commercially available diode of Fig. 1.15 at a for- 
ward current of 4 mA. 

28. Repeat Problem 27 at a forward current of 15 mA and compare results. 

29. Determine the static or dc resistance of the commercially available diode of Fig. 1 . 15 at a reverse 
voltage of — 10 V. How does it compare to the value determined at a reverse voltage of —30 V? 

30. Calculate the dc and ac resistances for the diode of Fig. 1.15 at a forward current of 10 mA and 
compare their magnitudes. 

31. a. Determine the dynamic (ac) resistance of the commercially available diode of Fig. 1 . 15 at a 

forward current of 10 mA using Eq. (1.5). 

b. Determine the dynamic (ac) resistance of the diode of Fig. 1 . 15 at a forward current of 10 mA 
using Eq. (1.6). 

c. Compare solutions of parts (a) and (b). 

32. Using Eq. (1.5), determine the ac resistance at a current of 1 mA and 15 mA for the diode of 
Fig. 1.15. Compare the solutions and develop a general conclusion regarding the ac resistance 
and increasing levels of diode current. 



53 






33. Using Eq. (1.6), determine the ac resistance at a current of 1 mA and 15 mA for the diode of 
Fig. 1.15. Modify the equation as necessary for low levels of diode current. Compare to the 
solutions obtained in Problem 32. 

34. Determine the average ac resistance for the diode of Fig. 1.15 for the region between 0.6 V 
and 0.9 V. 

35. Determine the ac resistance for the diode of Fig. 1.15 at 0.75 V and compare it to the average 
ac resistance obtained in Problem 34. 

1 .9 Diode Equivalent Circuits 

36. Find the piecewise-linear equivalent circuit for the diode of Fig. 1.15. Use a straight-line seg- 
ment that intersects the horizontal axis at 0.7 V and best approximates the curve for the region 
greater than 0.7 V. 

37. Repeat Problem 36 for the diode of Fig. 1 .27. 

38. Find the piecewise-linear equivalent circuit for the germanium and gallium arsenide diodes of 
Fig. 1.18. 

1.10 T ransition and Diffusion Capacitance 

*39. a. Referring to Fig. 1.33, determine the transition capacitance at reverse-bias potentials of 
-25 V and - 10 V. What is the ratio of the change in capacitance to the change in voltage? 

b. Repeat part (a) for reverse-bias potentials of - 10 V and — 1 V. Determine the ratio of the 
change in capacitance to the change in voltage. 

c. How do the ratios determined in parts (a) and (b) compare? What does this tell you about 
which range may have more areas of practical application? 

40. Referring to Fig. 1.33, determine the diffusion capacitance at 0 V and 0.25 V. 

41. Describe in your own words how diffusion and transition capacitances differ. 

42. Determine the reactance offered by a diode described by the characteristics of Fig. 1.33 at a 
forward potential of 0.2 V and a reverse potential of -20 V if the applied frequency is 6 MHz. 

43. The no-bias transition capacitance of a silicon diode is 8 pF with V K = 0.7 Y and n = 1/2. 
What is the transition capacitance if the applied reverse bias potential is 5 V? 

44. Find the applied reverse bias potential if the transition capacitance of a silicon diode is 4 pF but 
the no-bias level is 10 pF with n = 1/3 and V K = 0.7 V. 

1.11 Reverse Recovery Time 

45. Sketch the waveform for i of the network of Fig. 1.57 if t t = 2 t s and the total reverse recovery 
time is 9 ns. 



PROBLEMS 











10 


> v i 








t l = 5 ns 


0 

5 







FIG. 1.57 

Problem 45. 



►i 




1.12 Diode Specification Sheets 

*46. Plot I F versus V F using linear scales for the diode of Fig. 1.37. Note that the provided graph 
employs a log scale for the vertical axis (log scales are covered in Sections 9.2 and 9.3). 

47. a. Comment on the change in capacitance level with increase in reverse-bias potential for the 

diode of Fig. 1.37. 

b. What is the level of C(0)? 

c. Using V K = 0.7 V, find the level of n in Eq. 1.9. 

48. Does the reverse saturation current of the diode of Fig. 1.37 change significantly in magnitude 
for reverse-bias potentials in the range -25 Y to - 100 V? 







*49. For the diode of Fig. 1.37 determine the level of I R at room temperature (25°C) and the boiling 
point of water (100°C). Is the change significant? Does the level just about double for every 
10°C increase in temperature? 

50. For the diode of Fig. 1.37, determine the maximum ac (dynamic) resistance at a forward cur- 
rent of 0.1, 1.5, and 20 mA. Compare levels and comment on whether the results support con- 
clusions derived in earlier sections of this chapter. 

51. Using the characteristics of Fig. 1.37, determine the maximum power dissipation levels for the 
diode at room temperature (25°C) and 100°C. Assuming that V F remains fixed at 0.7 V, how 
has the maximum level of I F changed between the two temperature levels? 

52. Using the characteristics of Fig. 1.37, determine the temperature at which the diode current 
will be 50% of its value at room temperature (25 °C). 

1.15 Zener Diodes 

53. The following characteristics are specified for a particular Zener diode: V z = 29 V, V R = 16.8 V, 
I ZT =10 mA, I R = 20 ijlA, and I ZM = 40 mA. Sketch the characteristic curve in the manner 
displayed in Fig. 1.47. 

*54. At what temperature will the 10-V Zener diode of Fig. 1.47 have a nominal voltage of 10.75 V? 
(Hint: Note the data in Table 1.7.) 

55. Determine the temperature coefficient of a 5-V Zener diode (rated 25 °C value) if the nominal 
voltage drops to 4.8 V at a temperature of 100°C. 

56. Using the curves of Fig. 1.48a, what level of temperature coefficient would you expect for a 
20-V diode? Repeat for a 5-V diode. Assume a linear scale between nominal voltage levels and 
a current level of 0. 1 mA. 

57. Determine the dynamic impedance for the 24-V diode at I z = 10 mA for Fig. 1.48b. Note that 
it is a log scale. 

*58. Compare the levels of dynamic impedance for the 24-V diode of Fig. 1.48b at current levels of 
0.2, 1, and 10 mA. How do the results relate to the shape of the characteristics in this region? 

1.16 Light-Emitting Diodes 

59. Referring to Fig. 1.52e, what would appear to be an appropriate value of V K for this device? 
How does it compare to the value of V R for silicon and germanium? 

60. Given that E g = 0.67 eV for germanium, find the wavelength of peak solar response for the 
material. Do the photons at this wavelength have a lower or higher energy level? 

61. Using the information provided in Fig. 1.52, determine the forward voltage across the diode if 
the relative luminous intensity is 1.5. 

*62. a. What is the percentage increase in relative efficiency of the device of Fig. 1.52 if the peak 
current is increased from 5 mA to 10 mA? 

b. Repeat part (a) for 30 mA to 35 mA (the same increase in current). 

c. Compare the percentage increase from parts (a) and (b). At what point on the curve would 
you say there is little to be gained by further increasing the peak current? 

63. a. If the luminous intensity at 0° angular displacement is 3.0 mcd for the device of Fig. 1.52, 
at what angle will it be 0.75 mcd? 

b. At what angle does the loss of luminous intensity drop below the 50% level? 

*64. Sketch the current derating curve for the average forward current of the high-efficiency red 
LED of Fig. 1.52 as determined by temperature. (Note the absolute maximum ratings.) 



Diode Applications 



2 



CHAPTER OBJECTIVES ^ 

Understand the concept of load-line analysis and how it is applied to diode networks. 
Become familiar with the use of equivalent circuits to analyze series, parallel, and 
series-parallel diode networks. 

Understand the process of rectification to establish a dc level from a sinusoidal ac 
input. 

Be able to predict the output response of a clipper and clamper diode configuration. 
Become familiar with the analysis of and the range of applications for Zener diodes. 

2.1 INTRODUCTION ^ 

The construction, characteristics, and models of semiconductor diodes were introduced in 
Chapter 1. This chapter will develop a working knowledge of the diode in a variety of 
configurations using models appropriate for the area of application. By chapter’s end, the 
fundamental behavior pattern of diodes in dc and ac networks should be clearly under- 
stood. The concepts learned in this chapter will have significant carryover in the chapters 
to follow. For instance, diodes are frequently employed in the description of the basic con- 
struction of transistors and in the analysis of transistor networks in the dc and ac domains. 

This chapter demonstrates an interesting and very useful aspect of the study of a field 
such as electronic devices and systems: 

Once the basic behavior of a device is understood , its function and response in an 
infinite variety of configurations can be examined. 

In other words, now that we have a basic knowledge of the characteristics of a diode 
along with its response to applied voltages and currents, we can use this knowledge to ex- 
amine a wide variety of networks. There is no need to reexamine the response of the device 
for each application. 

In general: 

The analysis of electronic circuits can follow one of two paths: using the actual 
characteristics or applying an approximate model for the device. 

For the diode the initial discussion will include the actual characteristics to clearly dem- 
onstrate how the characteristics of a device and the network parameters interact. Once there 
is confidence in the results obtained, the approximate piecewise model will be employed to 
verify the results found using the complete characteristics. It is important that the role and 
the response of various elements of an electronic system be understood without continually 





56 DIODE APPLICATIONS having to resort to lengthy mathematical procedures. This is usually accomplished through 

the approximation process, which can develop into an art itself. Although the results ob- 
tained using the actual characteristics may be slightly different from those obtained using a 
series of approximations, keep in mind that the characteristics obtained from a specification 
sheet may be slightly different from those of the device in actual use. In other words, for 
example, the characteristics of a 1N4001 semiconductor diode may vary from one element 
to the next in the same lot. The variation may be slight, but it will often be sufficient to 
justify the approximations employed in the analysis. Also consider the other elements of the 
network: Is the resistor labeled 100 II exactly 100 12? Is the applied voltage exactly 10 V or 
perhaps 10.08 V? All these tolerances contribute to the general belief that a response deter- 
mined through an appropriate set of approximations can often be “as accurate” as one that 
employs the full characteristics. In this book the emphasis is toward developing a working 
knowledge of a device through the use of appropriate approximations, thereby avoiding an 
unnecessary level of mathematical complexity. Sufficient detail will normally be provided, 
however, to permit a detailed mathematical analysis if desired. 

2.2 LOAD-LINE ANALYSIS ^ 

The circuit of Fig. 2.1 is the simplest of diode configurations. It will be used to describe the 
analysis of a diode circuit using its actual characteristics. In the next section we will replace 
the characteristics by an approximate model for the diode and compare solutions. Solving 
the circuit of Fig. 2.1 is all about finding the current and voltage levels that will satisfy 
both the characteristics of the diode and the chosen network parameters at the same time. 








FIG. 2.1 

Series diode configuration: (a) circuit; (b) characteristics. 



In Fig. 2.2 the diode characteristics are placed on the same set of axes as a straight line 
defined by the parameters of the network. The straight line is called a load line because the 
intersection on the vertical axis is defined by the applied load R. The analysis to follow is 
therefore called load-line analysis. The intersection of the two curves will define the solu- 
tion for the network and define the current and voltage levels for the network. 

Before reviewing the details of drawing the load line on the characteristics, we need to 
determine the expected response of the simple circuit of Fig. 2.1. Note in Fig. 2.1 that the 
effect of the “pressure” established by the dc supply is to establish a conventional current 
in the direction indicated by the clockwise arrow. The fact that the direction of this current 
has the same direction as the arrow in the diode symbol reveals that the diode is in the 
“on” state and will conduct a high level of current. The polarity of the applied voltage has 
resulted in a forward-bias situation. With the current direction established, the polarities 
for the voltage across the diode and resistor can be superimposed. The polarity of V D and 
the direction of I D clearly reveal that the diode is indeed in the forward-bias state, result- 
ing in a voltage across the diode in the neighborhood of 0.7 V and a current on the order 
of 10 mA or more. 



LOAD-LINE ANALYSIS 



57 




The intersections of the load line on the characteristics of Fig. 2.2 can be determined by 
first applying Kirchhoff ’ s voltage law in the clockwise direction, which results in 

+e-v d -v r = 0 



or 



E=V d + I d R 



( 2 . 1 ) 



The two variables of Eq. (2.1), V D and I D , are the same as the diode axis variables of 
Fig. 2.2. This similarity permits plotting Eq. (2.1) on the same characteristics of Fig. 2.2. 

The intersections of the load line on the characteristics can easily be determined if one 
simply employs the fact that anywhere on the horizontal axis Id = OA and anywhere on 
the vertical axis V D = 0 V. 

If we set V D = 0 V in Eq. (2.1) and solve for I D , we have the magnitude of I D on the 
vertical axis. Therefore, with V D = 0 V, Eq. (2.1) becomes 

E=V d + I d R 

= 0 V + i d r 



and 



E 




Id ~ R 


> 

o 

II 

£ 



( 2 . 2 ) 



as shown in Fig. 2.2. If we set I D = 0 A in Eq. (2.1) and solve for V D , we have the magni- 
tude of V D on the horizontal axis. Therefore, with Id ~ 0 A, Eq. (2.1) becomes 

E=V d + I d R 
= V D + (0 A )R 



and 



Vd — E\i d =oa 



( 2 . 3 ) 



as shown in Fig. 2.2. A straight line drawn between the two points will define the load line 
as depicted in Fig. 2.2. Change the level of R (the load) and the intersection on the vertical 
axis will change. The result will be a change in the slope of the load line and a different 
point of intersection between the load line and the device characteristics. 

We now have a load line defined by the network and a characteristic curve defined by the 
device. The point of intersection between the two is the point of operation for this circuit. 
By simply drawing a line down to the horizontal axis, we can determine the diode voltage 
V Dq , whereas a horizontal line from the point of intersection to the vertical axis will provide 
the level of I Dq . The current I D is actually the current through the entire series configuration 
of Fig. 2.1a. The point of operation is usually called the quiescent point (abbreviated “Q- 
point”) to reflect its “still, unmoving” qualities as defined by a dc network. 



58 DIODE APPLICATIONS The solution obtained at the intersection of the two curves is the same as would be ob- 

tained by a simultaneous mathematical solution of 

I D = ^ ^ [ derived from Eq. (2.1)] 

and I D = I s (e VD / nVT - 1) 

Since the curve for a diode has nonlinear characteristics, the mathematics involved would 
require the use of nonlinear techniques that are beyond the needs and scope of this book. 
The load-line analysis described above provides a solution with a minimum of effort and a 
“pictorial” description of why the levels of solution for V Dq and I Dq were obtained. The 
next example demonstrates the techniques introduced above and reveals the relative ease 
with which the load line can be drawn using Eqs. (2.2) and (2.3). 



EXAMPLE 2.1 For the series diode configuration of Fig. 2.3a, employing the diode char- 
acteristics of Fig. 2.3b, determine: 

a. Vj) Q and I Dq . 

b. V R . 





FIG. 2.3 

(a) Circuit; (b) characteristics. 



Solution: 



a. Eq. (2.2): 



Id R 



v D =ov 



10 V 
0.5 kO 



= 20 mA 



Eq. (2.3): V D = E \ Id=0A = 10 V 

The resulting load line appears in Fig. 2.4. The intersection between the load line and 
the characteristic curve defines the g-point as 



= 0.78 V 
I Dq = 18.5 mA 

The level of V D is certainly an estimate, and the accuracy of I D is limited by the chosen 
scale. A higher degree of accuracy would require a plot that would be much larger and 
perhaps unwieldy. 

b. V R = E - V D = 10 V - 0.78 V = 9.22 V 



As noted in the example above, 

the load line is determined solely by the applied network , whereas the characteristics 
are defined by the chosen device. 

Changing the model we use for the diode will not disturb the network so the load line to 
be drawn will be exactly the same as appearing in the example above. 

Since the network of Example 2.1 is a dc network the g-point of Fig. 2.4 will remain 
fixed with V Dq = 0.78 V and I Dq = 18.5 mA. In Chapter 1 a dc resistance was defined at 
any point on the characteristics by R D c — Vd/Id • 



Id (mA) 



LOAD-LINE ANALYSIS 



59 




Using the g-point values, the dc resistance for Example 2.1 is 



Rt 



Vd 

In 



0.78 V 
18.5 mA 



= 42.1612 



An equivalent network (for these operating conditions only) can then be drawn as shown 
in Fig. 2.5. 



+ v D - 




Network quivalent to Fig. 2.4. 



The current 



Id = 


E 


10 V 


10V 


r d + r 


~ 42.16 12 + 50012 


“ 542.1612 


Vr = 


RE 


(500 O)(10V) 


= 9.22 V 


R D + R 


” 42.1612 + 50012 



= 18.5 mA 



and 



matching the results of Example 2.1. 

In essence, therefore, once a dc g-point has been determined the diode can be replaced 
by its dc resistance equivalent. This concept of replacing a characteristic by an equivalent 
model is an important one and will be used when we consider ac inputs and equivalent models 
for transistors in the chapters to follow. Let us now see what effect different equivalent 
models for the diode will have on the response in Example 2.1 



EXAMPLE 2.2 Repeat Example 2.1 using the approximate equivalent model for the sili- 
con semiconductor diode. 

Solution : The load line is redrawn as shown in Fig. 2.6 with the same intersections as 
defined in Example 2.1. The characteristics of the approximate equivalent circuit for the 
diode have also been sketched on the same graph. The resulting g-point is 

V Dq = 0.7 V 
I Dq = 18.5 mA 



60 



DIODE APPLICATIONS 



Id (mA) 




FIG. 2.6 

Solution to Example 2.1 using the diode approximate model. 



The results obtained in Example 2.2 are quite interesting. The level of I Dq is exactly the 
same as obtained in Example 2.1 using a characteristic curve that is a great deal easier to 
draw than that appearing in Fig. 2.4. The V D - 0.7 V here and the 0.78 V from Example 
2.1 are of a different magnitude to the hundredths place, but they are certainly in the same 
neighborhood if we compare their magnitudes to the magnitudes of the other voltages of 
the network. 

For this situation the dc resistance of the g-point is 



Vn 



Rn = 



0.7 V 
18.5 mA 



= 37.84 12 



which is still relatively close to that obtained for the full characteristics. 

In the next example we go a step further and substitute the ideal model. The results will 
reveal the conditions that must be satisfied to apply the ideal equivalent properly. 



EXAMPLE 2.3 Repeat Example 2.1 using the ideal diode model. 

Solution: As shown in Fig. 2.7, the load line is the same, but the ideal characteristics 
now intersect the load line on the vertical axis. The g-point is therefore defined by 

V Dq = 0\ 

I Do = 20 mA 




FIG. 2.7 

Solution to Example 2.1 using the ideal diode model. 



61 



The results are sufficiently different from the solutions of Example 2.1 to cause some con- 
cern about their accuracy. Certainly, they do provide some indication of the level of voltage 
and current to be expected relative to the other voltage levels of the network, but the addi- 
tional effort of simply including the 0.7- V offset suggests that the approach of Example 2.2 
is more appropriate. 

Use of the ideal diode model therefore should be reserved for those occasions when 
the role of a diode is more important than voltage levels that differ by tenths of a volt and 
in those situations where the applied voltages are considerably larger than the threshold 
voltage V K . In the next few sections the approximate model will be employed exclusively 
since the voltage levels obtained will be sensitive to variations that approach V K . In later 
sections the ideal model will be employed more frequently since the applied voltages will 
frequently be quite a bit larger than V K and the authors want to ensure that the role of the 
diode is correctly and clearly understood. 

In this case, 



Vn 



Rn = 



0V 
20 mA 



0 12 (or a short-circuit equivalent) 



SERIES DIODE 
CONFIGURATIONS 



2.3 SERIES DIODE CONFIGURATIONS ^ 

In the last section we found that the results obtained using the approximate piecewise-linear 
equivalent model were quite close, if not equal, to the response obtained using the full 
characteristics. In fact, if one considers all the variations possible due to tolerances, tem- 
perature, and so on, one could certainly consider one solution to be “as accurate” as the 
other. Since the use of the approximate model normally results in a reduced expenditure of 
time and effort to obtain the desired results, it is the approach that will be employed in this 
book unless otherwise specified. Recall the following: 

The primary purpose of this text is to develop a general knowledge of the behavior, 
capabilities, and possible areas of application of a device in a manner that will 
minimize the need for extensive mathematical developments . 

For all the analysis to follow in this chapter it is assumed that 

The forward resistance of the diode is usually so small compared to the other series 
elements of the network that it can be ignored. 

This is a valid approximation for the vast majority of applications that employ diodes. 
Using this fact will result in the approximate equivalents for a silicon diode and an ideal 
diode that appear in Table 2.1. For the conduction region the only difference between 
the silicon diode and the ideal diode is the vertical shift in the characteristics, which is 
accounted for in the equivalent model by a dc supply of 0.7 V opposing the direction of 
forward current through the device. For voltages less than 0.7 V for a silicon diode and 0 V 
for the ideal diode the resistance is so high compared to other elements of the network that 
its equivalent is the open circuit. 

For a Ge diode the offset voltage is 0.3 V and for a GaAs diode it is 1.2 V. Otherwise 
the equivalent networks are the same. For each diode the label Si, Ge, or GaAs will appear 
along with the diode symbol. For networks with ideal diodes the diode symbol will appear 
as shown in Table 2.1 without any labels. 

The approximate models will now be used to investigate a number of series diode con- 
figurations with dc inputs. This will establish a foundation in diode analysis that will carry 
over into the sections and chapters to follow. The procedure described can, in fact, be ap- 
plied to networks with any number of diodes in a variety of configurations. 

For each configuration the state of each diode must first be determined. Which diodes are 
“on” and which are “off’? Once determined, the appropriate equivalent can be substituted 
and the remaining parameters of the network determined. 

In general, a diode is in the “on” state if the current established by the applied sources 
is such that its direction matches that of the arrow in the diode symbol, and V D > 0.7 V 
for silicon, V D > 0.3 V for germanium, and V D > 1.2 V for gallium arsenide. 

For each configuration, mentally replace the diodes with resistive elements and note the 
resulting current direction as established by the applied voltages (“pressure”). If the resulting 



62 



DIODE APPLICATIONS 



TABLE 2.1 

Approximate and Ideal Semiconductor Diode Models. 




+ V D - 




direction is a “match” with the arrow in the diode symbol, conduction through the diode will 
occur and the device is in the “on” state. The description above is, of course, contingent on 
the supply having a voltage greater than the “turn-on” voltage (V£) of each diode. 

If a diode is in the “on” state, one can either place a 0.7- V drop across the element or 
redraw the network with the V K equivalent circuit as defined in Table 2. 1 . In time the prefer- 
ence will probably simply be to include the 0.7- V drop across each “on” diode and to draw a 
diagonal line through each diode in the “off’ or open state. Initially, however, the substitu- 
tion method will be used to ensure that the proper voltage and current levels are determined. 

The series circuit of Fig. 2.8 described in some detail in Section 2.2 will be used to 
demonstrate the approach described in the above paragraphs. The state of the diode is first 
determined by mentally replacing the diode with a resistive element as shown in Fig. 2.9a. 
The resulting direction of I is a match with the arrow in the diode symbol, and since E>V k . , 
the diode is in the “on” state. The network is then redrawn as shown in Fig. 2.9b with the 
appropriate equivalent model for the forward-biased silicon diode. Note for future refer- 
ence that the polarity of V D is the same as would result if in fact the diode were a resistive 
element. The resulting voltage and current levels are the following: 

( 2 . 4 ) 



v D = v* 



I + v D - 





FIG. 2.9 

(a) Determining the state of the diode of Fig. 2.8; (b) substituting the 
equivalent model for the “ on ” diode of Fig. 2.9a. 



Vr = E-V k 



Vr 

Id ~ Ir ~ R 



( 2 . 5 ) 



SERIES DIODE 63 
CONFIGURATIONS 



( 2 . 6 ) 



In Fig. 2.10 the diode of Fig. 2.7 has been reversed. Mentally replacing the diode with 
a resistive element as shown in Fig. 2.11 will reveal that the resulting current direction 
does not match the arrow in the diode symbol. The diode is in the “off’ state, resulting in 
the equivalent circuit of Fig. 2.12. Due to the open circuit, the diode current is 0 A and the 
voltage across the resistor R is the following: 

V R = I r R = I d R = (0 A)R = 0 V 






Ir 

+ 

Vr 



Reversing the diode of Fig. 2.8. 



Determining the state of the diode 
of Fig. 2.10. 



Substituting the equivalent model 
for the “off” diode of Fig. 2.10. 



The fact that V R = 0 V will establish E volts across the open circuit as defined by Kirchhoff’ s 
voltage law. Always keep in mind that under any circumstances — dc, ac instantaneous 
values, pulses, and so on — Kirchhoff s voltage law must be satisfied! 



EXAMPLE 2.4 For the series diode configuration of Fig. 2.13, determine V D , V R , and Id- 



+ Vd — 




Solution : Since the applied voltage establishes a current in the clockwise direction to 
match the arrow of the symbol and the diode is in the “on” state, 

V D = 0.7 V 

V R = E - V D = 8 V - 0.7 V = 7.3 V 



Vr _ 7.3 V 
R ~ 2.2 kfl 



3.32 mA 



Id = Is = 



64 DIODE APPLICATIONS 



EXAMPLE 2.5 Repeat Example 2.4 with the diode reversed. 

Solution: Removing the diode, we find that the direction of I is opposite to the arrow in 
the diode symbol and the diode equivalent is the open circuit no matter which model is 
employed. The result is the network of Fig. 2.14, where Id ~ 0 A due to the open circuit. 
Since Vr = IrR , we have V R = (0 )R = 0 V. Applying Kirchhoff s voltage law around 
the closed loop yields 

e-v d -v r = 0 

and V d = E-V r = E- 0 = E=8Y 




Determining the unknown quantities for 
Example 2.5. 



In particular, note in Example 2.5 the high voltage across the diode even though it is an 
“off’ state. The current is zero, but the voltage is significant. For review purposes, keep the 
following in mind for the analysis to follow: 

An open circuit can have any voltage across its terminals, but the current is always 0 A. 
A short circuit has a 0-V drop across its terminals, but the current is limited only by the 
surrounding network . 

In the next example the notation of Fig. 2.15 will be employed for the applied voltage. It 
is a common industry notation and one with which the reader should become very familiar. 
Such notation and other defined voltage levels are treated further in Chapter 4. 




FIG. 2.15 

Source notation. 



+0.5 V 




FIG. 2.16 

Series diode circuit for 
Example 2.6. 



EXAMPLE 2.6 For the series diode configuration of Fig. 2.16, determine V D , Vr, and Id- 



Solution: Although the “pressure” establishes a current with the same direction as the 
arrow symbol, the level of applied voltage is insufficient to turn the silicon diode “on.” 
The point of operation on the characteristics is shown in Fig. 2.17, establishing the open- 
circuit equivalent as the appropriate approximation, as shown in Fig. 2.18. The resulting 
voltage and current levels are therefore the following: 

Id = 0A 

Vr = IrR = I d R = (0 A) 1.2 kll = 0 V 



V n = E = 



0.5 V 



and 




+0.5 V 

o 

^/ D = 0 mA 
o - 



V D = 0.5 Y 




SERIES DIODE 65 
CONFIGURATIONS 



FIG. 2.17 

Operating point with E = 0.5 V. 



FIG. 2.18 

Determining Ip, V R , and V D for 
the circuit of Fig. 2.16. 



EXAMPLE 2.7 Determine V 0 and Ip for the series circuit of Fig. 2.19. 

Solution : An attack similar to that applied in Example 2.4 will reveal that the resulting 
current has the same direction as the arrowheads of the symbols of both diodes, and the 
network of Fig. 2.20 results because E = 12 V > (0.7 V + 1.8 V [Table 1.8]) = 2.5 V. 
Note the redrawn supply of 12 V and the polarity of V Q across the 680-12 resistor. The 
resulting voltage is 

V 0 = E - V Kl - V Kl = 12V - 2.5V = 9.5V 
V R V 0 9.5 V 

and I D = I R = — = — = — = 13.97 mA 

° R R 680 12 




Example 2. 7. 



EXAMPLE 2.8 Determine Ip , Vp 2 , and V 0 for the circuit of Fig. 2.21. 

Solution: Removing the diodes and determining the direction of the resulting current I 
result in the circuit of Fig. 2.22. There is a match in current direction for one silicon diode 
but not for the other silicon diode. The combination of a short circuit in series with an open 
circuit always results in an open circuit and I D = 0 A, as shown in Fig. 2.23. 




FIG. 2.21 

Circuit for Example 2.8. 



FIG. 2.22 

Determining the state of the diodes 
of Fig. 2.21. 



FIG. 2.23 

Substituting the equivalent state for 
the open diode. 



66 DIODE APPLICATIONS 



1=0 A 



v Dl = 0\ 



+ 




FIG. 2.24 

Determining the unknown quantities for the 
circuit of Example 2.8. 



The question remains as to what to substitute for the silicon diode. For the analysis to 
follow in this and succeeding chapters, simply recall for the actual practical diode that when 
Id = 0 A, V D = 0 V (and vice versa), as described for the no-bias situation in Chapter 1. 
The conditions described by I D = OA and V D{ = 0 V are indicated in Fig. 2.24. We have 

V 0 = I r R = I d R = (0 A)R = 0 V 

V/) 2 Fopen circuit E ^0 F 

Applying Kirchhoff’ s voltage law in a clockwise direction gives 



E-v Dl - v D2 -V o = 0 

and V Dl = E - V Dl ~ V 0 = 20 V - 0 - 0 

= 20 V 

with V 0 = 0 V 



EXAMPLE 2.9 Determine 7, V\, an d V 0 f° r the series dc configuration of Fig. 2.25. 



+ Vi - 




E 2 = -5 V 

FIG. 2.25 

Circuit for Example 2.9. 



Solution: The sources are drawn and the current direction indicated as shown in Fig. 2.26. 
The diode is in the “on” state and the notation appearing in Fig. 2.27 is included to indicate 
this state. Note that the “on” state is noted simply by the additional V D = 0.7 V on the 
figure. This eliminates the need to redraw the network and avoids any confusion that may 







- h 




E 2 — 5 V 

I + 



FIG. 2.26 

Determining the state of the diode for the 
network of Fig. 2.25. 



R * + 0.1 V “ 




FIG. 2.27 

Determining the unknown quantities for the network 
of Fig. 2.25. KVL, Kirchhoff voltage loop. 



67 



result from the appearance of another source. As indicated in the introduction to this sec- 
tion, this is probably the path and notation that one will take when a level of confidence 
has been established in the analysis of diode configurations. In time the entire analysis will 
be performed simply by referring to the original network. Recall that a reverse-biased 
diode can simply be indicated by a line through the device. 

The resulting current through the circuit is 

_ E x + E 2 ~ V D _ 10 V + 5 V - 0.7 V _ 14.3 V 
R x + R 2 ~ 4.7 kll + 2.2 kll ~ 6.9 kll 

= 2.07 mA 
and the voltages are 

Vi = IRi = (2.07 mA)(4.7 kll) = 9.73 V 
V 2 = IR 2 = (2.07 mA)(2.2 kft) = 4.55 V 

Applying Kirchhoff s voltage law to the output section in the clockwise direction results in 

-E 2 + V 2 ~V o = 0 

and V 0 = V 2 ~ E 2 = 4.55 V - 5 V = -0.45 V 

The minus sign indicates that V 0 has a polarity opposite to that appearing in Fig. 2.25. 



PARALLEL AND 
SERIES-PARALLEL 
CONFIGURATIONS 



2.4 PARALLEL AND SERIES-PARALLEL 

CONFIGURATIONS ^ 

The methods applied in Section 2.3 can be extended to the analysis of parallel and series- 
parallel configurations. For each area of application, simply match the sequential series of 
steps applied to series diode configurations. 



EXAMPLE 2.10 Determine V 0 , I \ , Ip > x , and I Dl for the parallel diode configuration of Fig. 2.28. 




+ Vr ~ 

0.33 kQ. 

— vw — 

R 



E 10 V 0.7 V- 



-o + 



T 0 ' 

— —0.7V C 



1 



FIG. 2.29 

Determining the unknown quantities for 
the network of Example 2.10. 



Solution: For the applied voltage the “pressure” of the source acts to establish a current 
through each diode in the same direction as shown in Fig. 2.29. Since the resulting current 
direction matches that of the arrow in each diode symbol and the applied voltage is greater 
than 0.7 V, both diodes are in the “on” state. The voltage across parallel elements is always 
the same and 



The current is 



= 0.7 V 



h 



Vr = E- l V r 

R R 



10 V - 0.7 V 
0.33 kfl 



28.18 mA 



Assuming diodes of similar characteristics, we have 

_ h _ 28.18 mA 

Id x -Id, - 2 - 2 



14.09 mA 



68 DIODE APPLICATIONS 



+8 V 




+8 V 




— 2V 



I 



This example demonstrates one reason for placing diodes in parallel. If the current rat- 
ing of the diodes of Fig. 2.28 is only 20 mA, a current of 28.18 mA would damage the 
device if it appeared alone in Fig. 2.28. By placing two in parallel, we limit the current to 
a safe value of 14.09 mA with the same terminal voltage. 



EXAMPLE 2.1 1 In this example there are two LEDs that can be used as a polarity detec- 
tor. Apply a positive source voltage and a green light results. Negative supplies result in a 
red light. Packages of such combinations are commercially available. 

Find the resistor R to ensure a current of 20 mA through the “on” diode for the configu- 
ration of Fig. 2.30. Both diodes have a reverse breakdown voltage of 3 V and an average 
turn-on voltage of 2 V. 



Solution: The application of a positive supply voltage results in a conventional current 
that matches the arrow of the green diode and turns it on. 

The polarity of the voltage across the green diode is such that it reverse biases the red 
diode by the same amount. The result is the equivalent network of Fig. 2.31. 

Applying Ohm’ s law, we obtain 



/ = 20 mA 



E ~ Vled 
R 



8 V - 2 V 
R 



and 



R = 



6 V 
20 mA 



= 300 a 



Note that the reverse breakdown voltage across the red diode is 2 V, which is fine for an 
LED with a reverse breakdown voltage of 3 V. 

However, if the green diode were to be replaced by a blue diode, problems would 
develop, as shown in Fig. 2.32. Recall that the forward bias required to turn on a blue diode 
is about 5 V. The result would appear to require a smaller resistor R to establish the current 
of 20 mA. However, note that the reverse bias voltage of the red LED is 5 V, but the 
reverse breakdown voltage of the diode is only 3 V. The result is the voltage across the red 
LED would lock in at 3 V as shown in Fig. 2.33. The voltage across R would be 5 V and 
the current limited to 20 mA with a 250 12 resistor but neither LED would be on. 



FIG. 2.31 

Operating conditions for the 
network of Fig. 2.30. 




FIG. 2.32 

Network of Fig. 2.31 
with a blue diode. 



FIG. 2.33 

Demonstrating damage to the red LED if the 
reverse breakdown voltage is exceeded. 



A simple solution to the above is to add the appropriate resistance level in series with 
each diode to establish the desired 20 mA and to include another diode to add to the 
reverse-bias total reverse breakdown voltage rating, as shown in Fig. 2.34. When the blue 
LED is on, the diode in series with the blue LED will also be on, causing a total voltage 
drop of 5.7 V across the two series diodes and a voltage of 2.3 V across the resistor R h 
establishing a high emission current of 19.17 mA. At the same time the red LED diode and 



8 V 




FIG. 2.34 

Protective measure for the red LED of Fig. 2.33. 



PARALLEL AND 69 
SERIES-PARALLEL 
CONFIGURATIONS 



its series diode will also be reverse biased, but now the standard diode with a reverse 
breakdown voltage of 20 V will prevent the full reverse-bias voltage of 8 V from appear- 
ing across the red LED. When forward biased, the resistor R 2 will establish a current of 
19.63 mA to ensure a high level of intensity for the red LED. 



EXAMPLE 2.12 Determine the voltage V 0 for the network of Fig. 2.35. 

Solutions Initially, it might appear that the applied voltage will turn both diodes “on” 
because the applied voltage (“pressure”) is trying to establish a conventional current 
through each diode that would suggest the “on” state. However, if both were on, there 
would be more than one voltage across the parallel diodes, violating one of the basic rules 
of network analysis: The voltage must be the same across parallel elements. 

The resulting action can best be explained by remembering that there is a period of 
build-up of the supply voltage from 0 V to 12 V even though it may take milliseconds or 
microseconds. At the instant the increasing supply voltage reaches 0.7 V the silicon diode will 
turn “on” and maintain the level of 0.7 V since the characteristic is vertical at this voltage — the 
current of the silicon diode will simply rise to the defined level. The result is that the volt- 
age across the green LED will never rise above 0.7 V and will remain in the equivalent 
open-circuit state as shown in Fig. 2.36. 

The result is 

V 0 = 12 V - 0.7 V = 11.3 V 




FIG. 2.35 

Network for Example 2.12. 




FIG. 2.36 

Determining V Q for the network of 
Fig. 2.35. 



70 DIODE APPLICATIONS 



EXAMPLE 2.13 Determine the currents I\, / 2 , and for the network of Fig. 2.37. 



3.3kQ 

-AAAr- 



Si 

>h 

Di 



+ 

E-=- 20 V 



Si 



[D, 



AAA r 

5.6 kU 



+ 0.7V- 




- V 2 + 



FIG. 2.37 

Network for Example 2.13. 



FIG. 2.38 

Determining the unknown quantities for 
Example 2.13. 



Solution: The applied voltage (pressure) is such as to turn both diodes on, as indicated 
by the resulting current directions in the network of Fig. 2.38. Note the use of the abbrevi- 
ated notation for “on” diodes and that the solution is obtained through an application of 
techniques applied to dc series-parallel networks. We have 



h 



Vk 2 _ 0.7 V 
Ri ~ 3.3 kil 



0.212 mA 



Applying Kirchhoff s voltage law around the indicated loop in the clockwise direction 
yields 

~V 2 + E - V K] -V K2 = 0 

and V 2 = E - V K] - V Kl = 20 V - 0.7 V - 0.7 V = 18.6 V 

V 2 18.6 V 

with I 2 = — = ^ = 3.32 mA 

2 R 2 5.6 kO 

At the bottom node a , 

b 2 + h = h 

and I Dl — 1 2 ~ 1\ — 3.32 mA - 0.212 mA = 3.11mA 



2.5 AND/OR CATES 



Si 




The tools of analysis are now at our disposal, and the opportunity to investigate a computer 
configuration is one that will demonstrate the range of applications of this relatively sim- 
ple device. Our analysis will be limited to determining the voltage levels and will not 
include a detailed discussion of Boolean algebra or positive and negative logic. 

The network to be analyzed in Example 2. 14 is an OR gate for positive logic. That is, the 
10-V level of Fig. 2.39 is assigned a “1” for Boolean algebra and the 0-V input is assigned 
a “0.” An OR gate is such that the output voltage level will be a 1 if either or both inputs is 
a 1. The output is a 0 if both inputs are at the 0 level. 

The analysis of AND/OR gates is made easier by using the approximate equivalent for 
a diode rather than the ideal because we can stipulate that the voltage across the diode must 
be 0.7 V positive for the silicon diode to switch to the “on” state. 

In general, the best approach is simply to establish a “gut” feeling for the state of the 
diodes by noting the direction and the “pressure” established by the applied potentials. The 
analysis will then verify or negate your initial assumptions. 



EXAMPLE 2.14 Determine V 0 for the network of Fig. 2.39. 

Solution: First note that there is only one applied potential; 10 V at terminal 1. Terminal 2 
with a 0-V input is essentially at ground potential, as shown in the redrawn network of 



AND/OR GATES 



71 



Fig. 2.40. Figure 2.40 “suggests” that D\ is probably in the “on” state due to the applied 10 V, 
whereas D 2 with its “positive” side at 0 V is probably “off.” Assuming these states will 
result in the configuration of Fig. 2.41. 




Redrawn network of Fig. 2.39. 




V 0 = E-V k = 9.3 V (a 1 level) 



FIG. 2.41 

Assumed diode states for Fig. 2.40. 



The next step is simply to check that there is no contradiction in our assumptions. That is, 
note that the polarity across D\ is such as to turn it on and the polarity across D 2 is such as to 
turn it off. ForT^ the “on” state establishes V 0 at V 0 = E — V D = 10 V - 0.7 V = 9.3 V. 
With 9.3 V at the cathode (— ) side of D 2 and 0 V at the anode (+) side, D 2 is definitely in the 
“off’ state. The current direction and the resulting continuous path for conduction further 
confirm our assumption that D\ is conducting. Our assumptions seem confirmed by the 
resulting voltages and current, and our initial analysis can be assumed to be correct. The out- 
put voltage level is not 10 V as defined for an input of 1, but the 9.3 V is sufficiently large to 
be considered a 1 level. The output is therefore at a 1 level with only one input, which suggests 
that the gate is an OR gate. An analysis of the same network with two 10-V inputs will result 
in both diodes being in the “on” state and an output of 9.3 V. A 0-V input at both inputs will 
not provide the 0.7 V required to turn the diodes on, and the output will be a 0 due to the 0-V 
output level. For the network of Fig. 2.41 the current level is determined by 



I = 




10 V - 0.7 V 

ikn 



9.3 mA 



EXAMPLE 2.15 Determine the output level for the positive logic AND gate of Fig. 2.42. 
An AND gate is one where a 1 output is only obtained when a 1 input appears at each and 
every input. 

Solution: Note in this case that an independent source appears in the grounded leg of the 
network. For reasons soon to become obvious, it is chosen at the same level as the input 
logic level. The network is redrawn in Fig. 2.43 with our initial assumptions regarding the 
state of the diodes. With 10 V at the cathode side of D\ it is assumed that D\ is in the “off’ 
state even though there is a 10-V source connected to the anode of D\ through the resistor. 

° ° 



(1) Si 




I 



(i) 

+ 

E l — 10 V 




( 0 ) 



I 




= V K = 0.7 V (a 0 level) 



FIG. 2.42 

Positive logic AND gate. 



FIG. 2.43 

Substituting the assumed states for the diodes of Fig. 2.42. 



72 



DIODE APPLICATIONS 



However, recall that we mentioned in the introduction to this section that the use of the 
approximate model will be an aid to the analysis. For D h where will the 0.7 V come from 
if the input and source voltages are at the same level and creating opposing “pressures”? 
D 2 is assumed to be in the “on” state due to the low voltage at the cathode side and the 
availability of the 10-V source through the 1-kH resistor. 

For the network of Fig. 2.43 the voltage at V 0 is 0.7 V due to the forward-biased diode 
D 2 . With 0.7 V at the anode of D\ and 10 V at the cathode, D\ is definitely in the “off’ 
state. The current I will have the direction indicated in Fig. 2.43 and a magnitude equal to 



I = 




10 V - 0.7 V 
1 kll 



9.3 mA 



The state of the diodes is therefore confirmed and our earlier analysis was correct. Al- 
though not 0 V as earlier defined for the 0 level, the output voltage is sufficiently small to 
be considered a 0 level. For the AND gate, therefore, a single input will result in a 0-level 
output. The remaining states of the diodes for the possibilities of two inputs and no inputs 
will be examined in the problems at the end of the chapter. 

2.6 SINUSOIDAL INPUTS; HALF-WAVE 

RECTIFICATION ^ 

The diode analysis will now be expanded to include time-varying functions such as the 
sinusoidal waveform and the square wave. There is no question that the degree of diffi- 
culty will increase, but once a few fundamental maneuvers are understood, the analysis 
will be fairly direct and follow a common thread. 

The simplest of networks to examine with a time-varying signal appears in Fig. 2.44. For 
the moment we will use the ideal model (note the absence of the Si, Ge, or GaAs label) to 
ensure that the approach is not clouded by additional mathematical complexity. 





-o 

+ 



FIG. 2.44 

Half-wave rectifier. 



Over one full cycle, defined by the period 7 of Fig. 2.44, the average value (the algebraic 
sum of the areas above and below the axis) is zero. The circuit of Fig. 2.44, called a half-wave 
rectifier , will generate a waveform v 0 that will have an average value of particular use in the 
ac-to-dc conversion process. When employed in the rectification process, a diode is typically 
referred to as a rectifier. Its power and current ratings are typically much higher than those 
of diodes employed in other applications, such as computers and communication systems. 

During the interval t = 0 — > 7/ 2 in Fig. 2.44 the polarity of the applied voltage v t is such 
as to establish “pressure” in the direction indicated and turn on the diode with the polarity 
appearing above the diode. Substituting the short-circuit equivalence for the ideal diode will 
result in the equivalent circuit of Fig. 2.45, where it is fairly obvious that the output signal 
is an exact replica of the applied signal. The two terminals defining the output voltage are 
connected directly to the applied signal via the short-circuit equivalence of the diode. 

For the period 7/2 —> 7, the polarity of the input v t is as shown in Fig. 2.46, and the 
resulting polarity across the ideal diode produces an “off’ state with an open-circuit equiva- 
lent. The result is the absence of a path for charge to flow, and v 0 = iR = (0)7 = 0 V for 
the period 7/2 —> 7. The input v z - and the output v Q are sketched together in Fig. 2.47 for 
comparison purposes. The output signal v 0 now has a net positive area above the axis over 




t 



FIG. 2.45 

Conduction region (0—>T/2). 




FIG. 2.46 

Nonconduction region (T/2—> T). 




a full period and an average value determined by 



V dc = 0.318 V m 



half-wave 



( 2 . 7 ) 



The process of removing one-half the input signal to establish a dc level is called half- 
wave rectification. 

The effect of using a silicon diode with V K = 0.7 V is demonstrated in Fig. 2.48 for the 
forward-bias region. The applied signal must now be at least 0.7 V before the diode can turn 
“on.” For levels of v t less than 0.7 V, the diode is still in an open-circuit state and v 0 = 0 V, 
as shown in the same figure. When conducting, the difference between v 0 and v t is a fixed 




FIG. 2.48 



Effect of V K on half-wave rectified signal. 



SINUSOIDAL INPUTS; 

HALF-WAVE 

RECTIFICATION 






74 



DIODE APPLICATIONS 



level of V K = 0.7 V and v Q = v t — V K , as shown in the figure. The net effect is a reduction 
in area above the axis, which reduces the resulting dc voltage level. For situations where 
V m » V K , the following equation can be applied to determine the average value with a 
relatively high level of accuracy. 



Vdc = 0.318(V m - V K ) 



( 2 . 8 ) 



In fact, if V m is sufficiently greater than V K , Eq. (2.7) is often applied as a first approxi- 
mation for V dc . 



EXAMPLE 2.16 

a. Sketch the output v 0 and determine the dc level of the output for the network of Fig. 2.49. 

b. Repeat part (a) if the ideal diode is replaced by a silicon diode. 

c. Repeat parts (a) and (b) if V m is increased to 200 V, and compare solutions using Eqs. 
(2.7) and (2.8). 



0 




T t 



o- 

+ 



v i 



H 




-o 

+ 



FIG. 2.49 

Network for Example 2.16. 



Solution: 

a. In this situation the diode will conduct during the negative part of the input as shown in 
Fig. 2.50, and v Q will appear as shown in the same figure. For the full period, the dc level is 

V dc = -0.31 8 V m = -0.318(20 V) = -6.36 V 

The negative sign indicates that the polarity of the output is opposite to the defined 
polarity of Fig. 2.49. 




FIG. 2.50 

Resulting v 0 for the circuit of Example 2.16. 






i v / ' i v / ' 

V r V 



20 V-0.7 V= 19.3 V 



FIG. 2.51 

Effect of Vx on output of 
Fig. 2.50. 



b. For a silicon diode, the output has the appearance of Fig. 2.51, and 

y dc = -0.318(V m - 0.7 V) = -0.318(19.3 V) = -6.14 V 
The resulting drop in dc level is 0.22 V, or about 3.5%. 

c. Eq. (2.7): V dc = -0.318 V m = -0.318(200 V) = -63.6 V 

Eq. (2.8): V dc = -0.318(V m - V K ) = -0.318(200 V - 0.7 V) 

= -(0.318)(199.3 V) = -63.38 V 

which is a difference that can certainly be ignored for most applications. For part (c) the 
offset and drop in amplitude due to V K would not be discernible on a typical oscillo- 
scope if the full pattern is displayed. 



FULL- WAVE 
RECTIFICATION 



75 



PIV (PRV) 



The peak inverse voltage (PIV) [or PRV (peak reverse voltage)] rating of the diode is of 
primary importance in the design of rectification systems. Recall that it is the voltage rat- 
ing that must not be exceeded in the reverse-bias region or the diode will enter the Zener 
avalanche region. The required PIV rating for the half-wave rectifier can be determined 
from Fig. 2.52, which displays the reverse-biased diode of Fig. 2.44 with maximum applied 
voltage. Applying Kirchhoff’ s voltage law, it is fairly obvious that the PIV rating of the 
diode must equal or exceed the peak value of the applied voltage. Therefore, 



PIV rating ^ V m 



half-wave rectifier 



( 2 . 9 ) 



V(PIV) + 




-o 



V D = IR = (0 )R = 0 V 

+ 

-o 



FIG. 2.52 

Determining the required PIV rating for the 
half-wave rectifier. 



2.7 FULL-WAVE RECTIFICATION ^ 

Bridge Network 

The dc level obtained from a sinusoidal input can be improved 100% using a process 
called full-wave rectification. The most familiar network for performing such a function 
appears in Fig. 2.53 with its four diodes in a bridge configuration. During the period t = 0 
to Tj 2 the polarity of the input is as shown in Fig. 2.54. The resulting polarities across the 
ideal diodes are also shown in Fig. 2.54 to reveal that D 2 and D 3 are conducting, whereas 
Di and D 4 are in the “off’ state. The net result is the configuration of Fig. 2.55, with its 
indicated current and polarity across R. Since the diodes are ideal, the load voltage is 
v 0 = Vi, as shown in the same figure. 






FIG. 2.53 

Full-wave bridge rectifier. 



FIG. 2.54 

Network of Fig. 2.53 for the period 
O^T 1 2 of the input voltage v t . 




FIG. 2.55 

Conduction path for the positive region ofvi. 



76 DIODE APPLI CAT IONS For the negative region of the input the conducting diodes are D \ and Z) 4 , resulting in the 

configuration of Fig. 2.56. The important result is that the polarity across the load resistor R 
is the same as in Fig. 2.54, establishing a second positive pulse, as shown in Fig. 2.56. Over 
one full cycle the input and output voltages will appear as shown in Fig. 2.57. 





Input and output waveforms for a full-wave rectifier. 



Since the area above the axis for one full cycle is now twice that obtained for a half-wave 
system, the dc level has also been doubled and 

V dc = 2[Eq.(2.7)] = 2(0.3 18V m ) 



or 



V dc = 0.636 V m 



full-wave 



( 2 . 10 ) 



If silicon rather than ideal diodes are employed as shown in Fig. 2.58, the application of 
Kirchhoff’ s voltage law around the conduction path results in 

Vi - V K - v a - V K = 0 

and v 0 = v t - 2V K 




7771 



V m - 2V] 



K 



T t 



Determining V 0max f or silicon diodes in the bridge configuration. 

The peak value of the output voltage v 0 is therefore 

Kw = ^ - 2^ 

For situations where V m » 2V K , the following equation can be applied for the average 
value with a relatively high level of accuracy: 



V dc = 0.636(V m - 2V*) 



( 2 . 11 ) 



Then again, if V m is sufficiently greater than 2V K , then Eq. (2.10) is often applied as a first 
approximation for V dc . 



The required PIV of each diode (ideal) can be determined from Fig. 2.59 obtained at 
the peak of the positive region of the input signal. For the indicated loop the maximum 
voltage across R is V m and the PIV rating is defined by 



PIV ^ V m 



full-wave bridge rectifier 



( 2 . 12 ) 



Center-Tapped Transformer 

A second popular full- wave rectifier appears in Fig. 2.60 with only two diodes but requir- 
ing a center-tapped (CT) transformer to establish the input signal across each section of the 
secondary of the transformer. During the positive portion of v t applied to the primary of the 
transformer, the network will appear as shown in Fig. 2.61 with a positive pulse across 
each section of the secondary coil. D\ assumes the short-circuit equivalent and D 2 the 
open-circuit equivalent, as determined by the secondary voltages and the resulting current 
directions. The output voltage appears as shown in Fig. 2.61. 



FULL- WAVE 77 

RECTIFICATION 




FIG. 2.59 

Determining the required PIV for 
the bridge configuration. 





FIG. 2.60 

Center-tapped transformer full-wave rectifier. 




FIG. 2.61 

Network conditions for the positive region ofv(. 



t 



During the negative portion of the input the network appears as shown in Fig. 2.62, revers- 
ing the roles of the diodes but maintaining the same polarity for the voltage across the load re- 
sistor R. The net effect is the same output as that appearing in Fig. 2.57 with the same dc levels. 




FIG. 2.62 

Network conditions for the negative region ofv[. 






78 DIODE APPLICATIONS 



- PIV + 




+ 

WSr 

- + 



The network of Fig. 2.63 will help us determine the net PIV for each diode for this 
full-wave rectifier. Inserting the maximum voltage for the secondary voltage and V m as 
established by the adjoining loop results in 

PIV V SeCOn( j ar y ~E V* 

= V + V 

v m ' v m 



and 



PIV > 2V m 



CT transformer, full-wave rectifier 



( 2 . 13 ) 



FIG. 2.63 

Determining the PIV level for 
the diodes of the CT transformer 
full-wave rectifier. 



EXAMPLE 2.17 Determine the output waveform for the network of Fig. 2.64 and calcu- 
late the output dc level and the required PIV of each diode. 





FIG. 2.64 

Bridge network for Example 2.17. 




FIG. 2.65 

Network of Fig. 2.64 for the positive region ofv t . 



FIG. 2.66 

Redrawn network of Fig. 2.65. 




Resulting output for Example 2.17. 



Solution: The network appears as shown in Fig. 2.65 for the positive region of the input 
voltage. Redrawing the network results in the configuration of Fig. 2.66, where v 0 = or 
V 0m ax = = ±<10 V) = 5 V, as shown in Fig. 2.66. For the negative part of the input, 

the roles of the diodes are interchanged and v 0 appears as shown in Fig. 2.67. 

The effect of removing two diodes from the bridge configuration is therefore to reduce 
the available dc level to the following: 

V dc = 0.636(5 V) = 3.18 V 

or that available from a half-wave rectifier with the same input. However, the PIV as deter- 
mined from Fig. 2.59 is equal to the maximum voltage across R , which is 5 V, or half of 
that required for a half-wave rectifier with the same input. 



2.8 CLIPPERS ^ 

The previous section on rectification gives clear evidence that diodes can be used to change 
the appearance of an applied waveform. This section on clippers and the next on clampers 
will expand on the wave-shaping abilities of diodes. 

Clippers are networks that employ diodes to “clip” away a portion of an input signal 
without distorting the remaining part of the applied waveform . 



CUPPERS 



79 



The half-wave rectifier of Section 2.6 is an example of the simplest form of diode clipper — 
one resistor and a diode. Depending on the orientation of the diode, the positive or negative 
region of the applied signal is “clipped” off. 

There are two general categories of clippers: series and parallel. The series configura- 
tion is defined as one where the diode is in series with the load, whereas the parallel variety 
has the diode in a branch parallel to the load. 

Series 

The response of the series configuration of Fig. 2.68a to a variety of alternating waveforms 
is provided in Fig. 2.68b. Although first introduced as a half-wave rectifier (for sinusoidal 
waveforms), there are no boundaries on the type of signals that can be applied to a clipper. 




FIG. 2.68 
Series clipper. 











rrl'lt* - 1 


► ° 




J 


+ 


0 


t\ It t Vj < 






o-t- 


i 0 



FIG. 2.69 

Series clipper with a dc supply. 



The addition of a dc supply to the network as shown in Fig. 2.69 can have a pronounced 
effect on the analysis of the series clipper configuration. The response is not as obvious 
because the dc supply can aid or work against the source voltage, and the dc supply can be 
in the leg between the supply and output or in the branch parallel to the output. 

There is no general procedure for analyzing networks such as the type in Fig. 2.69, but 
there are some things one can do to give the analysis some direction. 

First and most important: 

1. Take careful note of where the output voltage is defined. 

In Fig. 2.69 it is directly across the resistor R. In some cases it may be across a combi- 
nation of series elements. 

Next: 

2. Try to develop an overall sense of the response by simply noting the “pressure” 
established by each supply and the effect it will have on the conventional current 
direction through the diode. 

In Fig. 2.69, for instance, any positive voltage of the supply will try to turn the diode on 
by establishing a conventional current through the diode that matches the arrow in the 
diode symbol. However, the added dc supply V will oppose that applied voltage and try to 
keep the diode in the “off’ state. The result is that any supply voltage greater than V volts 
will turn the diode on and conduction can be established through the load resistor. Keep in 
mind that we are dealing with an ideal diode for the moment, so the turn-on voltage is 
simply 0 V. In general, therefore, for the network of Fig. 2.69 we can conclude that the 



80 DIODE APPLICATIONS 



diode will be on for any voltage v t that is greater than V volts and off for any lesser voltage. 
For the “off’ condition, the output would be 0 V due to the lack of current, and for the “on” 
condition it would simply be v Q = v t — V as determined by Kirchhoff s voltage law. 

3. Determine the applied voltage (transition voltage) that will result in a change of 
state for the diode from the “off’ to the “on” state. 

This step will help to define a region of the applied voltage when the diode is on and 
when it is off. On the characteristics of an ideal diode this will occur when V D = 0 V and 
Id = 0 mA. For the approximate equivalent this is determined by finding the applied volt- 
age when the diode has a drop of 0.7 V across it (for silicon) and I D = 0 mA. 

This exercise was applied to the network of Fig. 2.69 as shown in Fig. 2.70. Note the 
substitution of the short-circuit equivalent for the diode and the fact that the voltage across 
the resistor is 0 V because the diode current is 0 mA. The result is v t — V = 0, and so 




( 2 . 14 ) 



is the transition voltage. 




FIG. 2.71 

Using the transition voltage to 
define the “ on ” and “ off ” regions. 




v 0 = i R R = i d R= (0)R = 0 V 



FIG. 2.70 

Determining the transition level for the circuit of Fig. 2.69. 



This permits drawing a line on the sinusoidal supply voltage as shown in Fig. 2.71 to 
define the regions where the diode is on and off. 

For the “on” region, as shown in Fig. 2.72, the diode is replaced by a short-circuit 
equivalent, and the output voltage is defined by 



rH'F 





-o 

+ 



FIG. 2.72 

Determining v Q for the diode 
in the “on ” state. 




Sketching the waveform ofv 0 using 
the results obtained for v 0 above 
and below the transition level. 




( 2 . 15 ) 



For the “off’ region, the diode is an open circuit, Id ~ 0 mA, and the output voltage is 

v 0 = 0V 



4. It is often helpful to draw the output waveform directly below the applied voltage 
using the same scales for the horizontal axis and the vertical axis. 

Using this last piece of information, we can establish the 0-V level on the plot of Fig. 2.73 
for the region indicated. For the “on” condition, Eq. (2.15) can be used to find the output 
voltage when the applied voltage has its peak value: 

V Opeak _ Vm ~ V 

and this can be added to the plot of Fig. 2.73. It is then simple to fill in the missing section 
of the output curve. 



EXAMPLE 2.18 Determine the output waveform for the sinusoidal input of Fig. 2.74. 

Solution: 

Step 1: The output is again directly across the resistor R. 

Step 2: The positive region of Vi and the dc supply are both applying “pressure” to turn the 
diode on. The result is that we can safely assume the diode is in the “on” state for the entire 
range of positive voltages for v t . Once the supply goes negative, it would have to exceed 
the dc supply voltage of 5 V before it could turn the diode off. 





CUPPERS 81 



FIG. 2.74 

Series clipper for Example 2.18. 

Step 3: The transition model is substituted in Fig. 2.75, and we find that the transition 
from one state to the other will occur when 

+ 5 V = 0 V 

or Vf = — 5 V 



- , ,+ ^ = ov 

HI 

+ 5 \ 

Vf 




°f 




-o 

+ 



v 0 — vr — iftR — idR — (0) R — 0 V 



-o 



FIG. 2.75 

Determining the transition level for the clipper of Fig. 2.74. 



Step 4: In Fig. 2.76 a horizontal line is drawn through the applied voltage at the transition 
level. For voltages less than —5 V the diode is in the open-circuit state and the output is 0 
V, as shown in the sketch of v 0 . Using Fig. 2.76, we find that for conditions when the diode 
is on and the diode current is established the output voltage will be the following, as deter- 
mined using Kirchhoff s voltage law: 

= v t + 5 V 




The analysis of clipper networks with square- wave inputs is actually easier than with si- 
nusoidal inputs because only two levels have to be considered. In other words, the network 
can be analyzed as if it had two dc level inputs with the resulting v 0 plotted in the proper 
time frame. The next example demonstrates the procedure. 



EXAMPLE 2.19 Find the output voltage for the network examined in Example 2.18 if the 
applied signal is the square wave of Fig. 2.77. 

Solution: For v t = 20 V (0 — > T /2) the network of Fig. 2.78 results. The diode is in the 
short-circuit state, and v Q = 20 V + 5 V = 25 V. For v t = -10 V the network of Fig. 2.79 




Applied signal for Example 2.19. 



82 DIODE APPLICATIONS 



results, placing the diode in the “off’ state, and v 0 = i R R = (0)7? = 0 V. The resulting 
output voltage appears in Fig. 2.80. 







% 








25 V 






0 V 


0 


T T t 




2 



FIG. 2.80 

Sketching v 0 for Example 2.19. 



Note in Example 2.19 that the clipper not only clipped off 5 V from the total swing, but 
also raised the dc level of the signal by 5 V. 

Parallel 

The network of Fig. 2.81 is the simplest of parallel diode configurations with the output for 
the same inputs of Fig. 2.68. The analysis of parallel configurations is very similar to that 
applied to series configurations, as demonstrated in the next example. 



o WV 

+ R 




FIG. 2.81 

Response to a parallel clipper. 



EXAMPLE 2.20 Determine v 0 for the network of Fig. 2.82. 

Solution: 

Step 1: In this example the output is defined across the series combination of the 4-V sup- 
ply and the diode, not across the resistor R. 




FIG. 2.82 

Example 2.20. 




CUPPERS 83 



Step 2: The polarity of the dc supply and the direction of the diode strongly suggest that 
the diode will be in the “on” state for a good portion of the negative region of the input 
signal. In fact, it is interesting to note that since the output is directly across the series com- 
bination, when the diode is in its short-circuit state the output voltage will be directly 
across the 4-V dc supply, requiring that the output be fixed at 4 V. In other words, when 
the diode is on the output will be 4 V. Other than that, when the diode is an open circuit, 
the current through the series network will be 0 mA and the voltage drop across the resistor 
will be 0 V. That will result in v 0 = v t whenever the diode is off. 

Step 3: The transition level of the input voltage can be found from Fig. 2.83 by substitut- 
ing the short-circuit equivalent and remembering the diode current is 0 mA at the instant of 
transition. The result is a change in state when 

v f = 4 V 

Step 4: In Fig. 2.84 the transition level is drawn along with v Q = 4 V when the diode is 
on. For v* > 4 V, v Q = 4 V, and the waveform is simply repeated on the output plot. 



v* = 0V 




v, 6 

+ 

V 4 V 

o- o 

FIG. 2.83 

Determining the transition level 
for Example 2.20. 




To examine the effects of the knee voltage V K of a silicon diode on the output response, 
the next example will specify a silicon diode rather than the ideal diode equivalent. 



v R = i R R = i d R = (0)R = 0V 
R 



o WV 

+ i d = 0 A 

V/ 



o 




-o 

+ 



-o 



FIG. 2.85 

Determining the transition level for 
the network of Fig. 2.82. 



EXAMPLE 2.21 Repeat Example 2.20 using a silicon diode with V K = 0.7 V. 

Solution: The transition voltage can first be determined by applying the condition i d = 0 A 
at v d = Vd = 0-7 V and obtaining the network of Fig. 2.85. Applying Kirchhoff’ s voltage 
law around the output loop in the clockwise direction, we find that 

Vi+V K -V= 0 

and vi = V - V K = 4 V - 0.7 V = 3.3 V 

For input voltages greater than 3.3 V, the diode will be an open circuit and v Q = v*. For 
input voltages less than 3.3 V, the diode will be in the “on” state and the network of Fig. 2.86 
results, where 

Vp — 4 V 0.7 V — 3.3 \ 

The resulting output waveform appears in Fig. 2.87. Note that the only effect of V K was to 
drop the transition level to 3.3 from 4 V. 



There is no question that including the effects of V K will complicate the analysis some- 
what, but once the analysis is understood with the ideal diode, the procedure, including the 
effects of V K , will not be that difficult. 



o VW 

+ R 




o- 




-o 

+ 



FIG. 2.86 

Determining v 0 for the diode of 
Fig. 2.82 in the “on” state. 





‘ V o 


16 V 
3.3 V 


A-n . 


0 


T T t 

2 



FIG. 2.87 

Sketching v 0 for Example 2.21. 



Simple Series Clippers (Ideal Diodes) 



POSITIVE 




Biased Series Clippers (Ideal Diodes) 




H'l'.w i : 

V < 

v,- R 5 o 


‘ 0 


T 

-<% + V) 

> V o 




+ -v + " 1 + 

v i R< v 0 

" | - V 




• o 0 


t 

_ /!/ \7\ 



NEGATIVE 





0 

-V 



7\(Vn-V) 



t 




Simple Parallel Clippers (Ideal Diodes) 




Biased Parallel Clippers (Ideal Diodes) 




o 

+ R 





Pi 

0 

-V 2 






Ivj>|v 2 | 



FIG. 2.88 
Clipping circuits. 




o 

+ R 

v/ 





V 

0 



V m 



t 



84 



Summary 

A variety of series and parallel clippers with the resulting output for the sinusoidal input 
are provided in Fig. 2.88. In particular, note the response of the last configuration, with its 
ability to clip off a positive and a negative section as determined by the magnitude of the 
dc supplies. 

2.9 CLAMPERS ^ 

The previous section investigated a number of diode configurations that clipped off a por- 
tion of the applied signal without changing the remaining part of the waveform. This sec- 
tion will examine a variety of diode configurations that shift the applied signal to a 
different level. 

A clamper is a network constructed of a diode , a resistor , and a capacitor that shifts a 
waveform to a different dc level without changing the appearance of the applied signal. 

Additional shifts can also be obtained by introducing a dc supply to the basic structure. 
The chosen resistor and capacitor of the network must be chosen such that the time constant 
determined by t = RC is sufficiently large to ensure that the voltage across the capacitor 
does not discharge significantly during the interval the diode is nonconducting. Through- 
out the analysis we assume that for all practical purposes the capacitor fully charges or 
discharges in five time constants. 

The simplest of clamper networks is provided in Fig. 2.89. It is important to note that 
the capacitor is connected directly between input and output signals and the resistor and the 
diode are connected in parallel with the output signal. 

Clamping networks have a capacitor connected directly from input to output with a 
resistive element in parallel with the output signal. The diode is also in parallel with the 
output signal but may or may not have a series dc supply as an added element. 




FIG. 2.89 

Clamper. 



There is a sequence of steps that can be applied to help make the analysis straightfor- 
ward. It is not the only approach to examining clampers, but it does offer an option if dif- 
ficulties surface. 

Step 1: Start the analysis by examining the response of the portion of the input signal 
that will forward bias the diode. 

Step 2: During the period that the diode is in the “on” state, assume that the capac- 
itor will charge up instantaneously to a voltage level determined by the surrounding 
network. 

For the network of Fig. 2.89 the diode will be forward biased for the positive portion of 
the applied signal. For the interval 0 to T/2 the network will appear as shown in Fig. 2.90. 
The short-circuit equivalent for the diode will result in v 0 = 0 V for this time interval, as 
shown in the sketch of v Q in Fig. 2.92. During this same interval of time, the time constant 
determined by r = RC is very small because the resistor R has been effectively “shorted 
out” by the conducting diode and the only resistance present is the inherent (contact, wire) 
resistance of the network. The result is that the capacitor will quickly charge to the peak 
value of V volts as shown in Fig. 2.90 with the polarity indicated. 

Step 3: Assume that during the period when the diode is in the “off” state the capac- 
itor holds on to its established voltage level. 



CLAMPERS 85 



c 




FIG. 2.90 

Diode “on ” and the capacitor 
charging to V volts. 



86 DIODE APPLICATIONS 



C 




FIG. 2.91 

Determining v 0 with the diode “ off. 




FIG. 2.92 

Sketching v Q for the network of 
Fig. 2.91. 



Step 4: Throughout the analysis, maintain a continual awareness of the location and 
defined polarity for v 0 to ensure that the proper levels are obtained. 

When the input switches to the — V state, the network will appear as shown in Fig. 2.91, 
with the open-circuit equivalent for the diode determined by the applied signal and stored 
voltage across the capacitor — both “pressuring” current through the diode from cathode to 
anode. Now that R is back in the network the time constant determined by the RC product 
is sufficiently large to establish a discharge period 5 r, much greater than the period 
T/2 -> T, and it can be assumed on an approximate basis that the capacitor holds onto all 
its charge and, therefore, voltage (since V = Q/C) during this period. 

Since v 0 is in parallel with the diode and resistor, it can also be drawn in the alternative 
position shown in Fig. 2.91. Applying Kirchhoff’ s voltage law around the input loop results in 

-V ~ V - v 0 = 0 

and v Q = —2V 

The negative sign results from the fact that the polarity of 2 V is opposite to the polarity 
defined for v 0 . The resulting output waveform appears in Fig. 2.92 with the input signal. 
The output signal is clamped to 0 V for the interval 0 to T/2 but maintains the same total 
swing (2 V) as the input. 

Step 5: Check that the total swing of the output matches that of the input. 

This is a property that applies for all clamping networks, giving an excellent check on 
the results obtained. 



EXAMPLE 2.22 Determine v 0 for the network of Fig. 2.93 for the input indicated. 




C = lfiF 




c 




FIG. 2.94 

Determining v 0 and V c with the 
diode in the “on ” state. 



FIG. 2.93 

Applied signal and network for Example 2.22. 



Solution: Note that the frequency is 1000 Hz, resulting in a period of 1 ms and an inter- 
val of 0.5 ms between levels. The analysis will begin with the period t x — > t 2 of the input 
signal since the diode is in its short-circuit state. For this interval the network will appear 
as shown in Fig. 2.94. The output is across R , but it is also directly across the 5-V battery 
if one follows the direct connection between the defined terminals for v 0 and the battery 
terminals. The result is v Q = 5 V for this interval. Applying Kirchhoff s voltage law around 
the input loop results in 




FIG. 2.95 

Determining v Q with the diode 
in the “off” state. 



-20 V + V c - 5 V = 0 
and V c = 25 V 

The capacitor will therefore charge up to 25 V. In this case the resistor R is not shorted 
out by the diode, but a Thevenin equivalent circuit of that portion of the network that 
includes the battery and the resistor will result in R Th = 0 12 with E Th = V = 5 V. For 
the period t 2 — > t 2 the network will appear as shown in Fig. 2.95. 

The open-circuit equivalent for the diode removes the 5-V battery from having any 
effect on v 0 , and applying Kirchhoff s voltage law around the outside loop of the network 
results in 



and 



+ 10 V + 25 V - = 0 

v n — 35 V 



The time constant of the discharging network of Fig. 2.95 is determined by the product 
RC and has the magnitude 

t = RC = (100kI2)(0.1 /ulF) = 0.01 s — 10 ms 

The total discharge time is therefore 5 r = 5(10 ms) = 50 ms. 

Since the interval t 2 — > t 2 will only last for 0.5 ms, it is certainly a good approximation 
that the capacitor will hold its voltage during the discharge period between pulses of the 
input signal. The resulting output appears in Fig. 2.96 with the input signal. Note that the 
output swing of 30 V matches the input swing as noted in step 5. 





FIG. 2.96 

and v Q for the clamper of Fig. 2.93. 



EXAMPLE 2.23 Repeat Example 2.22 using a silicon diode with V K = 0.7 V. 

Solution: For the short-circuit state the network now takes on the appearance of Fig. 
2.97, and v 0 can be determined by Kirchhoff’ s voltage law in the output section: 

+5 V - 0.7 V - = 0 

and v 0 — 5 V 0.7 V = 4.3 V 

For the input section Kirchhoff’ s voltage law results in 

-20 V + V c + 0.7 V - 5 V = 0 
and V c = 25 V - 0.7 V = 24.3 V 

For the period t 2 — > t 2 the network will now appear as in Fig. 2.98, with the only change 
being the voltage across the capacitor. Applying Kirchhoff s voltage law yields 

+ 10 V + 24.3 V ~ v 0 = 0 
and v 0 = 34.3 V 

The resulting output appears in Fig. 2.99, verifying the statement that the input and output 
swings are the same. 




Sketching v 0 for the clamper of Fig. 2.93 
with a silicon diode. 



CLAMPERS 87 




FIG. 2.97 

Determining v 0 and V c with the 
diode in the “on ” state. 




J 



FIG. 2.98 

Determining v 0 with the diode 
in the open state. 



Clamping Networks 












T 

2V 

1 , 


- 






±7 



FIG. 2.100 

Clamping circuits with ideal diodes (5 t = 5RC » T/2). 



A number of clamping circuits and their effect on the input signal are shown in 
Fig. 2.100. Although all the waveforms appearing in Fig. 2.100 are square waves, clamp- 
ing networks work equally well for sinusoidal signals. In fact, one approach to the analysis 
of clamping networks with sinusoidal inputs is to replace the sinusoidal signal by a square 
wave of the same peak values. The resulting output will then form an envelope for the 
sinusoidal response as shown in Fig. 2.101 for a network appearing in the bottom right of 
Fig. 2.100. 




o- 

+ 

Vi 



K 




-o 

+ 




FIG. 2.101 

Clamping network with a sinusoidal input. 



2.10 NETWORKS WITH A DC AND AC SOURCE 



The analysis thus far has been limited to circuits with a single dc, ac, or square wave input. 
This section will expand that analysis to include both an ac and a dc source in the same 
configuration. In Fig. 2.102 the simplest of two-source networks has been constructed. 



For such a system it is especially important that the Superposition Theorem can be applied. 
That is, 

The response of any network with both an ac and a dc source can be found by finding 
the response to each source independently and then combining the results. 

DC Source 

The network is redrawn as shown in Fig. 2.103 for the dc source. Note that the ac source was 
removed by simply replacing it with a short-circuit equivalent to the condition v s = 0\. 
Using the approximate equivalent circuit for the diode, the output voltage is 

V R = E - V D = 10 V - 0.7 V = 9.3 V 
9.3 V 

and the currents are I D = I R = — = 4.65 uiA 

2 kll 



NETWORKS WITH A DC 89 
AND AC SOURCE 



+ vd - 




AC Source 



The dc source is also replaced by a short-circuit equivalent, as shown in Fig. 2.104. The 
diode will be replaced by the ac resistance, as determined by Eq. 1.5 in Chapter 1 — the 
current in the equation being the quiescent or dc value. For this case, 



U = 



26 mV 
Id 



26 mV 
4.65 mA 



5.5912 



+ 0.7 V - 






FIG. 2.103 

Applying superposition to determine 
effects of the dc source. 



FIG. 2.104 

Determing the response ofv R to the applied ac source. 



Replacing the diode by this resistance will result in the circuit of Fig. 2. 105. For the peak 
value of the applied voltage, the peak values of v R and v D will be 

2 kI2 (2 V) 



and 



VSpeak 2 k a + 5.59 fl 



= 1.99 V 



^^peak Upeak 



- v R = 2 V - 1.99 V = 0.01 V = 10 mV 

•“■peak 



^peak ' 



= 2V % 



+ v D - 

r d 

— wv — 

5.59 n 



+ 

R ^ 2 kll v R 



FIG. 2.105 

Replacing the diode of Fig. 2.104 by its 
equivalent ac resistance. 



Combining the results of the dc and ac analysis will result in the waveforms of Fig. 2.106 
for v R and v D . 



% = 9-3V 





FIG. 2.106 

(a) Vr and (b) v^for the network of Fig. 2.102. 



Note that the diode has an important impact on the resulting output voltage but very 
little impact on the ac swing. 

For comparison purposes the same system will now be analyzed using the actual charac- 
teristics and a load-line analysis. In Fig. 2.107 the dc load line has been drawn as described 
in Section 2.2. The resulting dc current is now slightly less due to a voltage drop across the 
diode that is slightly more than the approximate value of 0.7 V. For the peak value of the 
input voltage the load line will have intersections of E = 12 V and 1 = f = = 6 mA. For 

the negative peak the intersections are at 8 V and 4 mA. Take particular note of the region 
of the diode characteristics traversed by the ac swing. It defines the region for which the 
diode resistance was determined in the analysis above. In this case, however, the quiescent 
value of dc current is =4.6 mA so the new ac resistance is 



26 mV 
4.6 mA 



which is very close to the above value. 



5.65 12 




90 



FIG. 2.107 

Shifting load line due to v s , source. 



In any event, it is now clear that the change in diode voltage for this region is very small, ZENER DIODES 

resulting in minimum impact on the output voltage. In general, the diode had a strong im- 
pact on the dc level of the output voltage but very little impact on the ac swing of the output. 

The diode was clearly close to ideal for the ac voltage and 0.7 V off for the dc level. This is 
all due primarily to the almost vertical rise of the diode once conduction is fully established 
through the diode. In most cases, diodes in the “on” state that are in series with loads will 
have some effect on the dc level but very little effect on the ac swing if the diode is fully 
conducting for the full cycle. 

For the future, when dealing with diodes and an ac signal the dc level through the diode 
is first determined and the ac resistance level determined by Eq. 1.3. This ac resistance can 
then be substituted in place of the diode for the required analysis. 



2.11 ZENER DIODES ^ 

The analysis of networks employing Zener diodes is quite similar to the analysis of semi- 
conductor diodes in previous sections. First the state of the diode must be determined, 
followed by a substitution of the appropriate model and a determination of the other 
unknown quantities of the network. Figure 2.108 reviews the approximate equivalent cir- 
cuits for each region of a Zener diode assuming the straight-line approximations at each 
break point. Note that the forward-bias region is included because occasionally an applica- 
tion will skip into this region also. 




FIG. 2.108 

Approximate equivalent circuits for the Zener diode in the three possible 
regions of application. 

The first two examples will demonstrate how a Zener diode can be used to establish 
reference voltage levels and act as a protection device. The use of a Zener diode as a regu- 
lator will then be described in detail because it is one of its major areas of application. A 
regulator is a combination of elements designed to ensure that the output voltage of a supply 
remains fairly constant. 



EXAMPLE 2.24 Determine the reference voltages provided by the network of Fig. 2.109, 
which uses a white FED to indicate that the power is on. What is the level of current 
through the FED and the power delivered by the supply? How does the power absorbed by 
the FED compare to that of the 6-V Zener diode? 

Solution: First we have to check that there is sufficient applied voltage to turn on all the 
series diode elements. The white FED will have a drop of about 4 V across it, the 6-V and 
3.3-V Zener diodes have a total of 9.3 V, and the forward-biased silicon diode has 0.7 V, 
for a total of 14 V. The applied 40 V is then sufficient to turn on all the elements and, one 
hopes, establish a proper operating current. 



40 V 




FIG. 2.109 

Reference setting circuit for 
Example 2.24. 



92 DIODE APPLICATIONS Note that the silicon diode was used to create a reference voltage of 4 V because 

V 0l = V Z2 + V K = 3.3 V + 0.7 V = 4.0V 
Combining the voltage of the 6-V Zener diode with the 4 V results in 
Vo 2 = v 0l + y Zi = 4V + 6V = 10V 

Finally, the 4 V across the white LED will leave a voltage of 40 V - 14 V = 26 V across 
the resistor, and 

V R 40 V - v 02 - V LED 40 V - 10 V - 4 V 26 V 
R R 1.3 kn 1.3 kn 1.3 kn 

which should establish the proper brightness for the LED. 

The power delivered by the supply is simply the product of the supply voltage and cur- 
rent drain as follows: 

P s = EI S = EI r = (40 V)(20 mA) = 800 mW 
The power absorbed by the LED is 

Pled = V LED / LED = (4 V)(20 mA) - 80 mW 
and the power absorbed by the 6-V Zener diode is 

P z = V Z I Z = (6 V)(20 mA) = 120 mW 
The power absorbed by the Zener diode exceeds that of the LED by 40 mW. 



EXAMPLE 2.25 The network of Fig. 2. 1 10 is designed to limit the voltage to 20 V during 
the positive portion of the applied voltage and to 0 V for a negative excursion of the 
applied voltage. Check its operation and plot the waveform of the voltage across the sys- 
tem for the applied signal. Assume the system has a very high input resistance so it will not 
affect the behavior of the network. 




Controlling network for Example 2.25. 



Solution: For positive applied voltages less than the Zener potential of 20 V the Zener 
diode will be in its approximate open-circuit state, and the input signal will simply distrib- 
ute itself across the elements, with the majority going to the system because it has such a 
high resistance level. 

Once the voltage across the Zener diode reaches 20 V the Zener diode will turn on as 
shown in Fig. 2.111a and the voltage across the system will lock in at 20 V. Further 
increases in the applied voltage will simply appear across the series resistor with the volt- 
age across the system and the forward-biased diode remaining fixed at 20 V and 0.7 V, 
respectively. The voltage across the system is fixed at 20 V, as shown in Fig. 2.111a, 
because the 0.7 V of the diode is not between the defined output terminals. The system is 
therefore safe from any further increases in applied voltage. 

For the negative region of the applied signal the silicon diode is reverse biased and 
presents an open circuit to the series combination of elements. The result is that the full 
negatively applied signal will appear across the open-circuited diode and the negative volt- 
age across the system locked in at 0 V, as shown in Fig. 2.1 1 lb. 

The voltage across the system will therefore appear as shown in Fig. 2.1 1 lc. 



ZENER DIODES 



93 



R 

^AAr 



v ; > 20.7 V 



V z —20 V 



0.7 V 



:20 V 



+ 

v ; - < 20.7 V 



R 

-VSAr 



V d=Vi 

- - + 



I D = 0 mA 



= 0V 



(a) 



(b) 




FIG. 2.111 

Response of the network of Fig. 2.110 to the application of a 60-V sinusoidal signal. 



The use of the Zener diode as a regulator is so common that three conditions surrounding 
the analysis of the basic Zener regulator are considered. The analysis provides an excellent 
opportunity to become better acquainted with the response of the Zener diode to different 
operating conditions. The basic configuration appears in Fig. 2.112. The analysis is first 
for fixed quantities, followed by a fixed supply voltage and a variable load, and finally a 
fixed load and a variable supply. 



Vj and R Fixed 

The simplest of Zener diode regulator networks appears in Fig. 2.1 12. The applied dc volt- 
age is fixed, as is the load resistor. The analysis can fundamentally be broken down into 
two steps. 

1 . Determine the state of the Zener diode by removing it from the network and 
calculating the voltage across the resulting open circuit 

Applying step 1 to the network of Fig. 2.1 12 results in the network of Fig. 2.1 13, where 
an application of the voltage divider rule results in 



V = 






R L Vi 

r + r l 



( 2 . 16 ) 



If y > y z , the Zener diode is on, and the appropriate equivalent model can be substituted. 
If y < y z , the diode is off, and the open-circuit equivalence is substituted. 

2. Substitute the appropriate equivalent circuit and solve for the desired unknowns. 

For the network of Fig. 2.112, the “on” state will result in the equivalent network of 
Fig. 2.114. Since voltages across parallel elements must be the same, we find that 



R 




R 




FIG. 2.113 

Determining the state of the 
Zener diode. 



v L = v z 



( 2 . 17 ) 



94 



DIODE APPLICATIONS 



R 

AAA r 



Ir 



+ 



Vi 





+ 

v L 



FIG. 2.114 

Substituting the Zener equivalent for the 
“on ” situation. 



The Zener diode current must be determined by an application of Kirchhoff’s current law. 
That is, 

I r = h + h 



and 

where 



I7 — Ir ~ It 



( 2 . 18 ) 



1 1 = — and 



j - 1A - 
Ir — _ — 



Vi ~ V L 



r l r r 

The power dissipated by the Zener diode is determined by 



Pz ~ V z Iz 



( 2 . 19 ) 



that must be less than the P Z m specified for the device. 

Before continuing, it is particularly important to realize that the first step was employed 
only to determine the state of the Zener diode. If the Zener diode is in the “on” state, the 
voltage across the diode is not V volts. When the system is turned on, the Zener diode will 
turn on as soon as the voltage across the Zener diode is V z volts. It will then “lock in” at 
this level and never reach the higher level of V volts. 



EXAMPLE 2.26 

a. For the Zener diode network of Fig. 2.1 15, determine V L , V R , I z , and P z . 

b. Repeat part (a) with R L = 3 kft. 



+ Vr " 

R 




Zener diode regulator for Example 2.26. 



+ 

Vl 



Solution: 

a. Following the suggested procedure, we redraw the network as shown in Fig. 2.1 16. 
Applying Eq. (2.16) gives 

R L Vi 1.2 kll(16 V) 

V = — = — = 8.73 V 

R + R l 1 kfl + 1.2 kfl 



R 

A/W 

I kO 



ZENER DIODES 95 



f R 




a 



FIG. 2.116 

Determining V for the regulator of Fig. 2.115. 



Since V = 8.73 V is less than V z — 10 V, the diode is in the “off” state, as shown on 
the characteristics of Fig. 2.117. Substituting the open-circuit equivalent results in the 
same network as in Fig. 2.1 16, where we find that 

V L = V = 8.73 V 

V R = Vi - V L = 16 V - 8.73 V = 7.27 V 
h = 0A 

and P z = V z l z = V z (0 A) = 0 W 

b. Applying Eq. (2.16) results in 

R L Vi 3 kfl( 16 V) 

V = — = J = 12 V 

r + r l i m + 3 m 

Since V = 12 V is greater than V z = 10 V, the diode is in the “on” state and the net- 
work of Fig. 2.118 results. Applying Eq. (2.17) yields 

V L = V z = 10 V 

and V R = V t - V L = 16 V - 10 V = 6 V 

V L 10 V 

with I L = — = = 3.33 mA 

L R l 3 kfl 

V R 6 V 

and h = ~R = TidT = 6mA 

so that I z = Ir ~ II [Eq. (2.18)] 

= 6 mA — 3.33 mA 

= 2.67 mA 




Resulting operating point for the 
network of Fig. 2.115. 



+ Vfe - 
R 




Network of Fig. 2.115 in the “on” state. 

The power dissipated is 

P z = V Z I Z = (10 V)(2.67 mA) = 26.7 mW 
which is less than the specified P ZM = 30 mW. 



Fixed Vj, Variable R L 

Due to the offset voltage V z , there is a specific range of resistor values (and therefore load cur- 
rent) that will ensure that the Zener is in the “on” state. Too small a load resistance R L will result 
in a voltage V L across the load resistor less than V z , and the Zener device will be in the “off” state. 



96 



DIODE APPLICATIONS 



To determine the minimum load resistance of Fig. 2.1 12 that will turn the Zener diode 
on, simply calculate the value of R L that will result in a load voltage V L = V z . That is, 



Solving for R L , we have 



y L = y z = 



R,y, 

R L + R 



Rr 



RVz 

Vi - V z 



( 2 . 20 ) 



Any load resistance value greater than the R L obtained from Eq. (2.20) will ensure that the 
Zener diode is in the “on” state and the diode can be replaced by its V 7 source equivalent. 

The condition defined by Eq. (2.20) establishes the minimum R L , but in turn specifies 
the maximum I L as 



h 



max 



Yk 

r l 




( 2 . 21 ) 



Once the diode is in the “on” state, the voltage across R remains fixed at 

V* = V; - Vz 



( 2 . 22 ) 



and I R remains fixed at 




( 2 . 23 ) 



The Zener current 



h ~ Ir ~ h 



( 2 . 24 ) 



resulting in a minimum 7 Z when I L is a maximum and a maximum I z when I L is a minimum 
value, since I R is constant. 

Since I z is limited to I ZM as provided on the data sheet, it does affect the range of R L and 
therefore I L . Substituting I ZM for I z establishes the minimum I L as 



Ir ~ /; 



ZM 



( 2 . 25 ) 



and the maximum load resistance as 



Rl 



max 




( 2 . 26 ) 



EXAMPLE 2.27 

a. For the network of Fig. 2.1 19, determine the range of R L and I L that will result in V RL 
being maintained at 10 V. 

b. Determine the maximum wattage rating of the diode. 




FIG. 2.119 

Voltage regulator for Example 2.27. 



Solution: 

a. To determine the value of R L that will turn the Zener diode on, apply Eq. (2.20): 

„ _ RV Z _ (lknxiov) _ 10 kn _ 

a t ZjU &£ 

^mrn V t ~ V Z 50 V ~ 10 V 40 
The voltage across the resistor R is then determined by Eq. (2.22): 

V R = Vi - V z = 5 0 V - 10V = 40V 



and Eq. (2.23) provides the magnitude of I R \ 



Ir = 



Vr 

R 



40 V 
lkO 



= 40 mA 



The minimum level of I L is then determined by Eq. (2.25): 

= j r ~ j zm = 40 mA - 32 mA = 8 mA 
with Eq. (2.26) determining the maximum value of R L : 

V z 10 V 



^^rnax 



8mA 



= 1.25 kH 



A plot of V L versus R L appears in Fig. 2.120a and for V L versus I L in Fig. 2.120b. 



Vl 



10 V - 




(a) 




FIG. 2.120 

V L versus R L and Ii^for the regulator of Fig. 2.119. 



ZENER DIODES 97 



b- ^max V Z IzM 

= (10 V)(32 mA) = 320 mW 



Fixed R l , Variable V, 



For fixed values of R L in Fig. 2.1 12, the voltage V', must be sufficiently large to turn the 
Zener diode on. The minimum turn-on voltage V| = V; . is determined by 



V L = V z = 



R,y, 

R l + R 



and 






(Rl + R)Vz 

Rl 



( 2 . 27 ) 



The maximum value of V; is limited by the maximum Zener current I ZM . Since I ZM = 
Ir ~ lu 



Ir — I Z m + It 

A max £AY1 ^ 



( 2 . 28 ) 



Since I L is fixed at V Z /R L and I ZM is the maximum value of / z , the maximum V 7 ,- is 
defined by 



Vi = V R 



V/ 



Vi = I R R + V z 

l max iV max ^ 



( 2 . 29 ) 



98 DIODE APPLICATIONS 

EXAMPLE 2.28 Determine the range of values of V t that will maintain the Zener diode of 
Fig. 2.121 in the “on” state. 




Solution: 

Eq. (2.27): 

Eq. (2.28): 
Eq. (2.29): 



Vi . = 



(R l + R)V Z (1200 n + 220 D)(20 V) 



1200 n 



Ir — 



20 V 



= 16.67 mA 



v,-.. = 



Rl 

= Yl = Vz = 

L R l R l 1.2 kO 

I ZM + II = 6 0 mA + 16.67 mA 
76.67 mA 
I R R + V z 

iV max ^ 



= (76.67 mA)(0.22 kO) + 20 V 
= 16.87 V + 20 V 

= 36.87 V 

A plot of V L versus V t is provided in Fig. 2.122. 



= 23.67 V 



Vl 



20 V 



0 



10 



— 



20 | | 40 

23.67 V 36.87 V 



Vi 



FIG. 2.122 

V L versus V t for the regulator of Fig. 2.121. 



The results of Example 2.28 reveal that for the network of Fig. 2.121 with a fixed R L , 
the output voltage will remain fixed at 20 V for a range of input voltage that extends from 



23.67 V to 36.87 V. 



2.12 VOLTAGE-MULTIPLIER CIRCUITS 



Voltage-multiplier circuits are employed to maintain a relatively low transformer peak 
voltage while stepping up the peak output voltage to two, three, four, or more times the 
peak rectified voltage. 



Voltage Doubler voltage-multiplier 99 

CIRCUITS 

The network of Fig. 2.123 is a half-wave voltage doubler. During the positive voltage half- 
cycle across the transformer, secondary diode D\ conducts (and diode D 2 is cut off), charg- 
ing capacitor C\ up to the peak rectified voltage (V m ). Diode D\ is ideally a short during 
this half-cycle, and the input voltage charges capacitor C\ to V m with the polarity shown in 
Fig. 2.124a. During the negative half-cycle of the secondary voltage, diode D\ is cut off 
and diode D 2 conducts charging capacitor C 2 . Since diode D 2 acts as a short during the 
negative half-cycle (and diode D\ is open), we can sum the voltages around the outside 
loop (see Fig. 2.124b): 

-Vm - V C] + Vc 2 = 0 
-V m -Vm+Vc 2 = o 

from which we obtain 

Vc 2 = 2V m 




FIG. 2.123 

Half-wave voltage doubler. 





FIG. 2.124 

Double operation, showing each half-cycle of operation: (a) positive half-cycle; 

(b) negative half -cycle. 

On the next positive half-cycle, diode D 2 is nonconducting and capacitor C 2 will discharge 
through the load. If no load is connected across capacitor C 2 , both capacitors stay 
charged — C\ to V m and C 2 to 2V m . If, as would be expected, there is a load connected to 
the output of the voltage doubler, the voltage across capacitor C 2 drops during the positive 
half-cycle (at the input) and the capacitor is recharged up to 2V m during the negative half- 
cycle. The output waveform across capacitor C 2 is that of a half-wave signal filtered by a 
capacitor filter. The peak inverse voltage across each diode is 2V m . 

Another doubler circuit is the full- wave doubler of Fig. 2.125. During the positive 
half-cycle of transformer secondary voltage (see Fig. 2.126a) diode D\ conducts, charging 
capacitor C\ to a peak voltage V m . Diode D 2 is nonconducting at this time. 

During the negative half-cycle (see Fig. 2.126b) diode D 2 conducts, charging capacitor 
C 2 , while diode D\ is nonconducting. If no load current is drawn from the circuit, the volt- 
age across capacitors C\ and C 2 is 2V m . If load current is drawn from the circuit, the voltage 
across capacitors C\ and C 2 is the same as that across a capacitor fed by a full- wave rectifier 
circuit. One difference is that the effective capacitance is that of C\ and C 2 in series, which 
is less than the capacitance of either C\ or C 2 alone. The lower capacitor value will provide 
poorer filtering action than the single-capacitor filter circuit. 



100 DIODE APPLICATIONS 



o 

+ 




FIG. 2.125 

Full-wave voltage doubler. 




FIG. 2.126 

Alternate half-cycles of operation for full-wave voltage doubler. 

The peak inverse voltage across each diode is 2 V m , as it is for the filter capacitor circuit. 
In summary, the half-wave or full-wave voltage-doubler circuits provide twice the peak 
voltage of the transformer secondary while requiring no center-tapped transformer and only 
2V m PIV rating for the diodes. 

Voltage Tripler and Quadrupler 

Figure 2.127 shows an extension of the half-wave voltage doubler, which develops three 
and four times the peak input voltage. It should be obvious from the pattern of the circuit 




FIG. 2.127 

Voltage tripler and quadrupler. 



connection how additional diodes and capacitors may be connected so that the output volt- PRACTICAL 101 

age may also be five, six, seven, and so on, times the basic peak voltage (V m ). APPLICATIONS 

In operation, capacitor C\ charges through diode D\ to a peak voltage V m during the posi- 
tive half-cycle of the transformer secondary voltage. Capacitor C 2 charges to twice the peak 
voltage, 2 V m , developed by the sum of the voltages across capacitor C\ and the transformer 
during the negative half-cycle of the transformer secondary voltage. 

During the positive half-cycle, diode D 3 conducts and the voltage across capacitor C 2 
charges capacitor C 3 to the same 2V m peak voltage. On the negative half-cycle, diodes D 2 
and Z ) 4 conduct with capacitor C 3 , charging C 4 to 2V m . 

The voltage across capacitor C 2 is 2V m , across C\ and C 3 it is 3 V m , and across C 2 and C 4 it 
is 4 V m . If additional sections of diode and capacitor are used, each capacitor will be charged 
to 2V m . Measuring from the top of the transformer winding (Fig. 2.127) will provide odd 
multiples of V m at the output, whereas measuring the output voltage from the bottom of the 
transformer will provide even multiples of the peak voltage V m . 

The transformer rating is only V m , maximum, and each diode in the circuit must be rated 
at 2V m PIV. If the load is small and the capacitors have little leakage, extremely high dc 
voltages may be developed by this type of circuit, using many sections to step up the dc 
voltage. 



2.1 1 PRACTICAL APPLICATIONS ^ 

The range of practical applications for diodes is so broad that it would be virtually impos- 
sible to consider all the options in one section. However, to develop some sense for the use 
of the device in everyday networks, a number of common areas of application are intro- 
duced below. In particular, note that the use of diodes extends well beyond the important 
switching characteristic that was introduced earlier in this chapter. 



Rectification 

Battery chargers are a common household piece of equipment used to charge everything 
from small flashlight batteries to heavy-duty, marine, lead- acid batteries. Since all are 
plugged into a 120 -V ac outlet such as found in the home, the basic construction of each is 
quite similar. In every charging system a transformer must be included to cut the ac volt- 
age to a level appropriate for the dc level to be established. A diode (also called rectifier ) 
arrangement must be included to convert the ac voltage, which varies with time, to a fixed 
dc level such as described in this chapter. Some dc chargers also include a regulator to 
provide an improved dc level (one that varies less with time or load). Since the car battery 
charger is one of the most common, it will be described in the next few paragraphs. 

The outside appearance and the internal construction of a Sears 6/2 AMP Manual Bat- 
tery Charger are provided in Fig. 2. 128. Note in Fig. 2. 128b that the transformer (as in most 
chargers) takes up most of the internal space. The additional air space and the holes in the 
casing are there to ensure an outlet for the heat that develops due to the resulting current 
levels. 

The schematic of Fig. 2. 129 includes all the basic components of the charger. Note first 
that the 120 V from the outlet are applied directly across the primary of the transformer. 
The charging rate of 6 A or 2 A is determined by the switch, which simply controls how 
many windings of the primary will be in the circuit for the chosen charging rate. If the 
battery is charging at the 2 - A level, the full primary will be in the circuit, and the ratio of 
the turns in the primary to the turns in the secondary will be a maximum. If it is charging 
at the 6 - A level, fewer turns of the primary are in the circuit, and the ratio drops. When 
you study transformers, you will find that the voltage at the primary and secondary is 
directly related to the turns ratio. If the ratio from primary to secondary drops, then the 
voltage drops also. The reverse effect occurs if the turns on the secondary exceed those 
on the primary. 

The general appearance of the waveforms appears in Fig. 2.129 for the 6 - A charging 
level. Note that so far, the ac voltage has the same wave shape across the primary and the 
secondary. The only difference is in the peak value of the waveforms. Now the diodes take 




FIG. 2.128 

Battery charger: (a) external appearance; (b) internal construction. 




FIG. 2.129 

Electrical schematic for the battery charger of Fig. 2.128. 



over and convert the ac waveform, which has zero average value (the waveform above 
equals the waveform below), to one that has an average value (all above the axis) as shown 
in the same figure. For the moment simply recognize that diodes are semiconductor elec- 
tronic devices that permit only conventional current to flow through them in the direction 
indicated by the arrow in the symbol. Even though the waveform resulting from the diode 
action has a pulsing appearance with a peak value of about 18 V, it will charge the 12-V 
battery whenever its voltage is greater than that of the battery, as shown by the shaded area. 



102 



Below the 12-V level the battery cannot discharge back into the charging network because PRACTICAL 103 

the diodes permit current flow in only one direction. APPLICATIONS 

In particular, note in Fig. 2.128b the large plate that carries the current from the rectifier 
(diode) configuration to the positive terminal of the battery. Its primary purpose is to pro- 
vide a heat sink (a place for the heat to be distributed to the surrounding air) for the diode 
configuration. Otherwise the diodes would eventually melt down and self-destruct due to 
the resulting current levels. Each component of Fig. 2.129 has been carefully labeled in 
Fig. 2.128b for reference. 

When current is first applied to a battery at the 6-A charge rate, the current demand, as 
indicated by the meter on the face of the instrument, may rise to 7 A or almost 8 A. However, 
the level of current will decrease as the battery charges until it drops to a level of 2 A or 3 A. 

For units such as this that do not have an automatic shutoff, it is important to disconnect 
the charger when the current drops to the fully charged level; otherwise, the battery will 
become overcharged and may be damaged. A battery that is at its 50% level can take as long 
as 10 hours to charge, so one should not expect it to be a 10-minute operation. In addition, if 
a battery is in very bad shape, with a lower than normal voltage, the initial charging current 
may be too high for the design. To protect against such situations, the circuit breaker will 
open and stop the charging process. Because of the high current levels, it is important that 
the directions provided with the charger be carefully read and applied. 

In an effort to compare the theoretical world with the real world, a load (in the form of 
a headlight) was applied to the charger to permit a viewing of the actual output waveform. 

It is important to note and remember that a diode with zero current through it will not 
display its rectifying capabilities. In other words, the output from the charger of Fig. 2. 129 
will not be a rectified signal unless a load is applied to the system to draw current through 
the diode. Recall from the diode characteristics that when I D = 0 A, V D = 0 V. 

By applying the headlamp as a load, however, sufficient current is drawn through the 
diode for it to behave like a switch and convert the ac waveform to a pulsating one as 
shown in Fig. 2.130 for the 6-A setting. First note that the waveform is slightly distorted 
by the nonlinear characteristics of the transformer and the nonlinear characteristics of the 
diode at low currents. The waveform, however, is certainly close to what is expected when 
we compare it to the theoretical patterns of Fig. 2.129. The peak value is determined from 
the vertical sensitivity as 

Vpeak — (3.3 divisions)(5 V/division) = 16.5 V vs. the 18 V of Fig. 1.129 




FIG. 2.130 

Pulsating response of the charger of Fig. 2.129 
to the application of a headlamp as a load. 



with a dc level of 

V dc = 0.63 6 Vp eak = 0.636(16.5 V) = 10.49 V 

A dc meter connected across the load registered 10.41 V, which is very close to the theo- 
retical average (dc) level of 10.49 V. 

One may wonder how a charger having a dc level of 10.49 V can charge a 12-V battery 
to a typical level of 14 V. It is simply a matter of realizing that (as shown in Fig. 2.130) for 
a good deal of each pulse, the voltage across the battery will be greater than 12 V and the 
battery will be charging — a process referred to as trickle charging. In other words, charg- 
ing does not occur during the entire cycle, but only when the charging voltage is more than 
the voltage of the battery. 



104 diode applications Protective Configurations 

Diodes are used in a variety of ways to protect elements and systems from excessive volt- 
ages or currents, polarity reversals, arcing, and shorting, to name a few. In Fig. 2.131a, the 
switch on a simple RL circuit has been closed, and the current will rise to a level deter- 
mined by the applied voltage and series resistor R as shown on the plot. Problems arise 
when the switch is quickly opened as in Fig. 2.131b to essentially tell the circuit that the 
current must drop to zero almost instantaneously. You will remember from your basic 
circuits courses, however, that the inductor will not permit an instantaneous change in cur- 
rent through the coil. A conflict results, which will establish arcing across the contacts of 
the switch as the coil tries to find a path for discharge. Recall also that the voltage across 
an inductor is directly related to the rate of change in current through the coil (v L = L di L /dt). 
When the switch is opened, it is trying to dictate that the current change almost instanta- 
neously, causing a very high voltage to develop across the coil that will then appear across 
the contacts to establish this arcing current. Levels in the thousands of volts will develop 
across the contacts, which will soon, if not immediately, damage the contacts and thereby 
the switch. The effect is referred to as an “inductive kick.” Note also that the polarity of the 
voltage across the coil during the “build-up” phase is opposite to that during the “release” 
phase. This is due to the fact that the current must maintain the same direction before and 
after the switch is opened. During the “build-up” phase, the coil appears as a load, whereas 
during the release phase, it has the characteristics of a source. In general, therefore, always 
keep in mind that 

Trying to change the current through an inductive element too quickly may result in an 
inductive kick that could damage surrounding elements or the system itself \ 




FIG. 2.131 

(a) Transient phase of a simple RL circuit; (b) arcing that results across a switch when opened in series with an RL circuit. 



In Fig. 2.132a the simple network above may be controlling the action of a relay. 
When the switch is closed, the coil will be energized, and steady-state current levels will 
be established. However, when the switch is opened to deenergize the network, we have 
the problem introduced above because the electromagnet controlling the relay action will 
appear as a coil to the energizing network. One of the cheapest but most effective ways to 
protect the switching system is to place a capacitor (called a “snubber”) across the terminals 
of the coil as shown in Fig. 2.132b. When the switch is opened, the capacitor will initially 
appear as a short to the coil and will provide a current path that will bypass the dc supply 
and switch. The capacitor has the characteristics of a short (very low resistance) because of 
the high-frequency characteristics of the surge voltage, as shown in Fig. 2.131b. Recall that 
the reactance of a capacitor is determined by X c = 1 / 2irfC , so the higher the frequency, the 
less is the resistance. Normally, because of the high surge voltages and relatively low cost, ce- 
ramic capacitors of about 0.01 /iF are used. You don’t want to use large capacitors because 
the voltage across the capacitor will build up too slowly and will essentially slow down the 



V 



R 

vw 



R 

A/W 




(a) 




r , < 100 a 



C s Jo.OljiFj 



"Snubber" 




Relay 



(b) 




C = 0.01 |iF 
(c) 



FIG. 2.132 

(a) Inductive characteristics of a relay; (b) snubber protection for the configuration of part (a); 
(c) capacitive protection for a switch. 



performance of the system. The resistor of 100 II in series with the capacitor is introduced 
solely to limit the surge current that will result when a change in state is called for. Often, 
the resistor does not appear because of the internal resistance of the coil as established by 
many turns of fine wire. On occasion, you may find the capacitor across the switch as shown 
in Fig. 2.132c. In this case, the shorting characteristics of the capacitor at high frequencies 
will bypass the contacts with the switch and extend its life. Recall that the voltage across a 
capacitor cannot change instantaneously. In general, therefore, 

Capacitors in parallel with inductive elements or across switches are often there to act 
as protective elements , not as typical network capacitive elements. 

Finally, the diode is often used as a protective device for situations such as above. In 
Fig. 2.133, a diode has been placed in parallel with the inductive element of the relay con- 
figuration. When the switch is opened or the voltage source quickly disengaged, the polarity 
of the voltage across the coil is such as to turn the diode on and conduct in the direction 
indicated. The inductor now has a conduction path through the diode rather than through 
the supply and switch, thereby saving both. Since the current established through the coil 
must now switch directly to the diode, the diode must be able to carry the same level of 
current that was passing through the coil before the switch was opened. The rate at which 
the current collapses will be controlled by the resistance of the coil and the diode. It can 
be reduced by placing an additional resistor in series with the diode. The advantage of the 
diode configuration over that of the snubber is that the diode reaction and behavior are not 
frequency dependent. However, the protection offered by the diode will not work if the ap- 
plied voltage is an alternating one such as ac or a square wave since the diode will conduct 
for one of the applied polarities. For such alternating systems, the “snubber” arrangement 
would be the best option. 

In the next chapter we will find that the base-to-emitter junction of a transistor is 
forward-biased. That is, the voltage V BE of Fig. 2.134a will be about 0.7 V positive. To 
prevent a situation where the emitter terminal would be made more positive than the base 
terminal by a voltage that could damage the transistor, the diode shown in Fig. 2.134a 
is added. The diode will prevent the reverse-bias voltage V EB from exceeding 0.7 V. On 




FIG. 2.133 

Diode protection for an RL circuit. 




FIG. 2.134 

(a) Diode protection to limit the emitter-to-base voltage of a 
transistor; (b) diode protection to prevent a reversal in 
collector current. 



105 



106 DIODE APPLICATIONS occasion, you may also find a diode in series with the collector terminal of a transistor as 

shown in Fig. 2.134b. Normal transistor action requires that the collector be more positive 
than the base or emitter terminal to establish a collector current in the direction shown. 
However, if a situation arises where the emitter or base terminal is at a higher potential 
than the collector terminal, the diode will prevent conduction in the opposite direction. In 
general, therefore, 

Diodes are often used to prevent the voltage between two points from exceeding 0.7 V 
or to prevent conduction in a particular direction . 

As shown in Fig. 2.135, diodes are often used at the input terminals of systems such 
as op-amps to limit the swing of the applied voltage. For the 400-mV level the signal 
will pass undisturbed to the input terminals of the op-amp. However, if the voltage 
jumps to a level of 1 V, the top and bottom peaks will be clipped off before appearing at 
the input terminals of the op-amp. Any clipped-off voltage will appear across the series 
resistor R\. 




The controlling diodes of Fig. 2.135 may also be drawn as shown in Fig. 2.136 to control 
the signal appearing at the input terminals of the op-amp. In this example, the diodes are act- 
ing more like shaping elements than as limiters as in Fig. 2.135. However, the point is that 

The placement of elements may change, but their function may still be the same. Do 
not expect every network to appear exactly as you studied it for the first time. 

In general, therefore, don’t always assume that diodes are used simply as switches. There 
is a wide variety of uses for diodes as protective and limiting devices. 



PRACTICAL 107 
APPLICATIONS 






(b) 

FIG. 2.136 

(a) Alternate appearances for the network of Fig. 2.135; (b) establishing random levels of control 

with separate dc supplies. 



Polarity Insurance 

There are numerous systems that are very sensitive to the polarity of the applied voltage. 
For instance, in Fig. 2.137a, assume for the moment that there is a very expensive piece of 
equipment that would be damaged by an incorrectly applied bias. In Fig. 2. 137b the correct 
applied bias is shown on the left. As a result, the diode is reverse-biased, but the system 
works just fine — the diode has no effect. However, if the wrong polarity is applied as 




(a) 




(b) 




FIG. 2.137 

(a) Polarity protection for an expensive , sensitive piece of equipment; (b) correctly applied polarity; 

(c) application of the wrong polarity. 






108 DIODE APPLICATIONS 




FIG. 2.138 

Protection for a sensitive meter 
movement 



shown in Fig. 2.137c, the diode will conduct and ensure that no more than 0.7 V will 
appear across the terminals of the system, protecting it from excessive voltages of the 
wrong polarity. For either polarity, the difference between the applied voltage and the load 
or diode voltage will appear across the series source or network resistance. 

In Fig. 2.138 a sensitive measuring movement cannot withstand voltages greater than 
1 V of the wrong polarity. With this simple design the sensitive movement is protected from 
voltages of the wrong polarity of more than 0.7 V. 

Controlled Battery-Powered Backup 

In numerous situations a system should have a backup power source to ensure that the 
system will still be operational in case of a loss of power. This is especially true of security 
systems and lighting systems that must turn on during a power failure. It is also important 
when a system such as a computer or a radio is disconnected from its ac-to-dc power con- 
version source to a portable mode for traveling. In Fig. 2.139 the 12-V car radio operating 
off the 12-V dc power source has a 9-V battery backup system in a small compartment in 
the back of the radio ready to take over the role of saving the clock mode and the channels 
stored in memory when the radio is removed from the car. With the full 12 V available 
from the car, D\ is conducting, and the voltage at the radio is about 11.3 V. D 2 is reverse- 
biased (an open circuit), and the reserve 9-V battery inside the radio is disengaged. 
However, when the radio is removed from the car, D\ will no longer be conducting because 
the 12-V source is no longer available to forward-bias the diode. However, D 2 will be 
forward-biased by the 9-V battery, and the radio will continue to receive about 8.3 V to 
maintain the memory that has been set for components such as the clock and the channel 
selections. 




Backup system designed to prevent the loss of memory in a 
car radio when the radio is removed from the car. 



Polarity Detector 

Through the use of LEDs of different colors, the simple network of Fig. 2.140 can be used 
to check the polarity at any point in a dc network. When the polarity is as indicated for the 
applied 6 V, the top terminal is positive, D\ will conduct along with LED1, and a green 
light will result. Both D 2 and LED2 will be back-biased for the above polarity. However, 
if the polarity at the input is reversed, D 2 and LED2 will conduct, and a red light will 
appear, defining the top lead as the lead at the negative potential. It would appear that the 




FIG. 2.140 

Polarity detector using diodes and LEDs. 




network would work without diodes D\ and D 2 . However, in general, LEDs do not like to PRACTICAL 109 

be reverse-biased because of sensitivity built in during the doping process. Diodes D\ and APPLICATIONS 

D 2 offer a series open-circuit condition that provides some protection to the LEDs. In the 
forward-bias state, the additional diodes Di and D 2 reduce the voltage across the LEDs to 
more common operating levels. 

Displays 

Some of the primary concerns of using electric light bulbs in exit signs are their limited 
lifetime (requiring frequent replacement); their sensitivity to heat, fire, and so on; their 
durability factor when catastrophic accidents occur; and their high voltage and power 
requirements. For this reason LEDs are often used to provide the longer life span, higher 
durability levels, and lower demand voltage and power levels (especially when the reserve 
dc battery system has to take over). 

In Fig. 2.141 a control network determines when the EXIT light should be on. When it 
is on, all the LEDs in series will be on, and the EXIT sign will be fully lit. Obviously, if 
one of the LEDs should bum out and open up, the entire section will turn off. However, 
this situation can be improved by simply placing parallel LEDs between every two points. 

Lose one, and you will still have the other parallel path. Parallel diodes will, of course, reduce 
the current through each LED, but two at a lower level of current can have a luminescence 
similar to one at twice the current. Even though the applied voltage is ac, which means that 
the diodes will turn on and off as the 60-Hz voltage swings positive and negative, the per- 
sistence of the LEDs will provide a steady light for the sign. 




Limit to low mA 




FIG. 2.141 

EXIT sign using LEDs. 



Setting Voltage Reference Levels 

Diodes and Zeners can be used to set reference levels as shown in Fig. 2.142. The net- 
work, through the use of two diodes and one Zener diode, is providing three different 
voltage levels. 

Establishing a Voltage Level Insensitive to the Load Current 

As an example that clearly demonstrates the difference between a resistor and a diode in a 
voltage-divider network, consider the situation of Fig. 2.143a, where a load requires about 
6 V to operate properly but a 9-V battery is all that is available. For the moment let us 
assume that operating conditions are such that the load has an internal resistance of 1 k!2. 
Using the voltage-divider rule, we can easily determine that the series resistor should be 
470 12 (commercially available value) as shown in Fig. 2.143b. The result is a voltage 
across the load of 6.1 V, an acceptable situation for most 6-V loads. However, if the operat- 
ing conditions of the load change and the load now has an internal resistance of only 600 12, 
the load voltage will drop to about 4.9 V, and the system will not operate correctly. This 
sensitivity to the load resistance can be eliminated by connecting four diodes in series with 
the load as shown in Fig. 2.143c. When all four diodes conduct, the load voltage will be 



+ + 



R 

AAA r 

4.6 V 



i 0.7 V 



-o 7.4 V 



12V 



+ 

3C 0.7 V 



<5 6.7 V 



6 V 






FIG. 2.142 



Providing different reference levels 
using diodes. 



110 DIODE APPLICATIONS 



— 9V 

I' 




(a) 




. > i k o V ~ lk °( 9V > - 6 1 V 

l< 1U1 V R - + V 



+ 0.7 V- +0.7 V- +0.7 V- +0.7 V- 




6.2 V (with Rl = i hO or 600 12) 



(c) 

FIG. 2.143 

(a) How to drive a 6-V load with a 9 -V supply (b) using a fixed resistor value, 
(c) Using a series combination of diodes. 



about 6.2 V, irrespective of the load impedance (within device limits, of course) — the sen- 
sitivity to the changing load characteristics has been removed. 

AC Regulator and Square-Wave Generator 

Two back-to-back Zeners can also be used as an ac regulator as shown in Fig. 2.144a. For 
the sinusoidal signal v t the circuit will appear as shown in Fig. 2.144b at the instant 
Vi = 10 V. The region of operation for each diode is indicated in the adjoining figure. 
Note that Z\ is in a low-impedance region, whereas the impedance of Z 2 is quite large, cor- 
responding to the open-circuit representation. The result is that v 0 = v* when v t = 10 V. 
The input and the output will continue to duplicate each other until v t reaches 20 V. Then 
Z 2 will “turn on” (as a Zener diode), whereas Z\ will be in a region of conduction with a 
resistance level sufficiently small compared to the series 5-kI2 resistor to be considered a 







FIG. 2.144 

Sinusoidal ac regulation: (a) 40-V peak-to-peak sinusoidal ac regulator ; 
(b) circuit operation at Vf = 10 V. 




SUMMARY 111 



short circuit. The resulting output for the full range of v t is provided in Fig. 2.144a. Note 
that the waveform is not purely sinusoidal, but its root mean square (rms) value is lower 
than that associated with a full 22-V peak signal. The network is effectively limiting the 
rms value of the available voltage. The network of Fig. 2.144b can be extended to that of a 
simple square-wave generator (due to the clipping action) if the signal is increased to 
perhaps a 50-V peak with 10-V Zeners as shown in Fig. 2.145 with the resulting output 
waveform. 





FIG. 2.145 

Simple square-wave generator. 



2.14 SUMMARY ^ 

Important Conclusions and Concepts 

1 . The characteristics of a diode are unaltered by the network in which it is employed. 
The network simply determines the point of operation of the device. 

2. The operating point of a network is determined by the intersection of the network 
equation and an equation defining the characteristics of the device. 

3. For most applications, the characteristics of a diode can be defined simply by the 
threshold voltage in the forward-bias region and an open circuit for applied volt- 
ages less than the threshold value. 

4. To determine the state of a diode, simply think of it initially as a resistor, and find 
the polarity of the voltage across it and the direction of conventional current through 
it. If the voltage across it has a forward-bias polarity and the current has a direction 
that matches the arrow in the symbol, the diode is conducting. 

5. To determine the state of diodes used in a logic gate, first make an educated guess 
about the state of the diodes, and then test your assumptions. If your estimate is 
incorrect, refine your guess and try again until the analysis verifies the conclusions. 

6. Rectification is a process whereby an applied waveform of zero average value is 
changed to one that has a dc level. For applied signals of more than a few volts, the 
ideal diode approximations can normally be applied. 

7. It is very important that the PIV rating of a diode be checked when choosing a diode 
for a particular application. Simply determine the maximum voltage across the diode 
under reverse-bias conditions, and compare it to the nameplate rating. For the typical 
half-wave and full- wave bridge rectifiers, it is the peak value of the applied signal. For 
the CT transformer full-wave rectifier, it is twice the peak value (which can get quite 
high). 

8. Clippers are networks that “clip” away part of the applied signal either to create a 
specific type of signal or to limit the voltage that can be applied to a network. 

9. Clampers are networks that “clamp” the input signal to a different dc level. In any 
event, the peak-to-peak swing of the applied signal will remain the same. 

10. Zener diodes are diodes that make effective use of the Zener breakdown potential of 
an ordinary p-n junction characteristic to provide a device of wide importance and 
application. For Zener conduction, the direction of conventional flow is opposite to 
the arrow in the symbol. The polarity under conduction is also opposite to that of 
the conventional diode. 



112 DIODE APPLICATIONS 



11. To determine the state of a Zener diode in a dc network, simply remove the Zener 
from the network, and determine the open-circuit voltage between the two points 
where the Zener diode was originally connected. If it is more than the Zener poten- 
tial and has the correct polarity, the Zener diode is in the “on” state. 

12. A half-wave or full- wave voltage doubler employs two capacitors; a tripler, three 
capacitors; and a quadrupler, four capacitors. In fact, for each, the number of diodes 
equals the number of capacitors. 



Equations 



Approximate: 



Silicon: 


V K = 


Germanium: 


V K = 


Gallium arsenide: 


V K = 



Ideal: 



0.7 V; I D is determined by network. 

0.3 V; I D is determined by network. 
1.2 V; I D is determined by network. 



V K = 0 V; 

For conduction: 



I D is determined by network. 



V D > V* 

Half-wave rectifier: 

V dc = 0.318V m 

Full- wave rectifier: 

Vd c = 0.636V m 



2.15 COMPUTER ANALYSIS ^ 

Cadence OrCAD 

Series Diode Configuration In the previous chapter the OrCAD 16.3 folder was estab- 
lished as the location for our projects. This section will define the name of our project, set 
up the software for the analysis to be performed, describe how to build a simple circuit, 
and, finally, perform the analysis. The coverage will be quite extensive since this will be 
the first true exposure to the mechanics associated with using the software package. In the 
chapters to follow you will find the analysis can be performed quite rapidly to obtain 
results that confirm the long-hand solutions. 

Our first project can now be initiated by double-clicking on the OrCAD Capture CIS 
Demo icon on the screen, or you can use the sequence Start-All Programs-Cadence- 
OrCAD 16.3 Demo. The resulting screen has only a few active keys on the top toolbar. 
The first at the top left is the Create document key (or you can use the sequence File-New- 
Project). Selecting the key will result in a New Project dialog box, in which the Name of 
the project must be entered. For our purposes we will choose OrCAD 2-1 as shown in the 
heading of Fig. 2.146, and select Analog or Mixed A/D (to be used for all the analyses of 
this text). Note at the bottom of the dialog box that the Location appears as C:\OrCAD 
16.3 as set earlier. Click OK, and another dialog box will appear titled Create PSpice 
Project. Select Create a blank project (again, for all the analyses to be performed in this 
text). Click OK, and additional keys will be turned on along with additional toolbars. A 
Project Manager Window will appear with OrCAD 2-1 as its heading. The new project 
listing will appear with an icon and an associated + sign in a small square. Clicking on 
the + sign will take the listing a step further to SCHEMATIC1. Click + again (to the left 
of SCHEMATIC 1), and PAGE1 will appear; clicking on a — sign will reverse the pro- 
cess. Double-clicking on PAGE1 will create a working window titled SCHEMATIC1: 
PAGE1, revealing that a project can have more than one schematic file and more than one 
associated page. The width and the height of the window can be adjusted by grabbing an 
edge to obtain a double-headed arrow and dragging the border to the desired location. Either 
window on the screen can be moved by clicking on the top heading to make it dark blue 
and then dragging it to any location. 



COMPUTER ANALYSIS 



113 




FIG. 2.146 

Cadence Or CAD analysis of a series diode configuration. 



Now we are ready to build the simple circuit of Fig. 2. 146. Select the Place part key (the 
top key on the far right vertical toolbar that looks like an integrated circuit with a positive 
sign in the bottom right corner) to obtain the Place Part dialog box. Since this is the first 
circuit to be constructed, we must ensure that the parts appear in the list of active libraries. 
Go to Libraries and select the Add Library key (looks like a dashed rectangular box with 
a yellow star in the top left corner). The result is a Browse File in which analog.olb can 
be selected, followed by Open to place it in the active list of Libraries. Repeat the process 
to add the eval.olb and source.olb libraries. All three libraries will be required to build the 
networks appearing in this text. However, it is important to realize that: 

Once the library files have been selected ' they will appear in the active listing for each 
new project without having to add them each time — a step, such as the Folder step 
above , that does not have to be repeated with each similar project. 

Click the small x in the top right corner of the dialog box to remove the Place Part dialog 
box. We can now place components on the screen. For the dc voltage source, first select the 
Place Part key and then select SOURCE in the library listing. Under Part List, a list of 
available sources will appear; select VDC for this project. Once VDC has been selected, its 
symbol, label, and value will appear on the picture window at the bottom left of the dialog 
box. Click the Place Part key on the top of the dialog box, and the VDC source will follow 
the cursor across the screen. Move it to a convenient location, left-click the mouse, and it 
will be set in place as shown in Fig. 2.146. 

Since a second source is present in Fig. 2.146, move the cursor to the general area of the 
second source and click it in place. Since this is the last source to appear in the network, 
execute a right click of the mouse and select End Mode. Choosing this option will end the 
procedure, leaving the last source in a red dashed box. The fact that it is red indicates that 
it is still in the active mode and can be operated on. One more click of the mouse, and the 
second source will be in place and the red active status removed. The second source can 
be rotated 180° to match Fig. 2.146 by first clicking the source to make it red (active) to 
obtain a long list of options and select Rotate. Since each rotation only turns it 90° coun- 
terclockwise, two rotations will be required. The rotations can also be accomplished using 
the sequence Ctrl-R. 

One of the most important steps in the procedure is to ensure that a 0-V ground poten- 
tial is defined for the network so that voltages at any point in the network have a reference 
point. The result is a requirement that every network must have a ground defined. For our 
purposes, the O/SOURCE option will be our choice when the GND key is selected. It is 
obtained by selecting the ground symbol in the middle of the far right toolbar to obtain the 
Place Ground dialog box. Scroll down until O/SOURCE is selected and click OK. The 
result is a ground that can be placed anywhere on the screen. As with the voltage source, 



114 DIODE APPLICATIONS 



multiple grounds can be added by simply going from one point to another. The process is 
ended with a right click and the End Mode option. 

The next step will be to place the resistors of the network of Fig. 2.146. This is accom- 
plished by selecting the Place Part key again and then selecting the ANALOG library. 
Scrolling the options, note that R will appear and should be selected. Click the Place Part 
key, and the resistor will appear next to the cursor on the screen. Move it to the desired 
location and click it in place. The second resistor can be placed by simply moving to the 
general area of its location in Fig. 2.146 and clicking it in place. Since there are only two 
resistors, the process can be ended by making a right click of the mouse and selecting End 
Mode. The second resistor will have to be rotated to the vertical position using the same 
procedure described for the second voltage source. 

The last element to be placed is the diode. Selecting the Place Part keypad will again 
result in the Place Part dialog box, in which the EVAL library is chosen from the Libraries 
listing. Then type D under Part heading and select D14148 under Part List followed by 
the Place Part command to place on the screen in the same manner described for the source 
and resistors. 

Now that all the components are on the screen you may want to move them to positions 
corresponding directly with Fig. 2.146. This is accomplished by simply clicking on the 
element and holding the left-click down as you move the element. 

All the required elements are on the screen, but they need to be connected. This is ac- 
complished by selecting the Place wire key, which looks like a step, near the top of the 
toolbar to the left of the toolbar with the Place Part key. The result is a crosshair with a 
center that should be placed at the point to be connected. Place the crosshair at the top of the 
voltage source, and left-click it once to connect it to that point. Then draw a line to the end 
of the next element, and click the mouse again when the crosshair is at the correct point. A 
red line will result with a square at each end to confirm that the connection has been made. 
Then move the crosshair to the other elements, and build the circuit. Once everything is 
connected, a right click will provide the End Mode option. Don’t forget to connect the 
source to ground as shown in Fig. 2.146. 

Now we have all the elements in place, but their labels and values are wrong. To change 
any parameter, simply double-click on the parameter (the label or the value) to obtain the 
Display Properties dialog box. Type in the correct label or value, click OK, and the quan- 
tity is changed on the screen. The labels and values can be moved by simply clicking on 
the center of the parameter until it is closely surrounded by the four small squares and then 
dragging it to the new location. Another left click, and it is deposited in its new location. 

Finally, we can initiate the analysis process, called Simulation, by selecting the New 
Simulation Profile key near the top left of the display — it resembles a data page with a 
star in the top right corner. A New Simulation dialog box will result that first asks for 
the Name of the simulation. OrCAD 2-1 is entered, and none is left in the Inherit From 
request. Then select Create, and a Simulation Setting dialog box will appear in which 
Analysis-Analysis Type-Bias Point is sequentially selected. Click OK, and select the Run 
key (which looks like an isolated arrowhead in a green background) or choose PSpice-Run 
from the menu bar. An Output Window will result that appears to be somewhat inactive. 
It will not be used in the current analysis, so close (X) the window, and the circuit of Fig. 
2.146 will appear with the voltage and current levels of the network. The voltage, current, 
or power levels can be removed (or replaced) from the display by simply selecting the 
V, I, or W in the third toolbar from the top. Individual values can be removed by simply 
selecting the value and pressing the Delete key. Resulting values can be moved by simply 
left-clicking the value and dragging it to the desired location. 

The results of Fig. 2.146 show that the current through the series configuration is 
2.081 mA through each element, compared to the 2.072 mA of Example 2.9. The voltage 
across the diode is 218.8 mV - (-421.6 mV) = 0.64 V, compared to the 0.7 V applied 
in the long-hand solution of Example 2.9. The voltage across is 10 V — 218.8 mV = 
9.78 V, compared to 9.74 V in the long-hand solution. The voltage across the resistor R 2 
is 5 V - 421.6 mV = 4.58 V, compared to 4.56 V in Example 2.9. 

To understand the differences between the two solutions, one must be aware that the diode 
has internal characteristics that affect its behavior such as the reverse saturation current and 
its resistance levels at different current levels. Those characteristics can be viewed through 
the sequence Edit-PSpice Model resulting in the PSpice Model Editor Demo dialog box. 



You will find that the default value of the reverse saturation current is 2.682 nA — a quantity COMPUTER ANALYSIS 115 

that can have an important effect on the characteristics of the device. If we choose I s = 

3.5E-15A (a value determined by trial and error) and delete the other parameters for the 
device, a new simulation of the network will result in the response of Fig. 2.147. Now the 
current through the circuit is 2.072 mA, which is an exact match with the result of Example 
2.9. The voltage across the diode is 260.2 mV + 440.9 mV = 0.701 V, or essentially 
0.7 V, and the voltage across each resistor is exactly as obtained in the long-hand solution. 

In other words, by choosing this value of reverse saturation current, we created a diode with 
characteristics that permitted the approximation that V D = 0.7 V when in the “on” state. 



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The circuit of Fig. 2.146 reexamined with I s set at 3.5E-15A. 



The results can also be viewed in tabulated form by selecting PSpice at the head of the 
screen followed by View Output File. The result is the listing of Fig. 2.148 (modified to 
conserve space), which includes the CIRCUIT DESCRIPTION with all the components 
of the network, the Diode MODEL PARAMETERS with the chosen Is value, and the 
INITIAL TRANSIENT SOLUTION with the dc voltage levels, current levels, and total 
power dissipation. 

The analysis is now complete for the diode circuit of interest. Granted, there was a wealth 
of information provided to establish and investigate this rather simple network. However, 
the vast majority of this material will not be repeated in the PSpice examples to follow, 
which will have a dramatic effect on the length of the descriptions. For practice purposes, 
it is suggested that other examples in this chapter be checked using PSpice and that the 
exercises at the end of the chapter be investigated to develop confidence in applying the 
software package. 

Diode Characteristics The characteristics of the D1N4148 diode used in the above analysis 
will now be obtained using a few maneuvers somewhat more sophisticated than those 
employed in the first example. The process begins by first building the network of Fig. 
2. 149 using the procedures just described. Note in particular that the source is labeled E and 
set at 0V (its initial value). Next the New Simulation Profile icon is selected from the tool- 
bar to obtain the New Simulation dialog box. For the Name, Fig. 2-150 is entered since it 
is the location of the graph to be obtained. Create is then selected and the Simulation Set- 
tings dialog box will appear. Under Analysis Type, DC Sweep is chosen because we want 
to sweep through a range of values for the source voltage. When DC Sweep is selected a list 
of options will simultaneously appear in the right-hand region of the dialog box, requiring 
that some choices be made. Since we plan to sweep through a range of voltages, the Sweep 
variable is a Voltage source. Its name must be entered as E as appearing in Fig. 2.149. The 
sweep will be Linear (equal space between data points) with a Start value of 0 V, End 
Value of 10 V, and an Increment of 0.01 V. After making all the entries, click OK and the 



116 DIODE APPLICATIONS 



* * * * CIRCUIT DESCRIPTION 



* Analysis directives: 

.TRAN 0 1000ns 0 
.PROBE V(alias(*)) I(alias(*)) 

W(alias(*)) D(alias(*)) NOISE(alias(*)) 

.INC ".ASCHEMATICl.net” 

**** INCLUDING SCHEMATICl.net **** 

* source ORCAD2-2 
V_E1 N00103 0 lOVdc 
V_E2 0 N00099 5Vdc 

R_R1 N00103 N00204 4.7kTC=0,0 
R_R2 N00099 N00185 2.2kTC=0,0 
D_D1 N00204 N00185 D1N4148 

**** Diode MODEL PARAMETERS 

D1N4148 
IS 2.000000E-15 

**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C 

NODE VOLTAGE 
(N00099) -5.0000 
(N00103) 10.0000 
(N00185) -.4455 
(N00204) .2700 



VOLTAGE SOURCE CURRENTS 

NAME CURRENT 
V_E1 -2.070E-03 
V_E2 -2.070E-03 

TOTAL POWER DISSIPATION 3.11E-02 WATTS 



FIG. 2.148 

Output file for P Spice Windows analysis of the circuit of Fig. 2.147. 



RUN PSpice option can be selected. The analysis will be performed with the source voltage 
changing from 0 V to 10 V in 1000 steps (as resulting from the division of 10 V/0.01 V). 
The result, however, is simply a graph with a horizontal scale from 0 V to 10 V. 

Since the plot we want is of I D versus V D , we must change the horizontal (x-axis) to V D . 
This is accomplished by selecting Plot and then Axis Settings. An Axis Settings dialog 
box will appear, in which choices have to be made. If Axis Variables is selected, an X-Axis 



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FIG. 2.149 

Network for obtaining the characteristics of the D1N4148 diode. 




Variable dialog box will appear with a list of variables that can be chosen for the v-axis. COMPUTER ANALYSIS 117 

V1(D1) will be selected since it represents the voltage across the diode. If we then select 

OK, the Axis Settings dialog box will return, where User Defined is selected under the 

Data Range heading. User Defined is chosen because it will allow us to limit the graph 

to a range of 0 V to 1 V since the “on” voltage of the diode should be around 0.7 V. After 

entering the 0-1 V range, selecting OK will result in a graph with V1(D1) as the v variable 

with a range of 0 V to 1 V. The horizontal axis now seems to be set for the desired plot. 

We must now turn our attention to the vertical axis, which should be the diode current. 

Choosing Trace followed by Add Trace will result in an Add Trace dialog box in which 
1(01) will appear as one of the possibilities. Selecting I(D1) will also cause it to appear as 
the Trace Expression at the bottom of the dialog box. Selecting OK will then result in the 
diode characteristics of Fig. 2.150, clearly showing a steep rise around 0.7 V. 



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FIG. 2.150 

Characteristics of the D1N4148 diode. 



If we turn back to the PSpice Model Editor for the diode and change I s to 3.5E-15A as 
in the previous example, the curve will shift to the right. Similar procedures will be used to 
obtain the characteristic curves for a variety of elements to be introduced in later chapters. 

Multisim 

Fortunately, there are a number of similarities between Cadence OrCAD and Multisim. 
Then again, there are a number of differences also, but the saving point is that once you 
become proficient in the use of one software package, the other will be much easier to learn. 
For those users familiar with the earlier versions of Multisim, you will find that the new 
version has a minimum of changes, permitting an easy transition to the new procedures. 

Once the Multisim icon is chosen, a screen will appear with a vast array of toolbars. The 
content of each and the name of each can be found through the sequence View- toolbars. 
The result is a long vertical list of available toolbars. The content and location of each can 
be found by simply selecting or deleting a toolbar and noting the effect on the full screen. 
For our purposes the Standard, View, Main, Components, Simulation Switch, Simula- 
tion and Instruments will be used. 

When using Multisim you have a choice between using “virtual” or “real” components. 
Virtual components are those that can be given any value when you build the network. The 
term real comes from the fact that the resulting list is a list of standard component values 
that can be purchased from a supplier. Finding a component is initiated by first selecting 
the second keypad (from the left) on the component toolbar that looks like a resistor. As 
you approach the key, the label Place Basic will appear. Once it is chosen, the Select a 



118 DIODE APPLICATIONS Component dialog box will appear that contains a subset titled Family. Third down on 

that list is a RATEDJVIRTUAL option with a resistor symbol. When this is selected a list 
of components including RESISTOR_RATED, CAPACITOR_RATED, INDUCTOR. 
RATED, and a variety of others will appear. If RESISTOR-RATED is selected, a resistor 
symbol will appear under the Symbol heading. Note that the resistor docs not have a specific 
value. If we now select OK and place it on the screen in much the same way we did for 
the OrCAD introduction, you will find that the value was automatically labeled R1 with 
a value of 1 kft. In order to place another resistor the same sequence must be followed, 
but this time the resistor will automatically be called R2 but with the same value of 1 kft. 
This labeling process will continue in the same manner with the same 1-kft value for as 
many resistors as you place. As was done with OrCAD, the resistor labels and values can 
be changed quite easily. Of course, if the chosen resistor is a standard value then it can be 
found directly under the RESISTOR listing of “real” components. 

We are now ready to build the diode network of Example 2.13 so we can compare 
results. The diodes chosen will be commercially available under the “real” listing. In this 
case two 1N4009 diodes were found by first selecting the keypad Place Diode to the 
right of the Place Basic keypad to obtain the Select a Component dialog box. Then the 
sequence Family-DIODE-1N4009-OK will result in a diode on the screen labeled D1 
with 1N4009 below the symbol, as shown in Fig. 2.151. Next we can place the resistors 
on the screen by going to the RESISTOR option and typing in the value of one of the 
resistors, in this case, the 3.3-kft resistor in the area provided at the top of the resistor 
listing. This certainly removes the need to scroll through the list looking for a particular 
resistor. Once found and placed, it will appear as R1 with a value of 3.3 kft. The same 
procedure will result in a second resistor called R2 with a value of 5.6 kft. In each case the 
elements are initially placed closest to where they will end up. The dc voltage source is 
found by going to the Place Source keypad, which is the first keypad in the Component 
toolbar. Under Family, POWER SOURCES is selected, followed by DC.POWER. 
Click OK and a voltage source will appear on the screen with the label VI at a level of 
12 V. The last circuit element to be set on the screen is the ground, which is accomplished 
by going back to the Place Source option and, after selecting POWER SOURCES, 
choosing “ground” under the Component listing. Click OK and the ground can be placed 
anywhere on the screen. 




FIG. 2.151 

Verifying the results of Example 2.13 using Multisim. 

Now that all the components are on the screen, they must be placed and labeled properly. 
For each component, simply selecting the device will create a blue dashed box around it to 
indicate it is in the active mode. When clicked to establish this condition, it can be moved 
to any location on the screen. To rotate an element, establish the active mode and apply 
Crtl-R to rotate it 90 degrees. Each application of this process will rotate it an additional 
90 degrees. Changing a label simply requires double-clicking the label of interest to create 







a small blue box around it and produce a dialog box for the change. For the source, a dia- 
log box labeled DC_POWER will result, in which the heading Label is selected and the 
refDEs retyped as E. Click OK and the label E will appear. The same procedure can change 
the value to 20 V, although in this case the Value heading is chosen and the units are chosen 
using the scroll at the right of the entered value. 

The next step is to determine what quantities are to be measured and how to measure 
them. For this network a multimeter will be used to measure the current through the resistor 
Rl. The multimeter is found at the top of the Instrument toolbar. After selection it can be 
placed on the screen in the same manner as the other elements. Double-clicking the meter 
will then result in the Multimeter-XXMl dialog box, in which A is selected to set the mul- 
timeter as an ammeter. In addition, the DC box (a straight line) must be selected because 
we are dealing with dc voltages. The current through the diode D1 and the voltage across 
the resistor R2 will be found using Indicators, which are found as the tenth option to the 
right on the Component toolbar. The software symbol looks like an LED with a red dashed 
figure eight inside. Click on this option and a Select a Component dialog box will appear. 
Under Family, select AMMETER and then take note of the Component listing and the 
four options for the orientation of the indicator. For our analysis the AMMETER_H will 
be chosen since the plus sign or entering point for the current is on the left for the diode 
Dl. Click OK and the indicator can be placed to the left of the diode Dl. For the voltage 
across the resistor R2, the option VOLTMETER_HR is chosen so the polarity matches 
that across the resistor. 

Finally, all the components and meters must be connected. This is accomplished by 
simply placing the cursor at the end of an element until a small circle and a set of crosshairs 
appear to designate the starting point. Once these are in place, click the location and an x 
will appear at the terminal. Then move to the end of the other element and left-click the 
mouse again — a red connecting wire will automatically appear with the most direct route 
between the two elements. The process is called Automatic Wiring. 

Now that all the components are in place it is time to initiate the analysis of the circuit, 
an operation that can be performed in one of three ways. One option is to select Simulate 
at the head of the screen followed by Run. The next is the green arrow in the Simulation 
toolbar. The last is to simply toggle the switch at the head of the screen to the 1 position. In 
each case a solution appears in the indicators after a few seconds that seems to flicker over 
time. This flickering simply indicates the software package is repeating the analysis over 
time. To accept the solution and stop the continuing simulation, either toggle the switch to 
the 0 position or select the lightning bolt keypad again. 

The current through the diode is 3.349 mA, which compares well with the 3.32 mA in 
Example 2.13. The voltage across the resistor R 2 is 18.722 V, which is close to the 18.6 V 
of the same example. After the simulation, the multimeter can be displayed as shown in 
Fig. 2.151 by double-clicking on the meter symbol. By clicking anywhere on the meter, the 
top portion is dark blue, and the meter can be moved to any location by simply clicking on 
the blue region and dragging it to the desired location. The current of 193.285 jiA is very 
close to the 212 iulA of Example 2.13. The differences are primarily due to the fact that each 
diode voltage is assumed to be 0.7 V, whereas in fact it is different for each diode of Fig. 
2.151 since the current through each is different. In all, however, the Multisim solution is 
a very close match with the approximate solution of Example 2.13. 

PROBLEMS ^ 

*Note: Asterisks indicate more difficult problems. 

2.2 Load-Line Analysis 

1. a. Using the characteristics of Fig. 2. 152b, determine I D , V D , and V R for the circuit of Fig. 2. 152a. 

b. Repeat part (a) using the approximate model for the diode, and compare results. 

c. Repeat part (a) using the ideal model for the diode, and compare results. 

2. a. Using the characteristics of Fig. 2.152b, determine I D and V D for the circuit of Fig. 2. 153. 

b. Repeat part (a) with R = 0.47 kU. 

c. Repeat part (a) with R = 0.68 kU. 

d. Is the level of V D relatively close to 0.7 V in each case? 

How do the resulting levels of I D compare? Comment accordingly. 




DIODE APPLICATIONS 



+ V D - 



Si 





(b) 

FIG. 2.152 

Problems 1 and 2. 



3. Determine the value of R for the circuit of Fig. 2.153 that will result in a diode current of 
10 mA if E = 7 V. Use the characteristics of Fig. 2.152b for the diode. 

4. a. Using the approximate characteristics for the Si diode, determine V D , I D , and for the 

circuit of Fig. 2.154. 

b. Perform the same analysis as part (a) using the ideal model for the diode. 

c. Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good 
approximation for the actual response under some conditions? 




+ 

Vp 



+ v D - 




+ 

1.5 kO V R 



FIG. 2.153 
Problems 2 and 3. 



FIG. 2.154 
Problem 4. 




PROBLEMS 



2.3 Series Diode Configurations 

5. Determine the current I for each of the configurations of Fig. 2.155 using the approximate 
equivalent model for the diode. 



12 V 



io n 

-►( / vw- 

Si 




(a) 



20 V 




(b) 



FIG. 2.155 

Problem 5. 



6 . Determine V 0 and I D for the networks of Fig. 2.156. 



b 








FIG. 2.156 
Problems 6 and 49. 

*7. Determine the level of V Q for each network of Fig. 2. 157. 





ok. 




FIG. 2.157 
Problem 7. 



*8. Determine V 0 and I D for the networks of Fig. 2.158. 





+20 V 

o vw 

6.8 kQ 



V 0 



b^ 

-^| o -20 V 

Si 



(a) 



(b) 



FIG. 2.158 

Problem 8. 



DIODE APPLICATIONS 



* 9 . Determine V ol and V 02 for the networks of Fig. 2.159. 




4.7 




(a) 




FIG. 2.159 

Problem 9. 



2.4 Parallel and Series-Parallel Configurations 

10 . Determine V 0 and I D for the networks of Fig. 2.160. 



20 V 





FIG. 2.160 

Problems 10 and 50. 



*11. Determine V 0 and I for the networks of Fig. 2. 161 . 




(a) 



+ 16 V 




(b) 



FIG. 2.161 

Problem 11. 



12 . Determine V ov V or and I for the network of Fig. 2.162. 
* 13 . Determine V 0 and I D for the network of Fig. 2. 163. 




PROBLEMS 





FIG. 2.162 FIG. 2.163 

Problem 12. Problems 13 and 51. 



2.5 AND/OR Gates 



14 . Determine V D for the network of Fig. 2.39 with 0 V on both inputs. 

15 . Determine V 0 for the network of Fig. 2.39 with 10 V on both inputs. 

16 . Determine V 0 for the network of Fig. 2.42 with 0 V on both inputs. 

17 . Determine V 0 for the network of Fig. 2.42 with 10 V on both inputs. 

18 . Determine V 0 for the negative logic OR gate of Fig. 2.164. 

19 . Determine V 0 for the negative logic AND gate of Fig. 2.165. 





20 . Determine the level of V 0 for the gate of Fig. 2. 166. 

21 . Determine V 0 for the configuration of Fig. 2.167. 




FIG. 2.166 

Problem 20. 




2.6 Sinusoidal Inputs; Half-Wave Rectification 

22 . Assuming an ideal diode, sketch v t , v d , and i d for the half-wave rectifier of Fig. 2.168. The 
input is a sinusoidal waveform with a frequency of 60 Hz. Determine the profit value of v; from 
the given dc level. 

23 . Repeat Problem 22 with a silicon diode (V K = 0.7 V). 

24 . Repeat Problem 22 with a 10 k 12 load applied as shown in Fig. 2.169. Sketch v L and i L . 




+ ? 



DIODE APPLICATIONS 




FIG. 2.168 FIG. 2.169 

Problems 22 through 24. Problem 24. 



25. For the network of Fig. 2.170, sketch v Q and determine V^c- 
*26. For the network of Fig. 2.171, sketch v 0 and i R . 




FIG. 2.170 FIG. 2.171 

Problem 25. Problem 26. 

*27. a. Given P m ax = 14 mW for each diode at Fig. 2.172, determine the maximum current rating 
of each diode (using the approximate equivalent model). 

b. Determine 7 max for the parallel diodes. 

c. Determine the current through each diode at V*- using the results of part (b). 

d. If only one diode were present, which would be the expected result? 




FIG. 2.172 

Problem 27. 




2.7 Full-Wave Rectification 

28. A full- wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k D. 

a. If silicon diodes are employed, what is the dc voltage available at the load? 

b. Determine the required PIV rating of each diode. 

c. Find the maximum current through each diode during conduction. 

d. What is the required power rating of each diode? 

29. Determine v 0 and the required PIV rating of each diode for the configuration of Fig. 2.173. In 
addition, determine the maximum current through each diode. 




FIG. 2.173 
Problem 29. 




*30. Sketch v 0 for the network of Fig. 2.174 and determine the dc voltage available. 



PROBLEMS 



25 




FIG. 2.174 

Problem 30. 



*31. Sketch v 0 for the network of Fig. 2.175 and determine the dc voltage available. 





FIG. 2.175 
Problem 31. 

2.8 Clippers 

32. Determine v 0 for each network of Fig. 2.176 for the input shown. 






33. Determine v Q for each network of Fig. 2.177 for the input shown. 




FIG. 2.177 

Problem 33. 




DIODE APPLICATIONS 



*34. Determine v Q for each network of Fig. 2.178 for the input shown. 






(a) 

FIG. 2.178 

Problem 34. 



Ideal 

-Hr — r ov, 

% 2.2 kQ 

o+5 V 

(b) 



*35. Determine v Q for each network of Fig. 2.179 for the input shown. 





FIG. 2.179 
Problem 35. 



3 V 



© — ww-|i|h 

2.2 kQ, + - 



3? si 



(b) 



36. Sketch i R and v 0 for the network of Fig. 2. 180 for the input shown. 




FIG. 2.180 

Problem 36. 



2.9 Clampers 

37. Sketch v Q for each network of Fig. 2. 18 1 for the input shown. 





20 V 




0 




-20 V 


t 




FIG. 2.181 

Problem 37. 




38. Sketch v 0 for each network of Fig. 2. 182 for the input shown. 



PROBLEMS 





FIG. 2.182 

Problem 38. 



*39. For the network of Fig. 2.183: 

a. Calculate 5 r. 

b. Compare 5 r to half the period of the applied signal. 

c. Sketch v 0 . 




FIG. 2.183 

Problem 39. 



* 40 . Design a clamper to perform the function indicated in Fig. 2.184. 




Ideal diodes 





FIG. 2.184 

Problem 40. 

* 41 . Design a clamper to perform the function indicated in Fig. 2.185. 





\ V; 

10 V 




0 




-10 V 


t 



Silicon diodes 





FIG. 2.185 

Problem 41. 





128 



DIODE APPLICATIONS 



2.10 Zener Diodes 




*42. a. Determine V L , I L , I z , and I R for the network of Fig. 2.186 if R L = 180 O. 

b. Repeat part (a) if R L = 470 D. 

c. Determine the value of R L that will establish maximum power conditions for the Zener diode. 

d. Determine the minimum value of R r to ensure that the Zener diode is in the “on” state. 







*43. a. Design the network of Fig. 2. 1 87 to maintain V L at 12 V for a load variation (I L ) from 0 mA 
to 200 mA. That is, determine R$ and V z . 
b. Determine P z max for the Zener diode of part (a). 

*44. For the network of Fig. 2.188, determine the range of V) that will maintain V L at 8 V and not 
exceed the maximum power rating of the Zener diode. 




FIG. 2.187 FIG. 2.188 

Problem 43. Problems 44 and 52. 



45. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-kfl load with 
an input that will vary between 30 V and 50 V. That is, determine the proper value of R s and 
the maximum current / ZM . 

46. Sketch the output of the network of Fig. 2.145 if the input is a 50-V square wave. Repeat for a 
5-V square wave. 

2.1 1 Voltage-Multiplier Circuits 

47. Determine the voltage available from the voltage doubler of Fig. 2. 123 if the secondary voltage 
of the transformer is 120 V (rms). 

48. Determine the required PIV ratings of the diodes of Fig. 2.123 in terms of the peak secondary 
voltage V m . 

2. 1 4 Computer Analysis 

49. Perform an analysis of the network of Fig. 2.156b using PSpice Windows. 

50. Perform an analysis of the network of Fig. 2.161b using PSpice Windows. 

51. Perform an analysis of the network of Fig. 2.162 using PSpice Windows. 

52. Perform a general analysis of the Zener network of Fig. 2.188 using PSpice Windows. 

53. Repeat Problem 49 using Multisim. 

54. Repeat Problem 50 using Multisim. 

55. Repeat Problem 5 1 using Multisim. 

56. Repeat Problem 52 using Multisim. 




"V 

C9 



Jj 



Bipolar Junction Transistors 




I J N i iJ jl 



» r iy 

l &■' *L " f “ r " s 



CHAPTER OBJECTIVES ^ 

Become familiar with the basic construction and operation of the Bipolar 
Junction Transistor. 

Be able to apply the proper biasing to insure operation in the active region. 
Recognize and be able to explain the characteristics of an npn or pnp transistor. 
Become familiar with the important parameters that define the 
response of a transistor. 

Be able to test a transistor and identify the three terminals. 



3.1 INTRODUCTION ^ 

During the period 1904 to 1947, the vacuum tube was the electronic device of interest and 
development. In 1904, the vacuum-tube diode was introduced by J. A. Fleming. Shortly 
thereafter, in 1906, Lee De Forest added a third element, called the control grid , to the 
vacuum diode, resulting in the first amplifier, the triode. In the following years, radio 
and television provided great stimulation to the tube industry. Production rose from 
about 1 million tubes in 1922 to about 100 million in 1937. In the early 1930s the four- 
element tetrode and the five-element pentode gained prominence in the electron-tube 
industry. In the years to follow, the industry became one of primary importance, and rapid 
advances were made in design, manufacturing techniques, high-power and high-frequency 
applications, and miniaturization. 

On December 23, 1947, however, the electronics industry was to experience the advent 
of a completely new direction of interest and development. It was on the afternoon of this 
day that Dr. S. William Shockley, Walter H. Brattain, and John Bardeen demonstrated the 
amplifying action of the first transistor at the Bell Telephone Laboratories as shown in 
Fig. 3.1. The original transistor (a point-contact transistor) is shown in Fig. 3.2. The ad- 
vantages of this three-terminal solid-state device over the tube were immediately obvious: 
It was smaller and lightweight; it had no heater requirement or heater loss; it had a rugged 
construction; it was more efficient since less power was absorbed by the device itself; it 
was instantly available for use, requiring no warm-up period; and lower operating voltages 
were possible. Note that this chapter is our first discussion of devices with three or more 
terminals. You will find that all amplifiers (devices that increase the voltage, current, or 
power level) have at least three terminals, with one controlling the flow or potential between 
the other two. 




Dr. William Shockley (seated); 

Dr. John Bardeen (left); Dr. Walter 
H. Brattain. (Courtesy of AT&T 
Archives and History Center.) 



Dr. Shockley 



Dr. Bardeen 



Dr. Brattain 



Born: London, 
England, 1910 
PhD Harvard, 
1936 

Born: Madison, 
Wisconsin, 1908 
PhD Princeton, 
1936 

Born: Amoy, 
China, 1902 
PhD University 
of Minnesota, 
1928 



All shared the Nobel Prize in 1956 
for this contribution. 

FIG. 3.1 

Coinventors of the first transistor 
at Bell Laboratories. 



1| * > ■* H *» ^ 1 T Ti > 1 1 ^ 




130 BIPOLAR JUNCTION 
TRANSISTORS 




FIG. 3.2 

The first transistor. ( Courtesy of 
AT&T Archives and History Center.) 




(a) 




(b) 

FIG. 3.3 

Types of transistors: (a) pnp; 
(b) npn. 



3.2 TRANSISTOR CONSTRUCTION ^ 

The transistor is a three-layer semiconductor device consisting of either two n- and one 
p- type layers of material or two p- and one n- type layers of material. The former is called 
an npn transistor , and the latter is called a pnp transistor. Both are shown in Fig. 3.3 with 
the proper dc biasing. We will find in Chapter 4 that the dc biasing is necessary to establish 
the proper region of operation for ac amplification. The emitter layer is heavily doped, 
with the base and collector only lightly doped. The outer layers have widths much greater 
than the sandwiched p- or ft-type material. For the transistors shown in Fig. 3.2 the ratio of 
the total width to that of the center layer is 0.150/0.001 = 150:1. The doping of the sand- 
wiched layer is also considerably less than that of the outer layers (typically, 1:10 or less). 
This lower doping level decreases the conductivity (increases the resistance) of this mate- 
rial by limiting the number of “free” carriers. 

For the biasing shown in Fig. 3.3 the terminals have been indicated by the capital letters 
E for emitter , C for collector , and B for base. An appreciation for this choice of notation will 
develop when we discuss the basic operation of the transistor. The abbreviation BJT, from 
bipolar junction transistor , is often applied to this three-terminal device. The term bipolar 
reflects the fact that holes and electrons participate in the injection process into the oppo- 
sitely polarized material. If only one carrier is employed (electron or hole), it is considered 
a unipolar device. The Schottky diode of Chapter 16 is such a device. 

33 TRANSISTOR OPERATION ^ 

The basic operation of the transistor will now be described using the pnp transistor of Fig. 3.3a. 
The operation of the npn transistor is exactly the same if the roles played by the electron and 
hole are interchanged. In Fig. 3.4a the pnp transistor has been redrawn without the base-to- 
collector bias. Note the similarities between this situation and that of th t forward-biased diode 
in Chapter 1. The depletion region has been reduced in width due to the applied bias, resulting 
in a heavy flow of majority carriers from the p- to the n- type material. 

Let us now remove the base-to-emitter bias of the pnp transistor of Fig. 3.3a as shown 
in Fig. 3.4b. Consider the similarities between this situation and that of the reverse-biased 
diode of Section 1.6. Recall that the flow of majority carriers is zero, resulting in only a 
minority-carrier flow, as indicated in Fig. 3.4b. In summary, therefore: 

One p-n junction of a transistor is reverse-biased , whereas the other is forward-biased. 



+ Majority carriers 



+ Minority carriers 

► 





Biasing a transistor: (a) forward-bias; (b) reverse-bias. 



In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the resulting 
majority- and minority-carrier flows indicated. Note in Fig. 3.5 the widths of the depletion 
regions, indicating clearly which junction is forward-biased and which is reverse-biased. 
As indicated in Fig. 3.5, a large number of majority carriers will diffuse across the forward- 
biased p-n junction into the n- type material. The question then is whether these carriers will 
contribute directly to the base current I B or pass directly into the p-type material. Since the 
sandwiched ft-type material is very thin and has a low conductivity, a very small number of 




COMMON-BASE 131 
CONFIGURATION 



FIG. 3.5 

Majority and minority carrier flow of a pnp 
transistor. 



these carriers will take this path of high resistance to the base terminal. The magnitude of the 
base current is typically on the order of microamperes, as compared to milliamperes for the 
emitter and collector currents. The larger number of these majority carriers will diffuse across 
the reverse-biased junction into the /7-type material connected to the collector terminal as indi- 
cated in Fig. 3.5. The reason for the relative ease with which the majority carriers can cross the 
reverse-biased junction is easily understood if we consider that for the reverse-biased diode 
the injected majority carriers will appear as minority carriers in the / 2 -type material. In other 
words, there has been an injection of minority carriers into the n - type base region material. 
Combining this with the fact that all the minority carriers in the depletion region will cross the 
reverse-biased junction of a diode accounts for the flow indicated in Fig. 3.5. 

Applying Kirchhoff s current law to the transistor of Fig. 3.5 as if it were a single node, 
we obtain 



Ie ~ Ic + h 



( 3 . 1 ) 



and find that the emitter current is the sum of the collector and base currents. The collector 
current, however, comprises two components — the majority and the minority carriers as 
indicated in Fig. 3.5. The minority-current component is called the leakage current and is 
given the symbol I co (7c current with emitter terminal Open). The collector current, there- 
fore, is determined in total by 




E o \ / o c 






6 

B 



(a) 



( 3 . 2 ) 



For general-purpose transistors, I c is measured in milliamperes and I co is measured in 
microamperes or nanoamperes. I co , like I s for a reverse-biased diode, is temperature sen- 
sitive and must be examined carefully when applications of wide temperature ranges are 
considered. It can severely affect the stability of a system at high temperature if not con- 
sidered properly. Improvements in construction techniques have resulted in significantly 
lower levels of I co , to the point where its effect can often be ignored. 



lr = Ic 



+ 7 



co m 





ZA COMMON-BASE CONFIGURATION ^ 

The notation and symbols used in conjunction with the transistor in the majority of texts 
and manuals published today are indicated in Fig. 3.6 for the common-base configuration 
with pnp and npn transistors. The common-base terminology is derived from the fact that 
the base is common to both the input and output sides of the configuration. In addition, the 
base is usually the terminal closest to, or at, ground potential. Throughout this text all cur- 
rent directions will refer to conventional (hole) flow rather than electron flow. The result is 
that the arrows in all electronic symbols have a direction defined by this convention. Recall 
that the arrow in the diode symbol defined the direction of conduction for conventional 
current. For the transistor: 

The arrow in the graphic symbol defines the direction of emitter current ( conventional 
flow) through the device. 



Eo 



"V 

7 4 



■O C 



6 

B 

(b) 

FIG. 3.6 

Notation and symbols used with the 
common-base configuration: (a) pnp 
transistor; (b) npn transistor. 





132 BIPOLAR JUNCTION All the current directions appearing in Fig. 3.6 are the actual directions as defined by the 

TRAN S I STO RS choice of conventional flow. Note in each case that I E = I c + I B . Note also that the applied 

biasing (voltage sources) are such as to establish current in the direction indicated for each 
branch. That is, compare the direction of I E to the polarity of V EE for each configuration 
and the direction of I c to the polarity of V cc . 

To fully describe the behavior of a three-terminal device such as the common-base am- 
plifiers of Fig. 3.6 requires two sets of characteristics — one for the driving point or input 
parameters and the other for the output side. The input set for the common-base amplifier 
as shown in Fig. 3.7 relates an input current ( I E ) to an input voltage (V BE ) for various levels 
of output voltage ( V CB )• 




Input or driving point characteristics for a 
common-base silicon transistor amplifier. 

The output set relates an output current ( I c ) to an output voltage (V CB ) for various levels 
of input current ( I E ) as shown in Fig. 3.8. The output or collector set of characteristics has 
three basic regions of interest, as indicated in Fig. 3.8: the active , cutoff, \ and saturation 




FIG. 3.8 

Output or collector characteristics for a common-base transistor amplifier. 



regions. The active region is the region normally employed for linear (undistorted) ampli- 
fiers. In particular: 

In the active region the base-emitter junction is forward-biased, whereas the collector- 
base junction is reverse-biased. 

The active region is defined by the biasing arrangements of Fig. 3.6. At the lower end of 
the active region the emitter current ( I E ) is zero, and the collector current is simply that due to 
the reverse saturation current I co , as indicated in Fig. 3.9. The current I co is so small (micro- 
amperes) in magnitude compared to the vertical scale of I c (milliamperes) that it appears on 
virtually the same horizontal line as I c = 0. The circuit conditions that exist when I E = 0 for 
the common-base configuration are shown in Fig. 3.9. The notation most frequently used 
for I co on data and specification sheets is, as indicated in Fig. 3.9, Icbo (the collector-to- 
base current with the emitter leg open). Because of improved construction techniques, the 
level of I C bo f° r general-purpose transistors in the low- and mid-power ranges is usually 
so low that its effect can be ignored. However, for higher power units Iqbo will still appear 
in the microampere range. In addition, keep in mind that Icbcb like f° r the diode (both 
reverse leakage currents) is temperature sensitive. At higher temperatures the effect of Icbo 
may become an important factor since it increases so rapidly with temperature. 

Note in Fig. 3.8 that as the emitter current increases above zero, the collector current 
increases to a magnitude essentially equal to that of the emitter current as determined by 
the basic transistor-current relations. Note also the almost negligible effect of V C b on the 
collector current for the active region. The curves clearly indicate that a first approximation 
to the relationship between I E and I E in the active region is given by 




( 3 . 3 ) 



As inferred by its name, the cutoff region is defined as that region where the collector 
current is 0 A, as revealed on Fig. 3.8. In addition: 

In the cutoff region the base-emitter and collector-base junctions of a transistor are 
both reverse-biased. 

The saturation region is defined as that region of the characteristics to the left of 
Vcb = 0 V. The horizontal scale in this region was expanded to clearly show the dramatic 
change in characteristics in this region. Note the exponential increase in collector current 
as the voltage V E b increases toward 0 V. 

In the saturation region the base-emitter and collector-base junctions are forward-biased. 

The input characteristics of Fig. 3.7 reveal that for fixed values of collector voltage ( Vcb), 
as the base-to-emitter voltage increases, the emitter current increases in a manner that closely 
resembles the diode characteristics. In fact, increasing levels of V C b have such a small effect 
on the characteristics that as a first approximation the change due to changes in V C b can he 
ignored and the characteristics drawn as shown in Fig. 3.10a. If we then apply the piecewise- 
linear approach, the characteristics of Fig. 3.10b result. Taking it a step further and ignoring 
the slope of the curve and therefore the resistance associated with the forward-biased junction 
results in the characteristics of Fig. 3. 10c. For the analysis to follow in this book the equivalent 
model of Fig. 3.10c will be employed for all dc analysis of transistor networks. That is, once a 
transistor is in the “on” state, the base-to-emitter voltage will be assumed to be the following: 



V be = 0.7 V 



( 3 . 4 ) 



In other words, the effect of variations due to V C b an d the slope of the input characteristics 
will be ignored as we strive to analyze transistor networks in a manner that will provide a 
good approximation to the actual response without getting too involved with parameter 
variations of less importance. 

It is important to fully appreciate the statement made by the characteristics of Fig. 3.10c. 
They specify that with the transistor in the “on” or active state the voltage from base to 
emitter will be 0.7 V at any level of emitter current as controlled by the external network. 
In fact, at the first encounter of any transistor configuration in the dc mode, one can now 
immediately specify that the voltage from base to emitter is 0.7 V if the device is in the 
active region — a very important conclusion for the dc analysis to follow. 



COMMON-BASE 133 
CONFIGURATION 




Collector to base 

FIG. 3.9 



Reverse saturation current. 






FIG. 3.10 

Developing the equivalent model to be employed for the base-to-emitter region of an amplifier in the dc mode. 



EXAMPLE 3.1 

a. Using the characteristics of Fig. 3.8, determine the resulting collector current if I E = 3 mA 
and V CB = 10 V. 

b. Using the characteristics of Fig. 3.8, determine the resulting collector current if I E 
remains at 3 mA but Vqb is reduced to 2 V. 

c. Using the characteristics of Figs. 3.7 and 3.8, determine V B e if 7c = 4 mA and Vqb = 20 V. 

d. Repeat part (c) using the characteristics of Figs. 3.8 and 3.10c. 

Solution: 

a. The characteristics clearly indicate that 7c = I E — 3 mA. 

b. The effect of changing V CB is negligible and 7 C continues to be 3 mA. 

c. From Fig. 3.8, I E = I c = 4 mA. On Fig. 3.7 the resulting level of V BE is about 0.74 V. 

d. Again from Fig. 3.8, I E = 7 C = 4 mA. However, on Fig. 3.10c, V BE is 0.7 V for any 
level of emitter current. 



Alpha (a) 

DC Mode In the dc mode the levels of 7 C and I E due to the majority carriers are related by 
a quantity called alpha and defined by the following equation: 




( 3 . 5 ) 



where I c and I E are the levels of current at the point of operation. Even though the charac- 
teristics of Fig. 3.8 would suggest that a = 1, for practical devices alpha typically extends 
from 0.90 to 0.998, with most values approaching the high end of the range. Since alpha is 
defined solely for the majority carriers, Eq. (3.2) becomes 



7 c — a h + 7 cbo 



( 3 . 6 ) 



For the characteristics of Fig. 3.8 when I E = 0 mA, I c is therefore equal to Icbcb but as 
mentioned earlier, the level of I C bo is usually so small that it is virtually undetectable on 
the graph of Fig. 3.8. In other words, when I E = 0 mA on Fig. 3.8, I c also appears to be 0 mA 
for the range of V CB values. 



134 



AC Mode For ac situations where the point of operation moves on the characteristic 
curve, an ac alpha is defined by 



COMMON-BASE 135 
CONFIGURATION 



M c 




“ ac A I E 


VcB = constant 



( 3 . 7 ) 



The ac alpha is formally called the common-base , short-circuit , amplification factor , for 
reasons that will be more obvious when we examine transistor equivalent circuits in 
Chapter 5. For the moment, recognize that Eq. (3.7) specifies that a relatively small change 
in collector current is divided by the corresponding change in I E with the collector-to-base 
voltage held constant. For most situations the magnitudes of a ac and a dc are quite close, 
permitting the use of the magnitude of one for the other. The use of an equation such as 
(3.7) will be demonstrated in Section 3.6. 

Biasing 

The proper biasing of the common-base configuration in the active region can be deter- 
mined quickly using the approximation I c = I E and assuming for the moment that 
I B = 0 p, A. The result is the configuration of Fig. 3. 1 1 for the pnp transistor. The arrow of 
the symbol defines the direction of conventional flow for I E = I c . The dc supplies are 
then inserted with a polarity that will support the resulting current direction. For the npn 
transistor the polarities will be reversed. 



E C 




FIG. 3.11 

Establishing the proper biasing 
management for a common-base pnp 
transistor in the active region. 



Some students feel that they can remember whether the arrow of the device symbol is 
pointing in or out by matching the letters of the transistor type with the appropriate letters 
of the phrases “pointing in” or “not pointing in.” For instance, there is a match between 
the letters npn and the italic letters of not pointing in and the letters pnp with pointing in. 

Breakdown Region 

As the applied voltage V E b increases there is a point where the curves take a dramatic 
upswing in Fig. 3.8. This is due primarily to an avalanche effect similar to that described 
for the diode in Chapter 1 when the reverse-bias voltage reached the breakdown region. 
As stated earlier the base-to-collector junction is reversed biased in the active region, but 
there is a point where too large a reverse-bias voltage will lead to the avalanche effect. 
The result is a large increase in current for small increases in the base-to-collector 
voltage. The largest permissible base-to-collector voltage is labeled BV C bo as shown 
in Fig. 3.8. It is also referred to as V{br)CBO as shown on the characteristics of Fig. 3.23 to 
be discussed later. Note in each of the above notations the use of the uppercase letter O to 
represent that the emitter leg is in the open state (not connected). It is important to remem- 
ber when taking note of this data point that this limitation is only for the common-base 
configuration. You will find in the common-emitter configuration that this limiting volt- 
age is quite a bit less. 



136 BIPOLAR JUNCTION 
TRANSISTORS 



3.5 COMMON-EMITTER CONFIGURATION 



The most frequently encountered transistor configuration appears in Fig. 3.12 for the pnp 
and npn transistors. It is called the common- emitter configuration because the emitter is 
common to both the input and output terminals (in this case common to both the base and 
collector terminals). Two sets of characteristics are again necessary to describe fully the 
behavior of the common-emitter configuration: one for the input or base-emitter circuit 
and one for the output or collector-emitter circuit. Both are shown in Fig. 3.13. 




FIG. 3.12 

Notation and symbols used with the common-emitter configuration: (a) npn transistor; 

(b) pnp transistor. 





FIG. 3.13 

Characteristics of a silicon transistor in the common- emitter configuration: (a) collector characteristics; (b) base characteristics. 





The emitter, collector, and base currents are shown in their actual conventional current 
direction. Even though the transistor configuration has changed, the current relations devel- 
oped earlier for the common-base configuration are still applicable. That is, I E = I c + I B 
and I c — aI E . 

For the common-emitter configuration the output characteristics are a plot of the output 
current ( I c ) versus output voltage (Vce) for a range of values of input current ( I B ). The input 
characteristics are a plot of the input current ( I B ) versus the input voltage ( V BE ) for a range 
of values of output voltage (Vce)- 

Note that on the characteristics of Fig. 3.14 the magnitude of I B is in microamperes, 
compared to milliamperes of I c . Consider also that the curves of I B are not as horizontal as 
those obtained for I E in the common-base configuration, indicating that the collector-to- 
emitter voltage will influence the magnitude of the collector current. 

The active region for the common-emitter configuration is that portion of the upper-right 
quadrant that has the greatest linearity, that is, that region in which the curves for I B are 
nearly straight and equally spaced. In Fig. 3.14a this region exists to the right of the verti- 
cal dashed line at V E E SSLt and above the curve for I B equal to zero. The region to the left of 
V C £ sat is called the saturation region. 

In the active region of a common-emitter amplifier , the base-emitter junction is 
forward-biased , whereas the collector-base junction is reverse-biased . 



You will recall that these were the same conditions that existed in the active region of 
the common-base configuration. The active region of the common-emitter configuration 
can be employed for voltage, current, or power amplification. 

The cutoff region for the common-emitter configuration is not as well defined as for the 
common-base configuration. Note on the collector characteristics of Fig. 3.14 that I E is not 
equal to zero when I B is zero. For the common-base configuration, when the input current 
I E was equal to zero, the collector current was equal only to the reverse saturation current 
Icoi so that the curve I E = 0 and the voltage axis were, for all practical purposes, one. 

The reason for this difference in collector characteristics can be derived through the 
proper manipulation of Eqs. (3.3) and (3.6). That is, 

Eq. (3.6): I E — od E + Iqbo 



Substitution gives 
Rearranging yields 



Eq. (3.3): I c — a(Ic + h) + Icbo 

t _ aI B , Icbo 

L c ~ + , 

1 — a 1 — a 



( 3 . 8 ) 



If we consider the case discussed above, where I B = 0 A, and substitute a typical value 
of a such as 0.996, the resulting collector current is the following: 

«(0 A) Icbo 



Ir = 



1 — a 



+ 



1 - 0.996 



Icbo 

0.004 



— 250 I CB0 



If Icbo were 1 M A, the resulting collector current with I B = 0 A would be 250(1 /nA) = 
0.25 mA, as reflected in the characteristics of Fig. 3.14. 

For future reference, the collector current defined by the condition I B = 0 /mA will be 
assigned the notation indicated by the following equation: 



COMMON-EMITTER 137 
CONFIGURATION 



j Icbo 




'CEO ~ n 

1 — a 


I B =0 fiA 



( 3 . 9 ) 



In Fig. 3.13 the conditions surrounding this newly defined current are demonstrated with 
its assigned reference direction. 

For linear ( least distortion ) amplification purposes, cutoff for the common-emitter 
configuration will be defined by Ic — Iceo- 

In other words, the region below I B = 0 /mA is to be avoided if an undistorted output 
signal is required. 

When employed as a switch in the logic circuitry of a computer, a transistor will have 
two points of operation of interest: one in the cutoff and one in the saturation region. The 



138 BIPOLAR JUNCTION 
TRANSISTORS 




FIG. 3.14 

Circuit conditions related to Iceo- 




FIG. 3.15 

Piecewise-linear equivalent for the 
diode characteristics of Fig. 3.13b. 



cutoff condition should ideally be I c = 0 mA for the chosen V CE voltage. Since Iqeo I s typi- 
cally low in magnitude for silicon materials, cutoff will exist for switching purposes when 
I B = 0 ptA or I c = IcEof or silicon transistors only. For germanium transistors , however , 
cutoff for switching purposes will be defined as those conditions that exist when Iq = Icbo- 
This condition can normally be obtained for germanium transistors by reverse-biasing the 
base-to-emitter junction a few tenths of a volt. 

Recall for the common-base configuration that the input set of characteristics was ap- 
proximated by a straight-line equivalent that resulted in V BE = 0.7 V for any level of I E 
greater than 0 mA. For the common-emitter configuration the same approach can be taken, 
resulting in the approximate equivalent of Fig. 3.15. The result supports our earlier conclu- 
sion that for a transistor in the “on” or active region the base-to-emitter voltage is 0.7 V. In 
this case the voltage is fixed for any level of base current. 



EXAMPLE 3.2 

a. Using the characteristics of Fig. 3.13, determine Iq at I B = 30 ptA and Vce = 10 V. 

b. Using the characteristics of Fig. 3.13, determine 1q at V BE = 0.7 V and Vqe ~ 15 V. 

Solution: 

a. At the intersection of I B = 30 pt A and Vqe — 10 V, I c = 3.4 mA. 

b. Using Fig. 3.13b, we obtain I B = 20 pi A at the intersection of V BE — 0.7 V and Vqe ~ 
15 V (between V CE = 10 V and 20 V). From Fig. 3.13a we find that I c = 2.5 mA at the 
intersection of I B = 20 pi A and Vce —15 V. 



Beta (P) 

DC Mode In the dc mode the levels of Iq and I B are related by a quantity called beta and 
defined by the following equation: 




( 3 . 10 ) 



where I c and I B are determined at a particular operating point on the characteristics. For 
practical devices the level of / 3 typically ranges from about 50 to over 400, with most in the 
midrange. As for a, the parameter (3 reveals the relative magnitude of one current with 
respect to the other. For a device with a [3 of 200, the collector current is 200 times the 
magnitude of the base current. 



On specification sheets /3^ c is usually included as h FE with the italic letter h derived from 
an ac hybrid equivalent circuit to be introduced in Chapter 5. The subscript FE is derived 
from/orward-current amplification and common-emitter configuration, respectively. 

AC Mode For ac situations an ac beta is defined as follows: 



COMMON-EMITTER 139 
CONFIGURATION 



/^ac 



A I c 
A Ib 



V CE = constant 



( 3 . 11 ) 



The formal name for /3 ac is common- emitter, forward- current, amplification factor. Since the 
collector current is usually the output current for a common-emitter configuration and the base 
current is the input current, the term amplification is included in the nomenclature above. 

Equation (3. 1 1) is similar in format to the equation for a ac in Section 3.4. The procedure 
for obtaining a ac from the characteristic curves was not described because of the difficulty 
of actually measuring changes of Ic and I E on the characteristics. Equation (3.11), however, 
can be described with some clarity, and, in fact, the result can be used to find a ac using an 
equation to be derived shortly. 

On specification sheets /3 ac is normally referred to as hf e . Note that the only difference 
between the notation used for the dc beta, specifically, /3^ c = h FE , is the type of lettering 
for each subscript quantity. 

The use of Eq. (3.11) is best described by a numerical example using an actual set of 
characteristics such as appearing in Fig. 3.13a and repeated in Fig. 3.17. Let us determine 
/3 ac for a region of the characteristics defined by an operating point of I B = 25 pi A and Vqe 
= 7.5 V as indicated on Fig. 3.16. The restriction of V E e ~ constant requires that a vertical 
line be drawn through the operating point at Vqe = 7.5 V. At any location on this vertical 
line the voltage Vqe is 7.5 V, a constant. The change in I B (AI B ) as appearing in Eq. (3.11) 
is then defined by choosing two points on either side of the g-point along the vertical axis 
of about equal distances to either side of the g-point. For this situation the I B = 20 pi A and 
30 pi A curves meet the requirement without extending too far from the g-point. They also 




FIG. 3.16 

Determining /3 ac and p& c from the collector characteristics. 



140 BIPOLAR JUNCTION 
TRANSISTORS 



define levels of I B that are easily defined rather than require interpolation of the level of I B 
between the curves. It should be mentioned that the best determination is usually made by 
keeping the chosen A I B as small as possible. At the two intersections of I B and the vertical axis, 
the two levels of I c can be determined by drawing a horizontal line over to the vertical axis and 
reading the resulting values of I c . The resulting /3 ac for the region can then be determined by 



Aic 



A Ic = 7 C 2 ~ 7 Ci 

A/ S ^CE— constant 7 «2 “ 7 «l 



3.2 mA — 2.2 mA 1mA 



30 /x A — 20 in A 10 iulA 

= 100 



The solution above reveals that for an ac input at the base, the collector current will be 
about 100 times the magnitude of the base current. 

If we determine the dc beta at the g-point, we obtain 



/3dc = t - = 



2.7 mA 



= 108 



I B 25 fnA 

Although not exactly equal, the levels of /3 ac and /3 dc are usually reasonably close and 
are often used interchangeably. That is, if /3 ac is known, it is assumed to be about the same 
magnitude as /3d c , and vice versa. Keep in mind that in the same lot (large number of transis- 
tors manufactured at the same time), the value of /3 ac will vary somewhat from one transistor 
to the next even though each transistor has the same number code. The variation may not 
be significant, but for the majority of applications, it is certainly sufficient to validate the 
approximate approach above. Generally, the smaller the level of I C eo » the closer are the 
magnitudes of the two betas. Since the trend is toward lower and lower levels of Iceo> 
the validity of the foregoing approximation is further substantiated. 

If the characteristics of a transistor are approximated by those appearing in Fig. 3.17, 
the level of /3 ac would be the same in every region of the characteristics. Note that the step 
in I B is fixed at 10 /ulA and the vertical spacing between curves is the same at every point in 
the characteristics — namely, 2 mA. Calculating the /3 ac at the g-point indicated results in 






A I_c 

A / B 



9 mA - 7 mA 



2 mA 



45 /jlA — 35 /jlA 10 /jlA 



200 




FIG. 3.17 

Characteristics in which /3 ac is the same everywhere and /3 ac = /3d c . 



Determining the dc beta at the same g-point results in 

8 mA 



Ic 

Pdc — ~T ~ * 

I B 40 /jl A 



= 200 



revealing that if the characteristics have the appearance of Fig. 3.17, the magnitudes of /3 ac and 
/3d c will be the same at every point on the characteristics. In particular, note that Iqeo = 0 /jlA. 



Although a true set of transistor characteristics will never have the exact appearance of 
Fig. 3.17, it does provide a set of characteristics for comparison with those obtained from 
a curve tracer (to be described shortly). 

For the analysis to follow, the subscript dc or ac will not be included with /3 to avoid 
cluttering the expressions with unnecessary labels. For dc situations it will simply be rec- 
ognized as /3dc and for any ac analysis as /3 ac . If a value of /3 is specified for a particular 
transistor configuration, it will normally be used for both the dc and ac calculations. 

A relationship can be developed between /3 and a using the basic relationships in- 
troduced thus far. Using (3 = Ic/h* we have I B = I c /f3 , and from a = I C /I E we have 
I E — Ic/ a - Substituting into 



we have 



Ie ~ Ic + h 

I c Ic 

— = I c + — 

a c (3 



and dividing both sides of the equation by I E results in 



or 



1 1 

- = 1 + - 
a / 3 

f3 = a/3 + a = (J3 + 1 )a 



so that 



or 





J8 


Oi — 


P + 1 




p = 


a 


1 — a 



In addition, recall that 



but using an equivalence of 



Iceo ~ 



Icbo 
1 — a 




P + 1 



derived from the above, we find that 

Iceo = (P + 1 Ycbo 



( 3 . 12 ) 

( 3 . 13 ) 



or 



Iceo = filcBO 



( 3 . 14 ) 



as indicated on Fig. 3.13a. Beta is a particularly important parameter because it provides a 
direct link between current levels of the input and output circuits for a common-emitter 
configuration. That is, 



IC = Ph 



( 3 . 15 ) 



and since 



we have 



Ie ~ Ic + h 

= Ph + h 

I E = 08 + 1 )I B 



( 3 . 16 ) 



Both of the equations above play a major role in the analysis in Chapter 4. 



COMMON-EMITTER 141 
CONFIGURATION 



Biasing 

The proper biasing of a common-emitter amplifier can be determined in a manner similar 
to that introduced for the common-base configuration. Let us assume that we are presented 
with an npn transistor such as shown in Fig. 3.18a and asked to apply the proper biasing to 
place the device in the active region. 






FIG. 3.18 

Determining the proper biasing arrangement for a common-emitter npn transistor configuration. 



The first step is to indicate the direction of I E as established by the arrow in the tran- 
sistor symbol as shown in Fig. 3.18b. Next, the other currents are introduced as shown, 
keeping in mind Kirchhoff s current law relationship: I c + I B = I E . That is, I E is the sum 
of Ic and I B and both I c and I B must enter the transistor structure. Finally, the supplies are 
introduced with polarities that will support the resulting directions of I B and I E as shown 
in Fig. 3.18c to complete the picture. The same approach can be applied to pnp transistors. 
If the transistor of Fig. 3.18 was a pnp transistor, all the currents and polarities of Fig. 
3.18c would be reversed. 

Breakdown Region 

As with the common-base configuration, there is a maximum collector-emitter voltage that 
can be applied and still remain in the active stable region of operation. In Fig. 3.19 the 
characteristics of Fig. 3.8 have been extended to demonstrate the impact on the character- 
istics at high levels of V EE - At high levels of base current the currents almost climb verti- 
cally, whereas at lower levels a region develops that seems to back up on itself. This region 
is particularly noteworthy because an increase in current is resulting in a drop in voltage — 
totally different from that of any resistive element where an increase in current results in 
an increase in potential drop across the resistor. Regions of this nature are said to have a 



Ic (mA) 




142 



FIG. 3.19 

Examining the breakdown region of a transistor in the common- emitter 
configuration. 



negative-resistance characteristic. Although the concept of a negative resistance may COMMON-COLLECTOR 143 
seem strange at this point, this text will introduce devices and systems that rely on this type CO N FI G U RATI 0 N 

of characteristic to perform their desired task. 

The recommended maximum value for a transistor under normal operating conditions is 
labeled BVqeo as shown in Fig. 3. 19 or V{br)CEO as shown in Fig. 3.23. It is less than BV cbo 
and in fact, is often half the value of BV cbo . For this breakdown region there are two reasons 
for the dramatic change in the curves. One is the avalanche breakdown mentioned for the 
common-base configuration, whereas the other, called punch-through, is due to the Early 
Effect, to be introduced in Chapter 5. In total the avalanche effect is dominant because any 
increase in base current due to the breakdown phenomena will be increase the resulting 
collector current by a factor beta. This increase in collector current will then contribute to 
the ionization (generation of free carriers) process during breakdown, which will cause a 
further increase in base current and even higher levels of collector current. 



5.6 COMMON-COLLECTOR CONFIGURATION ^ 

The third and final transistor configuration is the common-collector configuration , shown 
in Fig. 3.20 with the proper current directions and voltage notation. The common-collector 
configuration is used primarily for impedance-matching purposes since it has a high input 
impedance and low output impedance, opposite to that of the common-base and common- 
emitter configurations. 






FIG. 3.20 

Notation and symbols used with the common-collector configuration : (a) pnp transistor; 

(b) npn transistor. 

A common-collector circuit configuration is provided in Fig. 3.21 with the load resistor 
connected from emitter to ground. Note that the collector is tied to ground even though the 
transistor is connected in a manner similar to the common-emitter configuration. From a 
design viewpoint, there is no need for a set of common-collector characteristics to choose 
the parameters of the circuit of Fig. 3.21. It can be designed using the common-emitter 
characteristics of Section 3.5. For all practical purposes, the output characteristics of the 
common-collector configuration are the same as for the common-emitter configuration. For 
the common-collector configuration the output characteristics are a plot of I E versus Vqe 
for a range of values of I B . The input current, therefore, is the same for both the common- 
emitter and common-collector characteristics. The horizontal voltage axis for the common- 
collector configuration is obtained by simply changing the sign of the collector-to-emitter 
voltage of the common-emitter characteristics. Finally, there is an almost unnoticeable 




FIG. 3.21 

Common-collector configuration 
used for impedance-matching 
purposes. 





144 BIPOLAR JUNCTION 
TRANSISTORS 



change in the vertical scale of I c of the common-emitter characteristics if I c is replaced 
by I E for the common-collector characteristics (since a = 1). For the input circuit of the 
common-collector configuration the common-emitter base characteristics are sufficient for 
obtaining the required information. 



5-7 LIMITS OF OPERATION ^ 

For each transistor there is a region of operation on the characteristics that will ensure that 
the maximum ratings are not being exceeded and the output signal exhibits minimum dis- 
tortion. Such a region has been defined for the transistor characteristics of Fig. 3.22. All of 
the limits of operation are defined on a typical transistor specification sheet described in 
Section 3.8. 

Some of the limits of operation are self-explanatory, such as maximum collector 
current (normally referred to on the specification sheet as continuous collector current) 
and maximum collector-to-emitter voltage (often abbreviated as BV CE0 or V(br)CEO on 
the specification sheet). For the transistor of Fig. 3.22, I Cmax was specified as 50 mA and 
BVceo as 20 V. The vertical line on the characteristics defined as Vc Esat specifies the 
minimum V EE that can be applied without falling into the nonlinear region labeled the 
saturation region. The level of V CE sat is typically in the neighborhood of the 0.3 V speci- 
fied for this transistor. 

The maximum dissipation level is defined by the following equation: 



P c — V CE^C 

^max K ' 1 -‘ ^ 



( 3 . 17 ) 




FIG. 3.22 

Defining the linear ( undistorted ) region of operation for a transistor. 



For the device of Fig. 3.22, the collector power dissipation was specified as 300 mW. 
The question then arises of how to plot the collector power dissipation curve specified by 
the fact that 



or 



Pr = V CE Ic = 300 mW 

''-'max j 

V CE I C = 300 mW 



At I At any point on the characteristics the product of Vqe an d Ic must be equal to 
300 mW. If we choose I c to be the maximum value of 50 mA and substitute into the rela- 
tionship above, we obtain 



V CE Ic = 300 mW 
V C £(50 mA) = 300 mW 



VcE 



300 mW 
50 mA 



6 v 



TRANSISTOR 145 
SPECIFICATION SHEET 



At V CEn As a result we find that if I c = 50 mA, then Vqe - 6 Von the power dissipa- 
tion curve as indicated in Fig. 3.22. If we now choose V CE to be its maximum value of 
20 V, the level of 1q is the following: 



(20 V)/ c = 300 mW 
300 mW 

1 r = 

20 V 



= 15 mA 



defining a second point on the power curve. 



At l c = \l Cmax If we now choose a level of Iq in the midrange such as 25 mA and solve 
for the resulting level of Vce, we obtain 

V C £(25 mA) = 300 mW 



and 



Vce ~ 



300 mW 
25 mA 



12 V 



as also indicated in Fig. 3.22. 

A rough estimate of the actual curve can usually be drawn using the three points defined 
above. Of course, the more points one has, the more accurate is the curve, but a rough es- 
timate is normally all that is required. 

The cutoff region is defined as that region below I c — Iceo • This region must also be 
avoided if the output signal is to have minimum distortion. On some specification sheets 
only I CBO is provided. One must then use the equation I CEO = [BIcbo t0 establish some 
idea of the cutoff level if the characteristic curves are unavailable. Operation in the result- 
ing region of Fig. 3.22 will ensure minimum distortion of the output signal and current and 
voltage levels that will not damage the device. 

If the characteristic curves are unavailable or do not appear on the specification sheet 
(as is often the case), one must simply be sure that 7 C , Vqei an d their product Vce^c fed 
into the following range: 



Iceo = Ic = k: mm 
v ce sx = Vce = VcE m „ 

v CEh: = P Cmm 



( 3 . 18 ) 



For the common-base characteristics the maximum power curve is defined by the following 
product of output quantities: 

( 3 . 19 ) 



P c — V CB^C 

^max ^ l> ^ 



1.8 TRANSISTOR SPECIFICATION SHEET ^ 

Since the specification sheet is the communication link between the manufacturer and 
user, it is particularly important that the information provided be recognized and correctly 
understood. Although all the parameters have not been introduced, a broad number will 
now be familiar. The remaining parameters will be introduced in the chapters that follow. 
Reference will then be made to this specification sheet to review the manner in which the 
parameter is presented. 

The information provided as Fig. 3.23 is provided by the Fairchild Semiconductor 
Corporation. The 2N4123 is a general-purpose npn transistor with the casing and terminal 



146 BIPOLAR JUNCTION 
TRANSISTORS 



identification appearing in the top-right corner of Fig. 3.23a. Most specification sheets are 
broken down into maximum ratings , thermal characteristics , and electrical characteristics. 
The electrical characteristics are further broken down into “on,” “off,” and small-signal 
characteristics. The “on” and “off” characteristics refer to dc limits, whereas the small- 
signal characteristics include the parameters of importance to ac operation. 

Note in the maximum rating list that Vcf — Vcfo — 30 V with I r = 200 mA. 

o '-'Mnax '-'max 

The maximum collector dissipation Pc max — Pd = 625 mW. The derating factor under 
the maximum rating specifies that the maximum rating must be decreased 5 mW for every 
1° rise in temperature above 25°C. In the “off” characteristics Iqbo is specified as 50 nA 



MAXIMUM RATINGS 



Rating 


Symbol 


2N4123 


Unit 


Collector-Emitter Voltage 


VcEO 


30 


Vdc 


Collector-Base Voltage 


VcBO 


40 


Vdc 


Emitter-Base Voltage 


Vebo 


5.0 


Vdc 


Collector Current - Continuous 


Ic 


200 


mAdc 


Total Device Dissipation @ Ta = 25 °C 


Pd 


625 


mW 


Derate above 25 °C 




5.0 


mW°C 


Operating and Storage Junction 
Temperature Range 


TjTstg 


-55 to +150 


°C 



THERMAL CHARACTERISTICS 



Characteristic 


Symbol 


Max 


Unit 


Thermal Resistance, Junction to Case 


Rfljc 


83.3 


°CW 


Thermal Resistance, Junction to Ambient 


R-0JA 


200 


°cw 


ELECTRICAL CHARACTERISTICS (T A 


= 25 °C unless otherwise noted) 



FAIRCHILD 



SEMICONDUCTOR i 



2N4123 




TO-92 



General Purpose 
Transistor 
NPN Silicon 



Characteristic 


Symbol 


Min 


Max 


Unit 


OFF CHARACTERISTICS 


Collector-Emitter Breakdown Voltage (1) 
(I c =1.0 mAdc, I E = 0) 


V(BR)CEO 


30 




Vdc 


Collector-Base Breakdown Voltage 
(I c = 10 pAdc, I E = 0) 


V(BR)CBO 


40 




Vdc 


Emitter-Base Breakdown Voltage 
(I E = 10 pAdc, I c = 0) 


V (BR)EBO 


5.0 


- 


Vdc 


Collector Cutoff Current 
(V CB = 20 Vdc, I E = 0) 


IcBO 


- 


50 


nAdc 


Emitter Cutoff Current 
(V BE = 3.0 Vdc, I c = 0) 


Iebo 


- 


50 


nAdc 


ON CHARACTERISTICS 


DC Current Gain(l) 

(I c = 2.0 mAdc, V CE = 1.0 Vdc) 
(I c = 50 mAdc, V CE = 1.0 Vdc) 


hFE 


50 

25 


150 


- 


Collector-Emitter Saturation Voltage(l) 
(Ic = 50 mAdc, Ib = 5.0 mAdc) 


VcE(sat) 


- 


0.3 


Vdc 


Base-Emitter Saturation Voltage(l) 
(Ic = 50 mAdc, Ib = 5.0 mAdc) 


VBE(sat) 


- 


0.95 


Vdc 



SMALL-SIGNAL CHARACTERISTICS 



Current-Gain - Bandwidth Product 

(I c = 10 mAdc, V CE = 20 Vdc, f = 100 MHz) 


f T 


250 




MHz 


Output Capacitance 

(V CB = 5.0 Vdc, I E = 0, f = 100 MHz) 


Cobo 


- 


4.0 


pF 


Input Capacitance 

(V BE = 0.5 Vdc, I c = 0, f = 100 kHz) 


Cibo 


- 


8.0 


pF 


Collector-Base Capacitance 

(Ie = 0, V CB = 5.0 V, f = 100 kHz) 


C c b 


- 


4.0 


pF 


Small-Signal Current Gain 

(I c = 2.0 mAdc, V CE = 10 Vdc, f = 1.0 kHz) 


hfe 


50 


200 


- 


Current Gain - High Frequency 

(I c = 10 mAdc, V CE = 20 Vdc, f = 100 MHz) 
(I c = 2.0 mAdc, V CE = 10 V, f = 1 .0 kHz) 


hfe 


2.5 

50 


200 


- 


Noise Figure 

(I c = 100 pAdc, V CE = 5.0 Vdc, R s = 1.0 k ohm, f = 1.0 kHz) 


NF 


- 


6.0 


dB 



(1) Pulse Test: Pulse Width = 300 (is. Duty Cycle = 2.0% 



(a) 



FIG. 3.23 

Transistor specification sheet. 




Time (ns) hj e Current gain 



h PARAMETERS 

V CE = 10 V,/= 1 kHz, T a = 25°C 



Figure 1 - Current Gain 




0.1 0.2 0.5 1.0 2.0 5.0 10 

I c , Collector current (mA) 

(b) 



Figure 3 - Capacitance 




0.1 0.2 0.3 0.5 0.71.0 2.0 3.0 5.0 7.0 10 20 3040 

Reverse bias voltage (V) 

(d) 



STATIC CHARACTERISTICS 




0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 

I c , Collector current (mA) 

(c) 



AUDIO SMALL SIGNAL CHARACTERISTICS 

NOISE FIGURE 

( V CE = 5 Vdc, T a = 25°C) 

Bandwidth = 1.0 Hz 



Figure 4 - Switching Times 




Figure 5 - Frequency Variations 




O' i * 

0.1 0.2 0.4 1 2 4 10 20 40 100 

/, Frequency (kHz) 



(e) 



(0 



FIG. 3.23 

Continued. 



Voltage feedback ratio (x 10 -4 ) 




0.1 0.2 0.4 



1.0 2.0 4.0 10 20 

R s , Source resistance (kQ) 



40 



100 




0.1 0.2 0.5 1.0 2.0 5.0 10 



I c , Collector current (mA) 



(g) 



(h) 




0.1 0.2 0.5 1.0 2.0 5.0 10 



I c , Collector current (mA) 




0.1 0.2 0.5 1.0 2.0 5.0 10 



I c , Collector current (mA) 



(i) 



CD 



FIG. 3.23 

Continued. 



and in the “on” characteristics VcE sat = 0-3 V. The level of h FE has a range of 50 to 150 at 
I c = 2 mA and V CE = 1 V and a minimum value of 25 at a higher current of 50 mA at the 
same voltage. 

The limits of operation have now been defined for the device and are repeated below 
in the format of Eq. (3.18) using h FE = 150 (the upper limit) and I CE0 = PIcbo = (150) 
(50 nA) = 7.5 fiA. Certainly, for many applications the 7.5 fiA = 0.0075 mA can be con- 
sidered to be 0 mA on an approximate basis. 



Limits of Operation 
7.5 iulA ^ I c ^ 200 mA 
0.3 V ^ V CE = 30 V 
V CE Ic = 650 mW 



fi Variation 

In the small-signal characteristics the level of hf e (/3 ac ) is provided along with a plot of how 
it varies with collector current in Fig. 3.23b. In Fig. 3.23c the effect of temperature and 
collector current on the level of h FE (/3d c ) is demonstrated. At room temperature (25 °C), 
note that h FE (/3d c ) is a maximum value of 1 in the neighborhood of about 8 mA. As I c 
increases beyond this level, h FE drops off to one-half the value with I c equal to 50 mA. It 
also drops to this level if I c decreases to the low level of 0. 15 mA. Since this is a normalized 



148 



TRANSISTOR TESTING 



149 



curve, if we have a transistor with /3^ c = h FF = 120 at room temperature (25 °C), the 
maximum value at 8 mA is 120. At I c = 50 mA it has dropped to about 0.52 and hf e = 
(0.52)120 = 62.4. In other words, normalizing reveals that the actual level of h FE at any 
level of I c has been divided by the maximum value of h FE at that temperature and 
I c = 8 mA. Note also that the horizontal scale of Fig. 3.23(c) is a log scale. Log scales are 
examined in depth in Chapter 9. You may want to look back at the plots of this section 
when you find time to review the first few sections of Chapter 9. 

Capacitance Variation The capacitance C iho and C 0 b 0 of Fig. 3.23(d) are the input and 
output capacitance levels, respectively, for the transistor in the common-base configura- 
tion. Their level is such that their impact can be ignored except for relatively high frequen- 
cies. Otherwise, they can be approximated by open circuits in any dc or ac analysis. 

Switching Times Figure 3.23(e) includes the important parameters that define the 
response of a transistor to an input that switches from the “off” to “on” state or vice versa. 
Each parameter will be discussed in detail in Section 4.15. 

Noise Figures Versus Frequency and Source Resistance The noise figure is a measure of 
the additional disturbance that is added to the desired signal response of an amplifier. In 
Fig. 3.23(f) the dB level of the noise figure is displayed for a wide frequency response at 
particular levels of source resistance. The lowest levels occur at the highest frequencies for 
the variety of collector currents and source resistance. As the frequency drops the noise 
figure increases with a strong sensitivity to the collector current. 

In Fig. 3.23(g) the noise figure is plotted for various levels of source resistance and 
collector current. For each current level the higher the source resistance, the higher the 
noise figure. 

Hybrid Parameters Figures 3.23(b), (h), (i), and (j) provide the components of a hybrid 
equivalent model for the transistor that will be discussed in detail in Chapter 5. In each case, 
note that the variation is plotted against the collector current — a defining level for the equiv- 
alent network. For most applications the most important parameters are hf e and h ie . The 
higher the collector current, the higher the magnitude of hf e and the lower the level of h ie . As 
indicated above, all the parameters will be discussed in detail in Sections 5.19-5.21. 

Before leaving this description of the characteristics, note that the actual collector char- 
acteristics are not provided. In fact, most specification sheets provided by manufacturers 
fail to provide the full characteristics. It is expected that the data provided are sufficient to 
use the device effectively in the design process. 



As with diodes, there are three routes one can take to check a transistor: use of a curve 
tracer , a digital meter , and an ohmmeter. 

Curve Tracer 

The curve tracer of Fig. 1.43 will provide the display of Fig. 3.24 once all the controls have 
been properly set. The smaller displays to the right reveal the scaling to be applied to the 
characteristics. The vertical sensitivity is 2 mA/div, resulting in the scale shown to the left 
of the monitor’s display. The horizontal sensitivity is 1 V/div, resulting in the scale shown 
below the characteristics. The step function reveals that the curves are separated by a dif- 
ference of 10 jx A, starting at 0 /ulA for the bottom curve. The last scale factor provided can 
be used to quickly determine the /3 ac for any region of the characteristics. Simply multiply 
the displayed factor by the number of divisions between I B curves in the region of interest. 
For instance, let us determine /3 ac at a g-point of I E = 7 mA and V EE — 5 V. In this region 
of the display, the distance between I B curves is ^ of a division, as indicated on Fig. 3.25. 
Using the factor specified, we find that 



3.9 TRANSISTOR TESTING 





150 BIPOLAR JUNCTION 
TRANSISTORS 



20 mA 




Vertical 
per div 

2mA 



Horizontal 
per div 

1 V 



Per Step 
10 jiA 



j3 or gm 
per div 

200 




Transistor 

test 



(a) 




Transistor 

JFET 

SCR 



(b) 

FIG. 3.26 

Transistor testers: (a) digital meter; 
(b) dedicated tester. ( Courtesy of 
B+K Precision Corporation .) 



FIG. 3.24 

Curve tracer response to 2N3904 npn transistor. 




FIG. 3.25 

Determining /3 ac for the transistor characteristics of Fig. 3.24 at Iq — 7 mA 
and V qe ~ 5 V. 



Using Eq. (3.11) gives 



Air 

A T B 



V CE= c< 



1.8 mA 



= 180 



10 iiA 

verifying the determination above. 



v - v 

h 2 ~ 



8.2 mA - 6.4 mA 
40 pi A — 30 pi A 



Transistor Testers 

There is a variety of transistor testers available. Some are simply part of a digital meter as 
shown in Fig. 3.26a that can measure a variety of levels in a network. Others, such as that 
in Fig. 3.26, are dedicated to testing a limited number of elements. The meter of Fig. 3.26b 
can be used to test transistors, JFETs (Chapter 6), and SCRs (Chapter 17) in and out of the 
circuit. In all cases the power must first be turned off to the circuit in which the element 
appears to ensure that the internal battery of the tester is not damaged and to provide a cor- 
rect reading. Once a transistor is connected, the switch can be moved through all the pos- 
sible combinations until the test light comes on and identifies the terminals of the transistor. 
The tester will also indicate an OK if the npn or pnp transistor is operating properly. 

Any meter with a diode-checking capability can also be used to check the status of a 
transistor. With the collector open the base-to-emitter junction should result in a low voltage 




of about 0.7 V with the red (positive) lead connected to the base and the black (negative) 
lead connected to the emitter. A reversal of the leads should result in an OL indication to 
represent the reverse-biased junction. Similarly, with the emitter open, the forward- and 
reverse-bias states of the base-to-collector junction can be checked. 

Ohmmeter 

An ohmmeter or the resistance scales of a digital multimeter (DMM) can be used to check 
the state of a transistor. Recall that for a transistor in the active region the base-to-emitter 
junction is forward-biased and the base-to-collector junction is reverse-biased. Essentially, 
therefore, the forward-biased junction should register a relatively low resistance, whereas 
the reverse-biased junction shows a much higher resistance. For an npn transistor, the 
forward-biased junction (biased by the internal supply in the resistance mode) from base to 
emitter should be checked as shown in Fig. 3.27 and result in a reading that will typically 
fall in the range of 100 12 to a few kilohms. The reverse-biased base-to-collector junction 
(again reverse-biased by the internal supply) should be checked as shown in Fig. 3.28 with 
a reading typically exceeding 100 kll. For a pnp transistor the leads are reversed for each 
junction. Obviously, a large or small resistance in both directions (reversing the leads) for 
either junction of an npn or pnp transistor indicates a faulty device. 

If both junctions of a transistor result in the expected readings, the type of transistor can 
also be determined by simply noting the polarity of the leads as applied to the base-emitter 
junction. If the positive (+) lead is connected to the base and the negative lead (-) to the 
emitter, a low resistance reading would indicate an npn transistor. A high resistance reading 
would indicate a pnp transistor. Although an ohmmeter can also be used to determine the 
leads (base, collector, and emitter) of a transistor, it is assumed that this determination can 
be made by simply looking at the orientation of the leads on the casing. 



TRANSISTOR CASING 151 
AND TERMINAL 
IDENTIFICATION 



Low R 




Checking the forward-biased base-to- 
emitter junction of an npn transistor. 



High R 




Checking the reverse-biased 
base-to-collector junction of an npn 
transistor. 



3.10 TRANSISTOR CASING AND 
TERMINAL IDENTIFICATION 



After the transistor has been manufactured using one of the techniques described in Appen- 
dix A, leads of, typically, gold, aluminum, or nickel are then attached and the entire struc- 
ture is encapsulated in a container such as that shown in Fig. 3.29. Those with the 
heavy-duty construction are high-power devices, whereas those with the small can (top 
hat) or plastic body are low- to medium-power devices. 




(a) (b) (c) 

FIG. 3.29 

Various types of general-purpose or switching transistors: (a) low power; (b) medium power; 

(c) medium to high power. 



Whenever possible, the transistor casing will have some marking to indicate which leads 
are connected to the emitter, collector, or base of a transistor. A few of the methods com- 
monly used are indicated in Fig. 3.30. 

The internal construction of a TO-92 package in the Fairchild line appears in Fig. 3.31. 
Note the very small size of the actual semiconductor device. There are gold bond wires, a 
copper frame, and an epoxy encapsulation. 










152 BIPOLAR JUNCTION 
TRANSISTORS 




FIG. 3.30 

Transistor terminal identification. 




Axial molding 





FIG. 3.31 

Internal construction of a Fairchild transistor in a TO -92 package. 



Four (quad) individual pnp silicon transistors can be housed in the 14-pin plastic dual-in- 
line package appearing in Fig. 3.32a. The internal pin connections appear in Fig. 3.32b. As 
with the diode IC package, the indentation in the top surface reveals the number 1 and 14 pins. 




(Top View) 




(b) 

FIG. 3.32 



Type Q2T2905 Texas Instruments quad pnp silicon transistor: 
(a) appearance; (b) pin connections. 



5.1 1 TRANSISTOR DEVELOPMENT ^ 

As mentioned in Section 1.1, Moore’s law predicts that the transistor count of an inte- 
grated circuit will double every 2 years. First presented in a paper by Gordon E. Moore in 
1965, the prediction has had an amazing accuracy level. A plot of the transistor count ver- 
sus years appearing in Fig. 3.33 is almost linear through the years. The amazing number of 
two billion transistors in a single integrated circuit using 45 nm lines is really beyond com- 
prehension. A 1 in. line contains more than 564,000 of the 45 nm lines of construction used 
in ICs today. Try to draw 100 lines in a 1 in. width using a pencil — almost impossible. The 
relative dimensions of drawing 45 nm lines in a 1 in. width would be like drawing a line 






TRANSISTOR 153 
DEVELOPMENT 



FIG. 3.33 

Transistor IC count versus time for the period 1960 to the present. 

with a width of 1 in. across a highway that is almost 9 miles long.* Although there is con- 
tinuing talk that Moore’s law will eventually suffer from density, performance, reliability, 
and budget corners, the general consensus of the industrial community is that Moore’s law 
will continue to be applicable for the next decade or two. Although silicon continues to be 
the leading fabrication material, there is a family of semiconductors referred to as III V 
compound semiconductors (the three and five referring to the number of valence elec- 
trons in each element) that are making important inroads into future development. One in 
particular is indium gallium arsenide, or InGaAs, which has improved transport character- 
istics. Others include GaAlAs, AlGaN, and AllnN, which are all being developed for 
increased speed, reliability, stability, reduced size, and improved fabrication techniques. 

Currently the Intel® Core™ i7 Quad Core processor has over 730 million transistors 
with a clock speed of 3.33 GHz in a package slightly larger than a 1.6" square. Recent 
developments by Intel include their Tukwila processor that will house over two billion 
transistors. Interestingly enough, Intel continues to employ silicon in its research develop- 
ment of transistors that will be 30% smaller and 25% faster than today’s fastest transistors 
using 20 nm technology. IBM, in concert with the Georgia Institute of Technology, has 
developed a silicon-germanium transistor that can operate at frequencies exceeding 500 
GHz — an enormous increase over current standards. 

Innovation continues to be the backbone of this ever-developing field, with one Swedish 
team introducing a junctionless transistor primarily to simplify the manufacturing process. 
Another has introduced carbon nanotubes (a carbon molecule in the form of a hollow 
cylinder that has a diameter about 1 / 50,000 the width of a human hair) as a path toward 
faster, smaller, and cheaper transistors. Hewlett Packard is developing a Crossbar Latch 
transistor that employs a grid of parallel conducting and signal wires to create junctions 
that act as switches. 

The question was often asked many years ago: Where can the field go from here? Obvi- 
ously, based on what we see today, there seems to be no limit to the innovative spirit of 
individuals in the field as they search for new directions of investigation. 



*In metric units, it would be like drawing more than 220,000 lines in a 1-cm length or a 1-cm width line across 
a highway over 2.2 km long. 



154 BIPOLAR JUNCTION 3.12 SUMMARY 

TRANSISTORS 

Important Conclusions and Concepts 

1. Semiconductor devices have the following advantages over vacuum tubes: They are 
(1) of smaller size, (2) more lightweight, (3) more rugged, and (4) more efficient. In 
addition, they have (1) no warm-up period, (2) no heater requirement, and (3) lower 
operating voltages. 

2. Transistors are three- terminal devices of three semiconductor layers having a base or 
center layer a great deal thinner than the other two layers. The outer two layers are 
both of either n- or p- type materials, with the sandwiched layer the opposite type. 

3. One p-n junction of a transistor is forward-biased, whereas the other is reverse- 
biased. 

4. The dc emitter current is always the largest current of a transistor, whereas the base 
current is always the smallest. The emitter current is always the sum of the other two. 

5. The collector current is made up of two components: the majority component and 
the minority current (also called the leakage current). 

6. The arrow in the transistor symbol defines the direction of conventional current flow 
for the emitter current and thereby defines the direction for the other currents of the 
device. 

7. A three-terminal device needs two sets of characteristics to completely define its 
characteristics. 

8. In the active region of a transistor, the base-emitter junction is forward-biased, 
whereas the collector-base junction is reverse-biased. 

9. In the cutoff region the base-emitter and collector-base junctions of a transistor are 

both reverse-biased. 

10. In the saturation region the base-emitter and collector-base junctions are forward- 
biased. 

11. On an average basis, as a first approximation, the base-to-emitter voltage of an operat- 
ing transistor can be assumed to be 0.7 V. 

12. The quantity alpha (a) relates the collector and emitter currents and is always close to 

one. 

13. The impedance between terminals of a forward-biased junction is always relatively 
small, whereas the impedance between terminals of a reverse-biased junction is usu- 
ally quite large. 

14. The arrow in the symbol of an npn transistor points out of the device (not pointing 
in), whereas the arrow points in to the center of the symbol for a pnp transistor 
(pointing in). 

15. For linear amplification purposes, cutoff for the common-emitter configuration will 
be defined by 1q — Iceo- 

16. The quantity beta (/3) provides an important relationship between the base and collec- 
tor currents, and is usually between 50 and 400. 

17. The dc beta is defined by a simple ratio of dc currents at an operating point, 
whereas the ac beta is sensitive to the characteristics in the region of interest. For 
most applications, however, the two are considered equivalent as a first approximation. 

18. To ensure that a transistor is operating within its maximum power level rating, simply 
find the product of the collector-to-emitter voltage and the collector current, and 
compare it to the rated value. 



Equations 

Ie = IC + 


Ic-- 


— Ir T Irn , 

'“'majority ^ '-'minority 


Vbe 


= 0.7 V 




II 

o 

TJ 

Q 


°^SLC 


_ A Ic 
A Ie 


VcB = constant 


Iceo 


ICBO 
1 — a 


h = 0jiA 


I C 

Pdc = -r, 




_ A Ic 
A Ib 


VcE= constant 


a = 


1 3 

P + 1 




cT 

II 

"CO 




= 03 + 1)1 B , 


Pc 

'-'max 


; = VceE 





5.15 COMPUTER ANALYSIS 
Cadence OrCAD 



COMPUTER ANALYSIS 



155 



Since the transistor characteristics were introduced in this chapter, it seems appropriate 
that a procedure for obtaining those characteristics using PSpice Windows should be exam- 
ined. The transistors are listed in the EYAL library and start with the letter Q. The library 
includes two npn transistors, two pnp transistors, and two Darlington configurations. The 
fact that there is a series of curves defined by the levels of I B will require that a sweep of I B 
values (a nested sweep) occur within a sweep of collector- to-emitter voltages. This is 
unnecessary for the diode, however, since only one curve would result. 

First, the network in Fig. 3.34 is established using the same procedure as defined in 
Chapter 2. The voltage Vcc will establish our main sweep, whereas the voltage V BB will 
determine the nested sweep. For future reference, note the panel at the top right of the menu 
bar with the scroll control when building networks. This option allows you to retrieve ele- 
ments that have been used in the past. For instance, if you placed a resistor a few elements 
ago, simply return to the scroll bar and scroll until the resistor R appears. Click the location 
once, and the resistor will appear on the screen. 



" i m OrCAD Capture CIS - Demo Edit... i 1=1 l‘ 

File Edit View TcjoIs Place Macro PSpice 
Accessories Options Window Help 

cadence 

|g§ OrCAD 3-1 PAGE1* j 

0 / - [SCHEMATIC! : PAGE!) 




FO items selected 



FIG. 3.34 

Network employed to obtain the collector 
characteristics of the Q2N2222 transistor. 



Once the network is established as appearing in Fig. 3.34, select the New Simulation 
Profile key and insert OrCAD 3-1 as the Name. Then select Create to obtain the Simula- 
tion Settings dialog box. The Analysis type will be DC Sweep, with the Sweep variable 
being a Voltage Source. Insert VCC as the name for the swept voltage source and select 
Linear for the sweep. The Start value is 0 V, the End value 10 V, and the Increment 0.01 V. 

It is important not to select x in the top right corner of the box to leave the settings 
control. We must first enter the nested sweep variable by selecting Secondary Sweep and 
inserting VBB as the voltage source to be swept. Again, it will be a Linear sweep, but now 
the starting value will be 2.7 V to correspond with an initial current of 20 pi A as determined by 



In = 



V BB 



v BE 



Rn 



2.7 V - 0.7 V 

ioo m 



= 20 pA 



The End value is 10.7 V to correspond with a current of 100 pA. The Increment is set 
at 2 V, corresponding to a change in base current of 20 pA. Both sweeps are now set, but 
before leaving the dialog box be sure both sweeps are enabled by a check in the box 
next to each sweep. Often after entering the second sweep, the user fails to establish the 
second sweep before leaving the dialog box. Once both are selected, leave the dialog box 
and select Run PSpice. The result will be a graph with a voltage VCC varying from 0 V 



156 BIPOLAR JUNCTION 
TRANSISTORS 



I SCHEMATICl-OrCADM plot 2 - PSpice A/D Demo - [OrCAD3-l plot 2 (active)] 






| File £dit View Simulation Trace Plot Tfiols Window Help 



cadence ' 



& i 



i SCHEMATIC - ! -OrCAD 



Q 




C:\ECET110RCAD\0rCAD3-l-PSpiceFiles 



V VCC = 10 



100 %| 



FIG. 3.35 

Collector characteristics for the transistor of Fig. 3.34. 



to 10 V. To establish the various / curves, apply the sequence Trace-Add Trace to obtain 
the Add Trace dialog box. Select IC(Q1), the collector current of the transistor for the 
vertical axis. An OK, and the characteristics will appear. Unfortunately, however, they 
extend from -10 mA to +20 mA on the vertical axis. This can be corrected by the sequence 
Plot- Axis Settings, which again will result in the Axis Settings dialog box. Select Y-Axis 
and under Data Range choose User Defined and set the range as 0-20 mA. An OK, and 
the plot of Fig. 3.35 will appear. Labels on the plot can be added using the production ver- 
sion of OrCAD. 

The first curve at the bottom of Fig. 3.35 represents I B = 20 /ulA . The curve above is I B = 
40 /jl A, the next 60 /rA, and so on. If we choose a point in the middle of the characteristics 
defined by V CE = 4 V and I B = 60 /mA as shown in Fig. 3.35 (3 can be determined from 



Ic 11 mA 

[3 = — = = 183.3 

I B 60 fiA 

Like the diode, the other parameters of the device will have a noticeable effect on the oper- 
ating conditions. If we return to the transistor specifications using Edit-PSpice Model to 
obtain the PSpice Model Editor Demo dialog box, we can delete ah the parameters except 
the Bf value. Be sure to leave the parentheses surrounding the value of Bf during the dele- 
tion process. When you exit the box the Model Editor/16.3 dialog box will appear asking 
you to save changes. It was saved as OrCAD 3-1 and the circuit was simulated again to 
obtain the characteristics of Fig. 3.36 following another adjustment of the range of the 
vertical axis. 

Note first that the curves are ah horizontal, meaning the element is void of any resistive 
characteristics. In addition, the equal spacing of the curves throughout reveals that beta is the 
same everywhere. At the intersection of Vce = 4 V and I B = 60 /jl A, the new value of / 3 is 

14.6 mA 



I c 

n = f = 

l B 



= 243.3 



60 1± A 

The real value of the above analysis is to recognize that even though beta may be provided, 
the actual performance of the device will be very dependent on its other parameters. 
Assume an ideal device is always a good starting point, but an actual network provides a 
different set of results. 




FIG. 3.36 

Ideal collector characteristics for the transistor of Fig. 3.34. 




PROBLEMS 



*Note: Asterisks indicate more difficult problems. 



3.2 Transistor Construction 



1. What names are applied to the two types of BJT transistors? Sketch the basic construction of 
each and label the various minority and majority carriers in each. Draw the graphic symbol next 
to each. Is any of this information altered by changing from a silicon to a germanium base? 

2 . What is the major difference between a bipolar and a unipolar device? 

3.3 Transistor Operation 

3. How must the two transistor junctions be biased for proper transistor amplifier operation? 

4 . What is the source of the leakage current in a transistor? 

5 . Sketch a figure similar to Fig. 3.4a for the forward-biased junction of an npn transistor. 
Describe the resulting carrier motion. 

6 . Sketch a figure similar to Fig. 3.4b for the reverse-biased junction of an npn transistor. Describe 
the resulting carrier motion. 

7 . Sketch a figure similar to Fig. 3.5 for the majority- and minority-carrier flow of an npn transis- 
tor. Describe the resulting carrier motion. 

8. Which of the transistor currents is always the largest? Which is always the smallest? Which 
two currents are relatively close in magnitude? 

9 . If the emitter current of a transistor is 8 mA and I B is 1/100 of I c , determine the levels of I c and I B . 

3.4 Common-Base Configuration 

10 . From memory, sketch the transistor symbol for a pnp and an npn transistor, and then insert the 
conventional flow direction for each current. 

11 . Using the characteristics of Fig. 3.7, determine V BE at I E = 5 mA for V CB = U 10, and 20 V. Is 
it reasonable to assume on an approximate basis that V CB has only a slight effect on the rela- 
tionship between V BE and I E 1 



12. a. Determine the average ac resistance for the characteristics of Fig. 3. 10b. 

b. For networks in which the magnitude of the resistive elements is typically in kilohms, is the 
approximation of Fig. 3.10c a valid one [based on the results of part (a)]? 

13. a. Using the characteristics of Fig. 3.8, determine the resulting collector current if I F = 3.5 mA 

and V CB = 10 V. 

b. Repeat part (a) for I E = 3.5 mA and V CB = 20 V. 

c. How have the changes in V CB affected the resulting level of 7 C ? 

d. On an approximate basis, how are I E and I c related based on the results above? 

14. a. Using the characteristics of Figs. 3.7 and 3.8, determine I c if V EB = 5 V and V BE = 0.7 V. 

b. Determine V BE if I c = 5 mA and V EB = 15 V. 

c. Repeat part (b) using the characteristics of Fig. 3.10b. 

d. Repeat part (b) using the characteristics of Fig. 3.10c. 

e. Compare the solutions for \ BE for parts (b) through (d). Can the difference be ignored if 
voltage levels greater than a few volts are typically encountered? 

15. a. Given an a dc of 0.998, determine I c if I E = 4 mA. 

b. Determine a dc if I E = 2.8 mA, I c = 2.75 mA and I CB0 = 0.1 /jlA. 

16. From memory only, sketch the common-base BJT transistor configuration (for npn and pnp) 
and indicate the polarity of the applied bias and resulting current directions. 

3.5 Common-Emitter Configuration 

17. Define I CB0 and Iceo- How are they different? How are they related? Are they typically close 
in magnitude? 

18. Using the characteristics of Fig. 3.13: 

a. Find the value of I c corresponding to V BE = +750 mV and V CE = +4 V. 

b. Find the value of V CE and V BE corresponding to I c = 3.5 mA and I B = 30 p,A. 

*19. a. For the common-emitter characteristics of Fig. 3.13, find the dc beta at an operating point 
of Vce = 6 V and I c = 2 mA. 

b. Find the value of a corresponding to this operating point. 

c. At V CE = +6 V, find the corresponding value of I CE o - 

d. Calculate the approximate value of I CB0 using the dc beta value obtained in part (a). 

*20. a. Using the characteristics of Fig. 3.13a, determine Iceo at Vce — 10 V. 

b. Determine /3 dc at I B = 10 pi A and V CE = 10 V. 

c. Using the (3 dc determined in part (b), calculate I EB o- 

21. a. Using the characteristics of Fig. 3.13a, determine /3 dc at I B = 60 p,A and V CE = 4 V. 

b. Repeat part (a) at I B = 30 p,A and V CE = 7 V. 

c. Repeat part (a) at I B = 10 pc A and V CE = 10 V. 

d. Reviewing the results of parts (a) through (c), does the value of (3 dc change from point to point 
on the characteristics? Where were the higher values found? Can you develop any general con- 
clusions about the value of (3 dc on a set of characteristics such as those provided in Fig. 3.13a? 

*22. a. Using the characteristics of Fig. 3.13a, determine /3 ac at I B = 60 pi A and V CE = 4 V. 

b. Repeat part (a) at I B = 30 piA and V CE = 7 V. 

c. Repeat part (a) at I B = 10 pi A and V CE = 10 V. 

d. Reviewing the results of parts (a) through (c), does the value of /3 ac change from point to 
point on the characteristics? Where are the high values located? Can you develop any gen- 
eral conclusions about the value of /3 ac on a set of collector characteristics? 

e. The chosen points in this exercise are the same as those employed in Problem 21. If Prob- 
lem 21 was performed, compare the levels of /3 dc and /3 ac for each point and comment on 
the trend in magnitude for each quantity. 

23. Using the characteristics of Fig. 3.13a, determine /3 dc at I B = 25 pi A and V CE = 10 V. Then 
calculate a dc and the resulting level of I E . (Use the level of I c determined by I c = /3 dc I B .) 

24. a. Given that a dc = 0.980, determine the corresponding value of / 3 dc . 

b. Given p dc = 120, determine the corresponding value of a. 

c. Given that p dc =120 and I c = 2.0 mA, find I E and I B . 

25. From memory only, sketch the common-emitter configuration (for npn and pnp) and insert the 
proper biasing arrangement with the resulting current directions for I B , I c , and I E . 

3.6 Common-Collector Configuration 

26. An input voltage of 2 V rms (measured from base to ground) is applied to the circuit of Fig. 3.21. 
Assuming that the emitter voltage follows the base voltage exactly and that V be (rms) = 0.1 V, 
calculate the circuit voltage amplification (A v = V 0 /V() and emitter current for R E = 1 kfl. 



27. For a transistor having the characteristics of Fig. 3.13, sketch the input and output characteris- 
tics of the common-collector configuration. 

3.7 Limits of Operation 

28. Determine the region of operation for a transistor having the characteristics of Fig. 3.13 if 
I c = 6 mA, BV C eo = 15 V, and P c — 35 mW. 

^max '-'max 

29. Determine the region of operation for a transistor having the characteristics of Fig. 3.8 if 
I c =1 mA, BV C bo = 20 V, and P c = 42 mW. 

^max 7 7 ^max 

3.8 Transistor Specification Sheet 

30. Referring to Fig. 3.23, determine the temperature range for the device in degrees Fahrenheit. 

31. Using the information provided in Fig. 3.23 regarding Fz) max , VcE max > ?c max and Vc£ sat , sketch the 
boundaries of operation for the device. 

32. Based on the data of Fig. 3.23, what is the expected value of I CE0 using the average value of /3 dc ? 

33. How does the range of h FE (Fig. 3.23c, normalized from h EE = 100) compare with the range 
of hf e (Fig. 3.23b) for the range of I c from 0.1 to 10 mA? 

34. Using the characteristics of Fig. 3.23d, determine whether the input capacitance in the common- 
base configuration increases or decreases with increasing levels of reverse-bias potential. Can 
you explain why? 

*35. Using the characteristics of Fig. 3.23b, determine how much the level of hj e has changed from 
its value at 1 mA to its value at 10 mA. Note that the vertical scale is a log scale that may require 
reference to Section 1 1.2. Is the change one that should be considered in a design situation? 

*36. Using the characteristics of Fig. 3.23c, determine the level of /3 dc at I c = 10 mA at the three 
levels of temperature appearing in the figure. Is the change significant for the specified tem- 
perature range? Is it an element to be concerned about in the design process? 

3.9 Transistor Testing 

37. a. Using the characteristics of Fig. 3.24, determine /3 ac at I c = 14 mA and V CE = 3 V. 

b. Determine /3 dc at I c = 1 mA and V EE = 8 V. 

c. Determine /3 ac at I c = 14 mA and V CE = 3 V. 

d. Determine /3 dc at I c = 1 mA and V CE = 8 V. 

e. How does the level of /3 ac and /3 dc compare in each region? 

f. Is the approximation /3 dc = /3 ac a valid one for this set of characteristics? 




19999 



DC Biasing— BJTs 




CHAPTER OBJECTIVES ^ 

Be able to determine the dc levels for the variety of important BJT configurations. 
Understand how to measure the important voltage levels of a BJT transistor configura- 
tion and use them to determine whether the network is operating properly. 

Become aware of the saturation and cutoff conditions of a BJT network and the 
expected voltage and current levels established by each condition. 

Be able to perform a load-line analysis of the most common BJT configurations. 

• Become acquainted with the design process for BJT amplifiers. 

• Understand the basic operation of transistor switching networks. 

Begin to understand the troubleshooting process as applied to BJT configurations. 
Develop a sense for the stability factors of a BJT configuration and how they affect its 
operation due to changes in specific characteristics and environmental changes. 



4.1 INTRODUCTION ^ 

The analysis or design of a transistor amplifier requires a knowledge of both the dc and the 
ac response of the system. Too often it is assumed that the transistor is a magical device 
that can raise the level of the applied ac input without the assistance of an external energy 
source. In actuality, 

any increase in ac voltage , current , or power is the result of a transfer of energy from 
the applied dc supplies. 

The analysis or design of any electronic amplifier therefore has two components: a dc and 
an ac portion. Fortunately, the superposition theorem is applicable, and the investigation of 
the dc conditions can be totally separated from the ac response. However, one must keep in 
mind that during the design or synthesis stage the choice of parameters for the required dc 
levels will affect the ac response, and vice versa. 

The dc level of operation of a transistor is controlled by a number of factors, includ- 
ing the range of possible operating points on the device characteristics. In Section 4.2 
we specify the range for the bipolar junction transistor (BJT) amplifier. Once the desired 
dc current and voltage levels have been defined, a network must be constructed that will 
establish the desired operating point. A number of these networks are analyzed in this 
chapter. Each design will also determine the stability of the system, that is, how sensitive 
the system is to temperature variations, another topic to be investigated in a later section 
of this chapter. 




160 




OPERATING POINT 161 



Although a number of networks are analyzed in this chapter, there is an underlying 
similarity in the analysis of each configuration due to the recurring use of the following 
important basic relationships for a transistor: 



V be = 0.7 V 



( 4 . 1 ) 



I E = (I 3 + 1 )h = Ic 



( 4 . 2 ) 



Ic = PI B 



( 4 . 3 ) 



In fact, once the analysis of the first few networks is clearly understood, the path toward 
the solution of the networks to follow will begin to become quite apparent. In most instances 
the base current I B is the first quantity to be determined. Once I B is known, the relationships 
of Eqs. (4.1) through (4.3) can be applied to find the remaining quantities of interest. The 
similarities in analysis will be immediately obvious as we progress through the chapter. 
The equations for I B are so similar for a number of configurations that one equation can be 
derived from another simply by dropping or adding a term or two. The primary function of 
this chapter is to develop a level of familiarity with the BJT transistor that would permit a 
dc analysis of any system that might employ the BJT amplifier. 



4.2 OPERATING POINT ^ 

The term biasing appearing in the title of this chapter is an all-inclusive term for the appli- 
cation of dc voltages to establish a fixed level of current and voltage. For transistor ampli- 
fiers the resulting dc current and voltage establish an operating point on the characteristics 
that define the region that will be employed for amplification of the applied signal. Because 
the operating point is a fixed point on the characteristics, it is also called the quiescent 
point (abbreviated g-point). By definition, quiescent means quiet, still, inactive. Figure 4.1 
shows a general output device characteristic with four operating points indicated. The 




FIG. 4.1 

Various operating points within the limits of operation of a transistor. 



162 DC BIASING— BJTs 



biasing circuit can be designed to set the device operation at any of these points or others 
within the active region. The maximum ratings are indicated on the characteristics of Fig. 
4.1 by a horizontal line for the maximum collector current I r and a vertical line at the 

J '-'max 

maximum collector-to-emitter voltage VcE max • The maximum power constraint is defined 
by the curve Pc max i n the same figure. At the lower end of the scales are the cutoff region, 
defined by I B < 0 /xA, and the saturation region, defined by V C e — Fc£ sat - 

The BJT device could be biased to operate outside these maximum limits, but the 
result of such operation would be either a considerable shortening of the lifetime of 
the device or destruction of the device. Confining ourselves to the active region, we 
can select many different operating areas or points. The chosen Q-point often depends 
on the intended use of the circuit. Still, we can consider some differences among the 
various points shown in Fig. 4.1 to present some basic ideas about the operating point 
and, thereby, the bias circuit. 

If no bias were used, the device would initially be completely off, resulting in a Q- 
point at A — namely, zero current through the device (and zero voltage across it). Because 
it is necessary to bias a device so that it can respond to the entire range of an input signal, 
point A would not be suitable. For point B, if a signal is applied to the circuit, the device 
will vary in current and voltage from the operating point, allowing the device to react to 
(and possibly amplify) both the positive and negative excursions of the input signal. If 
the input signal is properly chosen, the voltage and current of the device will vary, but not 
enough to drive the device into cutoff or saturation. Point C would allow some positive 
and negative variation of the output signal, but the peak-to-peak value would be limited 
by the proximity of V CE = 0 V and I c — 0 mA. Operating at point C also raises some 
concern about the nonlinearities introduced by the fact that the spacing between I B curves 
is rapidly changing in this region. In general, it is preferable to operate where the gain 
of the device is fairly constant (or linear) to ensure that the amplification over the entire 
swing of input signal is the same. Point B is a region of more linear spacing and therefore 
more linear operation, as shown in Fig. 4.1. Point D sets the device operating point near 
the maximum voltage and power level. The output voltage swing in the positive direction 
is thus limited if the maximum voltage is not to be exceeded. Point B therefore seems the 
best operating point in terms of linear gain and largest possible voltage and current swing. 
This is usually the desired condition for small-signal amplifiers (Chapter 5) but not the 
case necessarily for power amplifiers, which will be considered in Chapter 12. In this 
discussion, we will be concentrating primarily on biasing the transistor for small-signal 
amplification operation. 

One other very important biasing factor must be considered. Having selected and 
biased the BJT at a desired operating point, we must also take the effect of temperature 
into account. Temperature causes the device parameters such as the transistor current 
gain (/3 ac ) and the transistor leakage current (Jceo ) t0 change. Higher temperatures result 
in increased leakage currents in the device, thereby changing the operating condition set 
by the biasing network. The result is that the network design must also provide a degree 
of temperature stability so that temperature changes result in minimum changes in the 
operating point. This maintenance of the operating point can be specified by a stability 
factor S, which indicates the degree of change in operating point due to a temperature 
variation. A highly stable circuit is desirable, and the stability of a few basic bias circuits 
will be compared. 

For the BJT to be biased in its linear or active operating region the following must be true: 

1. The base-emitter junction must be forward-biased (p-region voltage more positive), 
with a resulting forward-bias voltage of about 0.6 V to 0.7 V. 

2. The base-collector junction must be reverse-biased (n-region more positive), with 
the reverse-bias voltage being any value within the maximum limits of the device. 

[Note that for forward bias the voltage across the p-n junction is /positive, whereas for 
reverse bias it is opposite (reverse) with ^-positive.] 

Operation in the cutoff, saturation, and linear regions of the BJT characteristic are pro- 
vided as follows: 

1. Linear-region operation: 

Base-emitter junction forward-biased 
Base-collector junction reverse-biased 



2. Cutoff-region operation: 

Base-emitter junction reverse-biased 
Base-collector junction reverse-biased 

3. Saturation-region operation: 

Base-emitter junction forward-biased 
Base-collector junction forward-biased 

4.5 FIXED-BIAS CONFIGURATION ^ 

The fixed-bias circuit of Fig. 4.2 is the simplest transistor dc bias configuration. Even 
though the network employs an npn transistor, the equations and calculations apply equally 
well to a pnp transistor configuration merely by changing all current directions and voltage 
polarities. The current directions of Fig. 4.2 are the actual current directions, and the volt- 
ages are defined by the standard double- sub script notation. For the dc analysis the network 
can be isolated from the indicated ac levels by replacing the capacitors with an open-circuit 
equivalent because the reactance of a capacitor is a function of the applied frequency. For 
dc, / = 0 Hz, and X c = VW/C = 1 / 2 / 7t(0 )C = 00 12. In addition, the dc supply V cc can 
be separated into two supplies (for analysis purposes only) as shown in Fig. 4.3 to permit a 
separation of input and output circuits. It also reduces the linkage between the two to the 
base current I B . The separation is certainly valid, as we note in Fig. 4.3 that V C c is con- 
nected directly to R B and R c just as in Fig. 4.2. 



FIXED-BIAS 163 
CONFIGURATION 




ac 

output 

signal 




FIG. 4.3 

DC equivalent of Fig. 4.2. 



Forward Bias of Base-Emitter 



Consider first the base-emitter circuit loop of Fig. 4.4. Writing Kirchhoff’ s voltage equa- 
tion in the clockwise direction for the loop, we obtain 

+ Vcc — IbRb ~ Vbe = 0 

Note the polarity of the voltage drop across R B as established by the indicated direction of 
I B . Solving the equation for the current I B results in the following: 



_ Vcc Vbe 
Rb 



( 4 . 4 ) 



Equation (4.4) is certainly not a difficult one to remember if one simply keeps in mind 
that the base current is the current through R B and by Ohm’s law that current is the voltage 
across R B divided by the resistance R B . The voltage across R B is the applied voltage V C c 
at one end less the drop across the base-to-emitter junction ( V BE ;). In addition, because the 
supply voltage Vcc an d the base-emitter voltage V BE are constants, the selection of a base 
resistor R B sets the level of base current for the operating point. 




164 DC BIASING— BJTs 




Collector-Emitter Loop 

The collector-emitter section of the network appears in Fig. 4.5 with the indicated direc- 
tion of current I E and the resulting polarity across R E - The magnitude of the collector cur- 
rent is related directly to I B through 




( 4 . 5 ) 



It is interesting to note that because the base current is controlled by the level of R B and 
Ic is related to I B by a constant /3, the magnitude of I E is not a function of the resistance 
Rc- Changing R c to any level will not affect the level of I B or I c as long as we remain in 
the active region of the device. However, as we shall see, the level of Rc will determine the 
magnitude of Vce, which is an important parameter. 

Applying Kirchhoff ’ s voltage law in the clockwise direction around the indicated closed 
loop of Fig. 4.5 results in the following: 

Vce + IcRc ~ Vcc = 0 



and 



Vce ~ Vcc ~ We 



( 4 . 6 ) 



which states that the voltage across the collector-emitter region of a transistor in the fixed- 
bias configuration is the supply voltage less the drop across Rc- 

As a brief review of single- and double- subscript notation recall that 



Vce =V C -V E 



( 4 . 7 ) 



where Vce is the voltage from collector to emitter and Vq and V E are the voltages from col- 
lector and emitter to ground, respectively. In this case, since V E = 0 V, we have 



Fce = Vc 



( 4 . 8 ) 




FIG. 4.6 

Measuring V CE and Ve- 



in addition, because 



V BE =v B -v E 



( 4 . 9 ) 



and V E = 0V, then 

V BE = V B 



( 4 . 10 ) 



Keep in mind that voltage levels such as V EE are determined by placing the positive lead 
(normally red) of the voltmeter at the collector terminal with the negative lead (normally 
black) at the emitter terminal as shown in Fig. 4.6. V E is the voltage from collector to ground 
and is measured as shown in the same figure. In this case the two readings are identical, but 
in the networks to follow the two can be quite different. Clearly understanding the differ- 
ence between the two measurements can prove to be quite important in the troubleshooting 
of transistor networks. 



EXAMPLE 4.1 Determine the following for the fixed-bias configuration of Fig. 4.7. 
a. I Bq and I Cq . 
b- Vceq- 

c. V B and V c . 

d. V BC - 



Solution: 

a. Eq. (4.4): 
Eq. (4.5): 






Vcc Vbe 
Rb 



12 V - 0.7 V 
240 m 



47.08 iulA 



PI BQ = (50)(47.08 ii A) = 2.35 mA 




FIXED-BIAS 

CONFIGURATION 



165 




ac 

output 



b. Eq. (4.6): Vce q ~ Vcc Ic^c 

= 12 V - (2.35 mA)(2.2 kfl) 

= 6.83 V 

c. V B = V BE = 0.7 V 
V c = Vce = 6.83 V 

d. Using double- subscript notation yields 

V BC = V B - V c = 0.7 V - 6.83 V 

= -6.13 V 

with the negative sign revealing that the junction is re versed-biased, as it should be for 
linear amplification. 



Transistor Saturation 

The term saturation is applied to any system where levels have reached their maximum values. 
A saturated sponge is one that cannot hold another drop of water. For a transistor operating in 
the saturation region, the current is a maximum value for the particular design. Change the 
design and the corresponding saturation level may rise or drop. Of course, the highest saturation 
level is defined by the maximum collector current as provided by the specification sheet. 

Saturation conditions are normally avoided because the base-collector junction is no 
longer reverse-biased and the output amplified signal will be distorted. An operating point 
in the saturation region is depicted in Fig. 4.8a. Note that it is in a region where the char- 
acteristic curves join and the collector- to-emitter voltage is at or below V C e sat - In addition, 
the collector current is relatively high on the characteristics. 





FIG. 4.8 

Saturation regions: (a) actual; (b) approximate. 



166 DC BIASING— BJTs 




FIG. 4.9 

Determining Iq . 



If we approximate the curves of Fig. 4.8a by those appearing in Fig. 4.8b, a quick, direct 
method for determining the saturation level becomes apparent. In Fig. 4.8b, the current is 
relatively high, and the voltage V CE is assumed to be 0 V. Applying Ohm’s law, we can 
determine the resistance between collector and emitter terminals as follows: 



) 



r ce ~ 



VcE 

Ic 



OV 

Ic 



= on 



Applying the results to the network schematic results in the configuration of Fig. 4.9. 

For the future, therefore, if there were an immediate need to know the approximate 
maximum collector current (saturation level) for a particular design, simply insert a short- 
circuit equivalent between collector and emitter of the transistor and calculate the resulting 
collector current. In short, set Vqe = 0 V. For the fixed-bias configuration of Fig. 4.10, the 
short circuit has been applied, causing the voltage across Rq to be the applied voltage Vqc • 
The resulting saturation current for the fixed-bias configuration is 



= Vcc 

sat Rq 



( 4 . 11 ) 




FIG. 4.10 

Determining Ic sat for the fixed-bias 
configuration. 



Once Iq is known, we have some idea of the maximum possible collector current for the 
chosen design and the level to stay below if we expect linear amplification. 



EXAMPLE 4.2 Determine the saturation level for the network of Fig. 4.7. 



Solution: 



= Vcc = 12 V 
R c 2.2 kfl 



5.45 mA 



The design of Example 4.1 resulted in I Cq = 2.35 mA, which is far from the saturation 
level and about one-half the maximum value for the design. 

Load-Line Analysis 

Recall that the load-line solution for a diode network was found by superimposing the actual 
diode characteristics of the diode on a plot of the network equation involving the same network 
variables. The intersection of the two plots defined the actual operating conditions for the net- 
work. It is referred to as load-line analysis because the load (network resistors) of the network 
defined the slope of the straight line connecting the points defined by the network parameters. 

The same approach can be applied to BJT networks. The characteristics of the BJT are 
superimposed on a plot of the network equation defined by the same axis parameters. The 
load resistor R c for the fixed-bias configuration will define the slope of the network equa- 
tion and the resulting intersection between the two plots. The smaller the load resistance, the 





FIG. 4.1 1 

Load-line analysis: (a) the network; (b) the device characteristics. 



steeper the slope of the network load line. The network of Fig. 4.1 la establishes an output 
equation that relates the variables I c and Vqe in the following manner: 



Vce ~ Vcc Wc 



( 4 . 12 ) 



The output characteristics of the transistor also relate the same two variables Ic and Vqe as 
shown in Fig. 4.1 lb. 

The device characteristics of Ic versus Vce are provided in Fig. 4.11b. We must now 
superimpose the straight line defined by Eq. (4.12) on the characteristics. The most direct 
method of plotting Eq. (4.12) on the output characteristics is to use the fact that a straight line 
is defined by two points. If we choose Ic to be 0 mA, we are specifying the horizontal axis as 
the line on which one point is located. By substituting Ic = 0 mA into Eq. (4. 12), we find that 

Vce = Vcc ~ (QWc 



and 



Vce ~ 



Vcc I 



7 C =0 mA 



( 4 . 13 ) 



defining one point for the straight line as shown in Fig. 4.12. 




FIG. 4.12 

Fixed-bias load line. 



167 






168 DC BIASING— BJTs 



If we now choose V CE to be 0 V, which establishes the vertical axis as the line on which 
the second point will be defined, we find that I c is determined by the following equation: 

0 — Vcc ~ IcRc 



and 



Ic 



Vcc 

Rc 



V CE = OV 



( 4 . 14 ) 



as appearing on Fig. 4.12. 

By joining the two points defined by Eqs. (4.13) and (4.14), we can draw the straight 
line established by Eq. (4.12). The resulting line on the graph of Fig. 4.12 is called the load 
line because it is defined by the load resistor R c . By solving for the resulting level of I B , we 
can establish the actual g-point as shown in Fig. 4.12. 

If the level of I B is changed by varying the value of R B , the g-point moves up or down 
the load line as shown in Fig. 4.13 for increasing values of I B . If V cc is held fixed and R c 
increased, the load line will shift as shown in Fig. 4.14. If 1 B is held fixed, the g-point will 
move as shown in the same figure. If R c is fixed and Vqc decreased, the load line shifts as 
shown in Fig. 4.15. 



/C 

c 




V C E 



FIG. 4.13 

Movement of the Q-point with increasing level of 1 B . 




Effect of an increasing level ofR c on the load line 
and the Q-point. 




FIG. 4.15 

Effect of lower values ofVcc on the load line and the Q-point. 



EXAMPLE 4.3 Given the load line of Fig. 4.16 and the defined g-point, determine the 
required values of R c , and R B for a fixed-bias configuration. 



EMITTER-BIAS 169 
CONFIGURATION 




Solution: From Fig. 4. 1 6, 

Vce = Vcc = 20 V at I c = 0 mA 
Vcc 



and 



and 



/ c = ^atV CE = 0V 

K c 

Vcc 20 V 

R c = = = 2 kll 

I c 10 mA 

T _ V C c V BE 

h ~ R, 

V_ ££ -V M= 20V-a7V = 772tfi 
I B 25 /jlA 



4.4 EMITTER-BIAS CONFIGURATION ^ 

The dc bias network of Fig. 4.17 contains an emitter resistor to improve the stability 
level over that of the fixed-bias configuration. The more stable a configuration, the less 
its response will change due to undesireable changes in temperature and parameter 




FIG. 4.17 

BJT bias circuit with emitter resistor. 



170 DC BIASING— BJTs 




FIG. 4.18 

DC equivalent of Fig. 4.17. 




FIG. 4.19 

Base-emitter loop. 




FIG. 4.20 

Network derived from Eq. (4.17). 




FIG. 4.21 

Reflected impedance level of R E . 



variations. The improved stability will be demonstrated through a numerical example 
later in the section. The analysis will be performed by first examining the base-emitter 
loop and then using the results to investigate the collector-emitter loop. The dc equiva- 
lent of Fig. 4.17 appears in Fig 4.18 with a separation of the source to create an input 
and output section. 



Base-Emitter Loop 



The base-emitter loop of the network of Fig. 4.18 can be redrawn as shown in Fig. 4.19. 
Writing Kirchhoff s voltage law around the indicated loop in the clockwise direction 
results in the following equation: 

+ V CC - I b R b — V BE — I e R e = 0 (4.15) 

Recall from Chapter 3 that 

h= 03 + l )i B (4.16) 

Substituting for I E in Eq. (4.15) results in 

Vcc ~ ~ V BE ~ (P + 1)1 b^e — 0 

Grouping terms then provides the following: 

-I b (R b + 08 + 1 )R e ) + Vcc - Vbe = 0 
Multiplying through by (—1), we have 

I b (R b + 08 + 1 )R e ) ~ V cc +V BE = 0 
with Ib(Rb + (/3 + 1 )R e ) = Vcc ~ V BE 

and solving for I B gives 



Vcc ~ Vbe 
Rb + (P + 1 We 



(4.17) 



Note that the only difference between this equation for I B and that obtained for the fixed- 
bias configuration is the term (/3 + 1 )R E . 

There is an interesting result that can be derived from Eq. (4.17) if the equation is used to 
sketch a series network that would result in the same equation. Such is the case for the net- 
work of Fig. 4.20. Solving for the current I B results in the same equation as obtained above. 
Note that aside from the base-to-emitter voltage Vbe> the resistor R E is reflected back to the 
input base circuit by a factor (/3 + 1). In other words, the emitter resistor, which is part of 
the collector-emitter loop, “appears as” (/3 + 1 )R E in the base-emitter loop. Because /3 is 
typically 50 or more, the emitter resistor appears to be a great deal larger in the base circuit. 
In general, therefore, for the configuration of Fig. 4.21, 



Ri = 08 + 1 )R e 



(4.18) 



Equation (4.18) will prove useful in the analysis to follow. In fact, it provides a fairly 
easy way to remember Eq. (4.17). Using Ohm’s law, we know that the current through a 
system is the voltage divided by the resistance of the circuit. For the base-emitter circuit 
the net voltage is Vcc ~ V BE . The resistance levels are R B plus R E reflected by (/3 + 1). 
The result is Eq. (4.17). 



Collector-Emitter Loop 

The collector-emitter loop appears in Fig. 4.22. Writing Kirchhoff s voltage law for the 
indicated loop in the clockwise direction results in 

+IeRe + V CE + Ic^c ~ V C c = 0 
Substituting I E = I c and grouping terms gives 

Vce ~ Vcc + IdRc + Re) = 0 



and 



Vce ~ Vcc ~ Ic(Rc + Re) 



(4.19) 



The single- subscript voltage V E is the voltage from emitter to ground and is deter- 
mined by 



EMITTER-BIAS 171 
CONFIGURATION 



V E ~ 



( 4 . 20 ) 



whereas the voltage from collector to ground can be determined from 

V CE =Vc~V E 



and 



Vc — Vce + Ve 



( 4 . 21 ) 



or 



V c — Vce ~ I C R C 



( 4 . 22 ) 



The voltage at the base with respect to ground can be determined using Fig. 4.18 



V E ~ Vqc 



( 4 . 23 ) 




or 



Vb — V be + V E 



( 4 . 24 ) 



EXAMPLE 4.4 For the emitter-bias network of Fig. 4.23, determine: 



a. I B . 

b. I c . 

c. V C e- 

d. V c - 

e. V E . 
f- V B . 
g- Vfic- 



+20 V 




Emitter- stabilized bias circuit for Example 4.4. 



Solution: 



a. Eq. (4.17): 



b. I c = P h 



Vcc ~ Vbe = 20 V - 0.7 V 

R b + (j8 + 1 )R e 430 kfl + (51)(1 kH) 



19.3 V 
481 kfl 



40.1 fiA 



= (50)(40.1 i±A) 

= 2.01mA 



172 DC BIASING— BJTs 



c. Eq. (4.19): V C £ = V C c " Wc + Re) 

= 20 V - (2.01 mA)(2 kll + 1 kft) = 20 V - 6.03 V 

= 13.97 V 

d. Vc — Vcc ~ IcRc 

= 20 V - (2.01mA)(2kU) = 20 V - 4.02 V 
= 15.98 V 

e. V E — Vc ~ Vce 

= 15.98 V - 13.97 V 

= 2.01 V 

or V E = I e R e = I c R E 

= (2.01 mA)(l kfl) 

= 2.01 V 

f • V B = V BE + V E 

= 0.7 V + 2.01 V 

= 2.71 V 

g- Vbc = v B ~ Vc 

= 2.71V - 15.98 V 
= — 13.27 V (reverse-biased as required) 



Improved Bias Stability 

The addition of the emitter resistor to the dc bias of the BJT provides improved stability, 
that is, the dc bias currents and voltages remain closer to where they were set by the circuit 
when outside conditions, such as temperature and transistor beta, change. Although a 
mathematical analysis is provided in Section 4.12, some comparison of the improvement 
can be obtained as demonstrated by Example 4.5. 



EXAMPLE 4.5 Prepare a table and compare the bias voltage and currents of the circuits of 
Fig. 4.7 and Fig. 4.23 for the given value of /3 = 50 and for a new value of (3 = 100. Com- 
pare the changes in I c and V EE for the same increase in /3. 

Solution: Using the results calculated in Example 4.1 and then repeating for a value of 
13 = 100 yields the following: 



Effect of (3 variation on the response of the 
fixed-bias configuration of Fig. 4.7. 



p 


/b(M) 


I c {mA) 


v a B(V) 


50 


47.08 


2.35 


6.83 


100 


47.08 


4.71 


1.64 



The BJT collector current is seen to change by 100% due to the 100% change in the value 
of 13. The value of I B is the same, and V EE decreased by 76%. 

Using the results calculated in Example 4.4 and then repeating for a value of (3 = 100, 
we have the following: 



Effect off variation on the response of the 
emitter-bias configuration of Fig. 4.23. 



p 


I B ( fiA ) 


I c (mA) 


V CE (V) 


50 


40.1 


2.01 


13.97 


100 


36.3 


3.63 


9.11 



Now the BJT collector current increases by about 81% due to the 100% increase in (3. 
Notice that I B decreased, helping maintain the value of I c — or at least reducing the overall 
change in I c due to the change in /3. The change in Vqe has dropped to about 35%. The 
network of Fig. 4.23 is therefore more stable than that of Fig. 4.7 for the same change in /3. 



Saturation Level 



The collector saturation level or maximum collector current for an emitter-bias design can 
be determined using the same approach applied to the fixed-bias configuration: Apply a 
short circuit between the collector-emitter terminals as shown in Fig. 4.24 and calculate 
the resulting collector current. For Fig. 4.24 



= Vcc 
Rc + R e 



( 4 . 25 ) 



The addition of the emitter resistor reduces the collector saturation level below that 
obtained with a fixed-bias configuration using the same collector resistor. 



EXAMPLE 4.6 Determine the saturation current for the network of Example 4.4. 



Solution: 

/ = ^CC 

Csat R c + R e 

_ 20 V _ 20 V 

~ 2m + ~ 3kn 

= 6.67 mA 



which is about three times the level of Ic Q for Example 4.4. 



Load-Line Analysis 

The load-line analysis of the emitter-bias network is only slightly different from that 
encountered for the fixed-bias configuration. The level of I B as determined by Eq. (4.17) 
defines the level of I B on the characteristics of Fig. 4.25 (denoted I Bq ). 

The collector-emitter loop equation that defines the load line is 

Vce ~ Vcc ~ Ic(Rc + Re) 




EMITTER-BIAS 173 
CONFIGURATION 




FIG. 4.24 

Determining Ic sat for the emitter- 
stabilized bias circuit. 



FIG. 4.25 

Load line for the emitter-bias configuration. 



174 DC BIASING— BJTs 



Choosing I c = 0 mA gives 



Vce ~ Vcc |/ c =0mA 



( 4 . 26 ) 



as obtained for the fixed-bias configuration. Choosing Vqe = 0 V gives 



j _ Vcc 




C Rc V Re 


> 

0 

II 

1 



( 4 . 27 ) 



as shown in Fig. 4.25. Different levels of I Bq will, of course, move the Q-point up or down 
the load line. 



EXAMPLE 4.7 

a. Draw the load line for the network of Fig. 4.26a on the characteristics for the transistor 
appearing in Fig. 4.26b. 

b. For a 2-point at the intersection of the load line with a base current of 15 /ulA , find the 
values of 1 Cq and V CEq - 

c. Determine the dc beta at the 2-point. 

d. Using the beta for the network determined in part c, calculate the required value of R B 
and suggest a possible standard value. 



V rr = 18 V 





Solution: 

a. Two points on the characteristics are required to draw the load line 

Vcc 18 V 18 V 



At V CE = 0 V: I c = 

ct c R c + R e 2.2 kO + 1.1 kD 

At I c = 0 mA: V CE = V cc = 18 V 

The resulting load line appears in Fig. 4.27. 

b. From the characteristics of Fig. 4.27 we find 

= 7 .5\J Cq = 3.3 mA 

c. The resulting dc beta is: 



3.3 kD 



= 5.45 mA 



P = -T^ = 



3.3 mA 
15 iiA 



= 220 




VOLTAGE-DIVIDER BIAS 175 
CONFIGURATION 



d. Applying Eq. 4 . 1 7 : 

h = 

and 15 jm A = 



Vcc ~ V; 



BE 



18 V - 0.7 V 



R b + 08 + 1)/^ R b + (220 + 1)(1.1 kO) 
17.3 V 17.3 V 



+ (221)(1.1 kO) + 243.1 kfl 
so that (15 M)(^) + (15/iA)(243.1kn) = 17.3 V 
and (15 /ulA)(R b ) = 17.3 V - 3.65 V = 13.65 V 
13.65 V 



resulting in R B + 



15 M 



910 ka 



4.5 VOLTAGE-DIVIDER BIAS CONFIGURATION ^ 

In the previous bias configurations the bias current I c and voltage Vce q were a func- 
tion of the current gain /3 of the transistor. However, because /3 is temperature sensi- 
tive, especially for silicon transistors, and the actual value of beta is usually not well 
defined, it would be desirable to develop a bias circuit that is less dependent on, or in 
fact is independent of, the transistor beta. The voltage-divider bias configuration of 
Fig. 4.28 is such a network. If analyzed on an exact basis, the sensitivity to changes in 
beta is quite small. If the circuit parameters are properly chosen, the resulting levels of 
I Cq and Vce q can be almost totally independent of beta. Recall from previous discus- 
sions that a Q-point is defined by a fixed level of I c and Vce q as shown in Fig. 4.29. 
The level of I Bq will change with the change in beta, but the operating point on the 
characteristics defined by I Cq and Vqe q can remain fixed if the proper circuit parame- 
ters are employed. 

As noted earlier, there are two methods that can be applied to analyze the voltage-divider 
configuration. The reason for the choice of names for this configuration will become obvi- 
ous in the analysis to follow. The first to be demonstrated is the exact method , which can be 
applied to any voltage-divider configuration. The second is referred to as the approximate 
method and can be applied only if specific conditions are satisfied. The approximate ap- 
proach permits a more direct analysis with a savings in time and energy. It is also particu- 
larly helpful in the design mode to be described in a later section. All in all, the approximate 
approach can be applied to the majority of situations and therefore should be examined with 
the same interest as the exact method. 



176 DC BIASING— BJTs 



Vcc 





FIG. 4.29 

Defining the Q-pointfor the voltage-divider bias 
configuration. 




Exact Analysis 

For the dc analysis the network of Fig. 4.28 can be redrawn as shown in Fig. 4.30. The 
input side of the network can then be redrawn as shown in Fig. 4.31 for the dc analysis. 
The Thevenin equivalent network for the network to the left of the base terminal can then 
be found in the following manner: 



^Th The voltage source is replaced by a short-circuit equivalent as shown in Fig. 4.32: 



^Th ~ ^lll^2 



( 4 . 28 ) 



FIG. 4.30 

DC components of the voltage - 
divider configuration. 



f T h The voltage source V cc is returned to the network and the open-circuit Thevenin 
voltage of Fig. 4.33 determined as follows: 

Applying the voltage-divider rule gives 




-Th 






^2 VCC 



( 4 . 29 ) 



The Thevenin network is then redrawn as shown in Fig. 4.34, and I Bq can be determined 
by first applying Kirchhoff’s voltage law in the clockwise direction for the loop indicated: 

F’xh — IbR Th — VbE — IrRe = 0 
Substituting I E = (/3 + 1 )I B and solving for I B yields 



/ r — 



^Th - V; 



BE 



Rjh + 08 + 1 We 



( 4 . 30 ) 



Redrawing the input side of the 
network of Fig. 4.28. 




Although Eq. (4.30) initially appears to be different from those developed earlier, note 
that the numerator is again a difference of two voltage levels and the denominator is the base 
resistance plus the emitter resistor reflected by (/3 + 1) — certainly very similar to Eq. (4. 17). 

Once I B is known, the remaining quantities of the network can be found in the same 
manner as developed for the emitter-bias configuration. That is, 



Vce ~ Vcc Ic(Rc + Re) 



( 4 . 31 ) 



FIG. 4.32 

Determining Rj h- 



which is exactly the same as Eq. (4.19). The remaining equations for V E , V c , and V B are 
also the same as obtained for the emitter-bias configuration. 




EXAMPLE 4.8 Determine the dc bias voltage V CE and the current I c for the voltage- 
divider configuration of Fig. 4.35. 



Solution: Eq. (4.28): 



^Th ~ ^lll^2 

_ (39 kD)(3.9kD) 
~~ 39 kll + 3.9 kO 



R-iYcc 

Eq. (4.29): E Th = 

4 7 111 R x + R 2 

(3.9 klf )(22 V) 

_ 39kD + 3.9 kD 



3.55 kfl 



2 V 



Eq. (4.30): 



j _ ^Th ~ VbE 

R Th + (/3 + 1 )R e 

_ 2 V - 0.7 V _ 1.3 V 

~~ 3.55 kO + (101)(1.5 kO) ~~ 3.55 kD + 151.5 kO 
= 8.38 /lA 

Ic = Ph 

= (100)(8.38 tiA) 

= 0.84 mA 



+22 v 




VOLTAGE-DIVIDER BIAS 177 
CONFIGURATION 



AAA 





+ 

Err h 



FIG. 4.33 

Determining Ej h- 




Inserting the Thevenin equivalent 
circuit. 



Eq. (4.31): V CE = V cc ~ I C (R C + Re) 

= 22 V - (0.84mA)(10kft + 1.5 kll) 
= 22 V - 9.66 V 

= 12.34 V 



Approximate Analysis 

The input section of the voltage-divider configuration can be represented by the network of 
Fig. 4.36. The resistance R t is the equivalent resistance between base and ground for the 
transistor with an emitter resistor R E . Recall from Section 4.4 [Eq. (4.18)] that the reflected 
resistance between base and emitter is defined by R t = (/3 + 1 )R E . If R[ is much larger 
than the resistance R 2 , the current I B will be much smaller than / 2 (current always seeks the 
path of least resistance) and / 2 will be approximately equal to I\. If we accept the approxi- 
mation that I B is essentially 0 A compared to I\ or / 2 , then I\ = / 2 , and R\ and R 2 can be 
considered series elements. The voltage across R 2 , which is actually the base voltage, can be 



178 DC BIASING— BJTs 



+ 





(/l=/ 2 ) 



FIG. 4.36 

Partial-bias circuit for calculating the approximate base 
voltage V B . 



determined using the voltage-divider rule (hence the name for the configuration). That is, 



V B = 



KiVcc 
R\ + R 2 



( 4 . 32 ) 



Because R t = (/3 + 1 )R E = f3R E the condition that will define whether the approxi- 
mate approach can be applied is 



/ 3R e > \0R 2 



( 4 . 33 ) 



In other words, if /3 times the value of R E is at least 10 times the value of R 2 , the approximate 
approach can be applied with a high degree of accuracy. 

Once V E is determined, the level of V E can be calculated from 



V E =V B ~ V BE 



and the emitter current can be determined from 



and 



Ie ~r* 



] C Q = h 



( 4 . 34 ) 



( 4 . 35 ) 



( 4 . 36 ) 



The collector-to-emitter voltage is determined by 



but because I E = 7 C , 



Vce ~ Vcc IcRc Ie^e 



VcEq ~ Vcc IdRc + Re) 



( 4 . 37 ) 



Note in the sequence of calculations from Eq. (4.33) through Eq. (4.37) that /3 does not 
appear and I B was not calculated. The g-point (as determined by I Cq and VcEq) i s therefore 
independent of the value of /3 . 



EXAMPLE 4.9 Repeat the analysis of Fig. 4.35 using the approximate technique, and 
compare solutions for l c and Vce q - 

Solution: Testing: 

I3R e > 10R 2 

(100X1.5 kid) > 10(3.9 kO) 

150 k. Q > 39 k.Q (satisfied) 



^2 VcC 



VOLTAGE-DIVIDER BIAS 
CONFIGURATION 



179 



Eq. (4.32): 



V R = 



R\ + R 2 
(3.9 kH)(22 V) 
~~ 39 kO + 3.9 m 
= 2 V 



Note that the level of V B is the same as E Th determined in Example 4.7. Essentially, 
therefore, the primary difference between the exact and approximate techniques is the 
effect of Rjh in the exact analysis that separates E Th and V B . 

Eq. (4.34): V E = V B - V BE 

= 2 V - 0.7 V 



= 1.3 V 



_ Ve _ 1.3 V 
Icq = Ie ~ Rr ~ i. 5 kft 



= 0.867 mA 



compared to 0.84 mA with the exact analysis. Finally, 



Vce q ~ Vcc ~ IdRc + Re) 

= 22 V - (0.867 mA)(10kV + 1.5 kO) 
= 22 V - 9.97 V 

= 12.03 V 



versus 12.34 V obtained in Example 4.8. 

The results for I c and V CEq are certainly close, and considering the actual variation in 
parameter values, one can certainly be considered as accurate as the other. The larger the 
level of R t compared to R 2 , the closer is the approximate to the exact solution. Example 
4.11 will compare solutions at a level well below the condition established by Eq. (4.33). 



EXAMPLE 4. 1 0 Repeat the exact analysis of Example 4.8 if /3 is reduced to 50, and com- 
pare solutions for I Cq and Vce q - 

Solution: This example is not a comparison of exact versus approximate methods, but a test- 
ing of how much the g-point will move if the level of [3 is cut in half. R Th and E Th are the same: 

R Th = 3.55kI2, £ Th = 2V 

j _ ^Th VbE 

B ~ R Th + (13+ 1 )Re 

2 V — 0.7 V _ 1.3 V 

~ 3.55 kfl + (51X1.5 kO) _ 3.55 kO + 76.5 kO 
= 16.24 /a A 

Ic Q = Ph 

= (50)(16.24 fiA) 

= 0.81 mA 

Vce q — Vcc ~ IciRc + Re) 

= 22 V - (0.81mA)(10kH + 1.5 kO) 

= 12.69 V 
Tabulating the results, we have: 



Effect of /3 variation on the response of the 
voltage-divider configuration of Fig. 4.35. 



p 


!c a (mA) 


Vce q (V) 


100 


0.84 mA 


12.34 V 


50 


0.81 mA 


12.69 V 



The results clearly show the relative insensitivity of the circuit to the change in (3. Even though 
13 is drastically cut in half, from 100 to 50, the levels of I Eq and Vce q are essentially the same. 



180 DC BIAS I N G— BJTs Important Note: Looking back on the results for the fixed-bias configuration, we find the cur- 

rent decreased from 4.71 mA to 2.35 mA when beta dropped from 100 to 50. For the voltage- 
divider configuration, the same change in beta only resulted in a change in current from 
0.84 mA to 0.81 mA. Even more noticeable is the change in Vce q for the fixed-bias configuration. 
Dropping beta from 100 to 50 resulted in an increase in voltage from 1.64 to 6.83 V (a change of 
over 300%). For the voltage-divider configuration, the increase in voltage was only from 12.34 V 
to 12.69 V, which is a change of less than 3%. In summary, therefore, changing beta by 50% 
resulted in a change in an important network parameter of over 300% for the fixed-bias configura- 
tion and less than 3% for the voltage-divider configuration — a significant difference. 



El MV IE 4.11 Determine the levels of Iq q and Vce q for the voltage-divider configura- 
tion of Fig. 4.37 using the exact and approximate techniques and compare solutions. In this 
case, the conditions of Eq. (4.33) will not be satisfied and the results will reveal the differ- 
ence in solution if the criterion of Eq. (4.33) is ignored. 



18 V 




Solution: Exact analysis: 

Eq. (4.33): 

2= 10tf 2 

(50)(1.2 kO) > 10(22 kD) 

60 kfl it 220 kfl ( not satisfied) 

R Th = R\ ||/? 2 = 82 kH || 22 kD = 17.35 kD 

R 2 V cc 22 kfl(18 V) 

£ — — = — = 3 8 1 V 

lh R x + R 2 82kI2 + 22kI2 

_ ffrh ~ Vbe _ 3.81V - 0.7 V _ 3.11V 

B ~ Rjh + (j8 + 1 )R e ~ 17.35 kO + (5 1)(1 .2 kfl) _ 78.55 kO 

Ic Q = Ph = (50X39.6 ijlA) = 1.98 mA 

Vceq = Vcc ~ Ic(Rc + Re) 

= 18 V - (1.98 mA)(5.6 kfl + 1.2 kO) 

= 4.54 V 



Approximate analysis: 



V B = 


Eh - 


= 3.81 V 




V E = 


v B ~ 


V BE = 3.81 V - 


0.7 V = 3.11 






V E _ 3.11 V _ 




Ir„ = 


I /. — 




2.59 mA 






R e ~ 1.2 kO ” 




II 

a 


Vcc ' 


_ Ic(Rc + Re) 




= 


18 V 


- (2.59 mA)(5.6 


m + 1.2 kO) 


= 


3.88 1 


V 





39.6 ju,A 



Tabulating the results, we have: 



COLLECTOR FEEDBACK 181 
CONFIGURATION 



Comparing the exact and approximate approaches. 





h: Q (mA) 


Vce q (T > 


Exact 


1.98 


4.54 


Approximate 


2.59 


3.88 



The results reveal the difference between exact and approximate solutions. I Eq is about 
30% greater with the approximate solution, whereas Vce q * s about 10% less. The results 
are notably different in magnitude, but even though (3R E is only about three times larger 
than R 2 , the results are still relatively close to each other. For the future, however, our 
analysis will be dictated by Eq. (4.33) to ensure a close similarity between exact and 
approximate solutions. 



Transistor Saturation 



The output collector-emitter circuit for the voltage-divider configuration has the same 
appearance as the emitter-biased circuit analyzed in Section 4.4. The resulting equation for 
the saturation current (when V CE is set to 0 V on the schematic) is therefore the same as 
obtained for the emitter-biased configuration. That is, 



Ir ... = Ir 



Vcc 

Rc + r e 



( 4 . 38 ) 



Load-Line Analysis 

The similarities with the output circuit of the emitter-biased configuration result in the 
same intersections for the load line of the voltage-divider configuration. The load line will 
therefore have the same appearance as that of Fig. 4.25, with 



and 



j _ V cc 




C ^c + Re 


> 

0 
II 

1 



( 4 . 39 ) 



VCE ~ 



Vcc I 



7 C =0 mA 



( 4 . 40 ) 



The level of I B is of course determined by a different equation for the voltage-divider bias 
and the emitter-bias configurations. 



4.6 COLLECTOR FEEDBACK CONFIGURATION ^ 

An improved level of stability can also be obtained by introducing a feedback path from 
collector to base as shown in Fig. 4.38. Although the g-point is not totally independent of 
beta (even under approximate conditions), the sensitivity to changes in beta or temperature 
variations is normally less than encountered for the fixed-bias or emitter-biased configura- 
tions. The analysis will again be performed by first analyzing the base-emitter loop, with 
the results then applied to the collector-emitter loop. 

Base-Emitter Loop 

Figure 4.39 shows the base-emitter loop for the voltage feedback configuration. Writing 
Kirchhoff’s voltage law around the indicated loop in the clockwise direction will result in 

Vcc ~ IcRc ~ ~ V BE - I e R e = 0 

It is important to note that the current through R c is not I c , but I E (where I E = Ic + h)- 
However, the level of I c and I E far exceeds the usual level of I B , and the approximation 
Ic = Ic is normally employed. Substituting I E = I c = /3I B and I E = I c results in 

Vcc ~ PhRc ~ ~ V BE - pi B R E = 0 



182 DC BIASING— BJTs 




FIG. 4.40 

Collector-emitter loop for the 
network of Fig. 4.38. 




FIG. 4.38 

DC bias circuit with voltage feedback. 




Base-emitter loop for the network of Fig. 4.38. 



Gathering terms, we have 

Vcc ~ V be ~ PIb(Rc + Re) ~ Ib^f = 0 
and solving for I B yields 




( 4 . 41 ) 



The result is quite interesting in that the format is very similar to equations for I B ob- 
tained for earlier configurations. The numerator is again the difference of available voltage 
levels, whereas the denominator is the base resistance plus the collector and emitter resis- 
tors reflected by beta. In general, therefore, the feedback path results in a reflection of the 
resistance Rc back to the input circuit, much like the reflection of R E . 

In general, the equation for I B has the following format, which can be compared with the 
result for the fixed-bias and emitter-bias configurations. 

_ V' 

Ib ~ R f + pR' 

For the fixed-bias configuration /3R' does not exist. For the emitter-bias setup (with 
P + 1 = P), R’ = R e . 

Because Ic = /3/ B , 

_ pr _ V 
Ic ° ~ R f + PR' ~ «f , 

P 



In general, the larger R' is compared with 



Rp 

P’ 



the more accurate the approximation that 



r 

R' 



The result is an equation absent of /3, which would be very stable for variations in /3. 
Because R' is typically larger for the voltage-feedback configuration than for the emitter- 
bias configuration, the sensitivity to variations in beta is less. Of course, R' is 0 O for the 
fixed-bias configuration and is therefore quite sensitive to variations in beta. 



Collector-Emitter Loop 

The collector-emitter loop for the network of Fig. 4.38 is provided in Fig. 4.40. Applying 
Kirchhoff’ s voltage law around the indicated loop in the clockwise direction results in 

Ie^e + Vce + IcRc ~ Vcc = 0 



COLLECTOR FEEDBACK 183 
CONFIGURATION 



Because /£ = I c and I E = I c , we have 

Ic(Rc + — Vcc = 0 



and 



Vce ~ Vcc ~ IdRc + Re) 



( 4 . 42 ) 



which is exactly as obtained for the emitter-bias and voltage-divider bias configurations. 



EXAMPLE 4.12 Determine the quiescent levels of *ca and V C e q for the network of Fig. 
4.41. 



10V 




FIG. 4.41 

Network for Example 4.12. 



Solution: 



Eq. (4.41): 



Vcc ~ Vbe 
R f + (3(Rc + Re) 

10 V - 0.7 V 

250 kO + (90)(4.7kD + 1.2 kD) 
9.3 V _ 9.3 V 
250 kO + 531 kO _ 781 kO 



= 11.91 /iA 



Ic Q = Ph = (90X11.91 /xA) 

= 1.07 mA 



Vceq ~ Vcc ~ Ic(Rc + Re) 

= 10 V - (1.07 mA)(4.7 kD + 1.2 kO) 
= 10 V - 6.31V 

= 3.69 V 



EXAMPLE 4.13 Repeat Example 4.12 using a beta of 135 (50% greater than in Example 
4.12). 

Solution: It is important to note in the solution for I B in Example 4.12 that the second 
term in the denominator of the equation is much larger than the first. Recall in a recent 
discussion that the larger this second term is compared to the first, the less is the sensitivity 
to changes in beta. In this example, the level of beta is increased by 50%, which will 
increase the magnitude of this second term even more compared to the first. It is more 
important to note in these examples, however, that once the second term is relatively large 
compared to the first, the sensitivity to changes in beta is significantly less. 



184 DC BIASING— BJTs 



Solving for I B gives 



j. _ Vcc Vbe 
B ~ Rb + J8(tf c + Re) 

10 V - 0.7 V 

~~ 250 kfl + (135X4.7 kn + 1.2 kfl) 

_ 9.3 V _ 9.3 V 

~~ 250 kll + 796.5 kfl ~~ 1046.5 kfl 
= 8.89 i±A 

and I Cq = PI B 

= (135)(8.89 M) 

= 1.2 mA 

and ^cEq = Vcc ~ + Re) 

= 10 V - (1.2 mA)(4.7 kfl + 1.2 kfl) 

= 10 V - 7.08 V 

= 2.92 V 

Even though the level of /3 increased 50%, the level of I Cq only increased 12.1%, whereas 
the level of Vce q decreased about 20.9%. If the network were a fixed-bias design, a 50% 
increase in /3 would have resulted in a 50% increase in I Cq and a dramatic change in the 
location of the Q-point. 



E il LE LI 4 Determine the dc level of I B and Vc for the network of Fig. 4.42. 



18V 




Solution: In this case, the base resistance for the dc analysis is composed of two resistors 
with a capacitor connected from their junction to ground. For the dc mode, the capacitor 
assumes the open-circuit equivalence, and R B = R Fl + R Fr 
Solving for I B gives 

j _ Vcc ~ Vbe 

B ~ R b + I3(R c + R e ) 

18 V - 0.7 V 

~ (91 kfl + 110 kfl) + (75)(3.3 kfl + 0.51 kfl) 

_ 17.3 V _ 17.3 V 

~ 201 kfl + 285.75 kfl _ 486.75 kfl 

= 35.5 /x A 



COLLECTOR FEEDBACK 185 
CONFIGURATION 



lc = Ph 

= (75)(35.5 ilA) 

= 2.66 mA 

V c — Vcc ~ IcRc — Vcc ~ We 
= 18 V - (2.66mA)(3.3kH) 

= 18 V - 8.78 V 

= 9.22 V 



Saturation Conditions 



Using the approximation Iq = I c , we find that the equation for the saturation current is the 
same as obtained for the voltage-divider and emitter-bias configurations. That is, 



Vcc 

Rc + Re 



( 4 . 43 ) 



Load-Line Analysis 

Continuing with the approximation I’ c = I c results in the same load line defined for the 
voltage-divider and emitter-biased configurations. The level of I Bq is defined by the chosen 
bias configuration. 



EXAMPLE 1.1 5 Given the network of Fig. 4.43 and the BJT characteristics of Fig. 4.44. 

a. Draw the load line for the network on the characteristics. 

b. Determine the dc beta in the center region of the characteristics. Define the chosen 
point as the 2-point. 

c. Using the dc beta calculated in part b, find the dc value of I B . 

d. Find 1 Cq and 1 CEq . 



36 V 





FIG. 4.44 

BJT characteristics. 



Solution: 



a. The load line is drawn on Fig. 4.45 as determined by the following intersections: 



Vce ~ 

Ic = 



0 V:/ c = 
0 mA: V 



Vcc 

Rc + r e 
= V cc = 



_ 36 V 

~ 2.7 kO + 330 ft 

36 V 



11.88 mA 



186 DC BIASING— BJTs 




FIG. 4.45 

Defining the Q-pointfor the voltage-divider bias configuration of 
Fig. 4.43. 



b. The dc beta was determined using I B = 25 pi A and Vqe about 17 V. 



£ - z = 

1 Bq 



6.2 rnA 
25 pi A 



- 248 



Using Eq. 4.41: 

Vcc ~ Vbe 



In — 



36 V - 0.7 V 



and/# = 



Rb + 0(* c + r e) 
35.3 V 

510 kll + 751.44 kll 
35.3 V 



510 kn + 248(2.7 kU + 33012) 



= 28 /xA 



1.261 Mil 

d. From Fig. 4.45 the quiescent values are 
I Cq = 6.9 mA and V CEq = 15 V 



4.7 EMITTER-FOLLOWER CONFIGURATION ^ 

The previous sections introduced configurations in which the output voltage is typically 
taken off the collector terminal of the B JT. This section will examine a configuration where 
the output is taken off the emitter terminal as shown in Fig. 4.46. The configuration of Fig. 
4.46 is not the only one where the output can be taken off the emitter terminal. In fact, any of 
the configurations just described can be used so long as there is a resistor in the emitter leg. 




FIG. 4.46 

Common-collecter ( emitter-follower ) configuration. 



The dc equivalent of the network of Fig. 4.46 appears in Fig. 4.47 
Applying Kirchhoff s voltage rule to the input circuit will result in 

~h^B ~ V be ~ Ie Re + Vee = 0 

and using I E = (/3 + 1)1 B 

+ (P + 1 ¥bRe = Vee ~ V be 



so that 



Vee Vbe 
Rb + (P + 1 )R e 



( 4 . 44 ) 



For the output network, an application of Kirchhoff s voltage law will result in 

~Vce ~ h^E + V E e = 0 



and 



Vce ~ Vee ~ HRe 



( 4 . 45 ) 



COMMON-BASE 187 
CONFIGURATION 




FIG. 4.47 

dc equivalent of 
Fig. 4.46. 



EXAMPT2 1.16 Determine Vce q and Ie q f° r the network of Fig. 4.48. 




Solution: 

Eq. 4.44: 



and Eq. 4.45: 



1 r — 



V EE 



Vi 



BE 



19.3 V 



Rb + (fi + ^) R E 

20 V - 0.7 V _ 

240 kn + (90 + 1)2 kD _ 240 kD + 182 kn 
19.3 V 



422 kfl 



= 45.73 fiA 



Vce q ~ V E e h R E 

= V ee - 08 + We 

= 20 V - (90 + 1)(45.73 /xA)(2kH) 
= 20 V - 8.32 V 



= 11.68 V 

h Q = 08 + 1)/b = (91)(45.73 /xA) 

= 4.16 mA 



4.8 COMMON-BASE CONFIGURATION ^ 

The common-base configuration is unique in that the applied signal is connected to the 
emitter terminal and the base is at, or just above, ground potential. It is a fairly popular 
configuration because in the ac domain it has a very low input impedance, high output 
impedance, and good gain. 



188 DC BIASING— BJTs 



A typical common-base configuration appears in Fig. 4.49. Note that two supplies are 
used in this configuration and the base is the common terminal between the input emitter 
terminal and output collector terminal. 

The dc equivalent of the input side of Fig. 4.49 appears in Fig. 4.50. 




Ie 



+ 



v ee 






FIG. 4.50 

Input dc equivalent of 
Fig. 4.49. 



Applying Kirchhoff s voltage law will result in 

— V EE + d E R E + V BE — 0 




( 4 . 46 ) 



Applying Kirchhoff s voltage law to the entire outside perimeter of the network of Fig. 
4.51 will result in 

~V EE + h^E + Vce + I c *c ~ Vcc = 0 
and solving for V CE \ V CE = V EE + V C c ~ IeRe ~ Ic^c 
Because I E = I c 




FIG. 4.51 

Determining Vqe an d Vcb- 



Vce — V EE + fee “ Ie(Rc + Re) 



( 4 . 47 ) 



The voltage V C b of Fig. 4.51 can be found by applying Kirchhoff s voltage law to the 
output loop of Fig 4.51 to obtain: 

Vcb + d c R c — V cc = 0 

or V CB = V C c ~ d c Rc 

Using l c = I E 



we have 



Vcb ~ Vcc I C Rc 



( 4 . 48 ) 



EXAMPLE 4.17 Determine the currents I E and I B and the voltages V C e and Vqb f° r the 
common-base configuration of Fig. 4.52. 



/3 = 60 




FIG. 4.52 
Example 4.17. 



Solution: Eq. 4.46: 



Vee Vbe 



MISCELLANEOUS BIAS 
CONFIGURATIONS 



189 



Eq. 4.47: 



Eq. 4.48: 



If — 



r e 

4V - 0.7 V 



h 



1.2 kfl 
1 E 2.75 mA 



= 2.75 mA 

2.75 mA 



61 



/3 + 1 60+1 

= 45.08 /jlA 

VCE “ V EE + ^CC ~~ Ie(R C + 

= 4 V + 10 V - (2.75 mA)(2.4 kfl + 1.2 kD) 
= 14 V - (2.75 mA)(3.6 kll) 

= 14 V - 9.9 V 

= 4.1V 



Vcb ~ Vcc Ic R c — Vcc &Ib R C 
= 10 V - (60)(45.08 M)(24kI2) 
= 10 V - 6.49 V 

= 3.51 V 



4.9 MISCELLANEOUS BIAS CONFIGURATIONS ^ 

There are a number of BJT bias configurations that do not match the basic mold of those 
analyzed in the previous sections. In fact, there are variations in design that would require 
many more pages than is possible in a single publication. However, the primary purpose 
here is to emphasize those characteristics of the device that permit a dc analysis of the 
configuration and to establish a general procedure toward the desired solution. For each 
configuration discussed thus far, the first step has been the derivation of an expression for 
the base current. Once the base current is known, the collector current and voltage levels of 
the output circuit can be determined quite directly. This is not to imply that all solutions 
will take this path, but it does suggest a possible route to follow if a new configuration is 
encountered. 

The first example is simply one where the emitter resistor has been dropped from the 
voltage-feedback configuration of Fig. 4.38. The analysis is quite similar, but does require 
dropping R E from the applied equation. 



EXAMPLE i.18 For the network of Fig. 4.53: 

a. Determine I Eq and Vce q - 

b. Find V B , V E , V E , and V BE . 




190 DC BIASING— BJTs 



Solution: 



a. The absence of R E reduces the reflection of resistive levels to simply that of R c , and the 
equation for I B reduces to 

j _ Vcc ~ Vbe 

B ~ R b + pR c 

_ 20 V - 0.7 V _ 19.3 V 

~~ 680 kfl + (120)(4.7 kH) ~~ 1.244 Mil 

= 15.51 fiA 

Ic Q = Ph = (120X15.51 M) 

= 1.86 mA 



b. 



Vce q — Vcc ~ We 

= 20 V - (1.86mA)(4.7kH) 

= 11.26 V 
= y BE = o.7V 

V c = V CE = H-26 V 

V^ov 

V BC = V B ~ V c = 0.7 V - 11.26 V 

= -10.56 V 



In the next example, the applied voltage is connected to the emitter leg and R c is con- 
nected directly to ground. Initially, it appears somewhat unorthodox and quite different 
from those encountered thus far, but one application of Kirchhoff ’ s voltage law to the base 
circuit will result in the desired base current. 



EXAMPLE 4.19 Determine V c and V B for the network of Fig. 4.54. 




Solution: Applying Kirchhoff’ s voltage law in the clockwise direction for the base-emitter 
loop results in 

~h^B ~ V BE + V EE = 0 

, _ V EE - V BE 

Lb ~ p 
k b 

_ 9 V - 0.7 V 

loom 

8.3 V 

- loom 

= 83 fJtA 



and 

Substitution yields 



Ic = Ph 

= (45)(83 tiA) 

= 3.735 mA 
Vc — —Ic^c 

= -(3.735 mA)(1.2kft) 

= -4.48 V 

V B — ~ l B^B 

= -(83 il AXlOOkO) 

= -8.3 V 



MISCELLANEOUS BIAS 191 
CONFIGURATIONS 



Example 4.20 employs a split supply and will require the application of Thevenin’s 
theorem to determine the desired unknowns. 



EXAMPLE 4.20 Determine and V B for the network of Fig. 4.55. 




Solution: The Thevenin resistance and voltage are determined for the network to the left 
of the base terminal as shown in Figs. 4.56 and 4.57. 

^Th 

R Th = 8.2 m || 2.2 Ml = 1.73 m 




8.2 kU 

vw 

r " 

+ 

Vcc — 20 V 



-o B 

+ 




V ee 20 V 

I + ' 



FIG. 4.56 

Determining Rj h- 



FIG. 4.57 

Determining E Th- 



192 DC BIASING— BJTs 



_ Vcc + Vee _ 20 V + 20 V _ 40 V 

R x + R 2 ~ 8.2 kfl + 2.2 kO ~~ 10.4 kO 
= 3.85 mA 
^Th — I&2 V EE 

= (3.85 mA)(2.2 k!2) - 20 V 
= -11.53 V 



The network can then be redrawn as shown in Fig. 4.58, where the application of 
Kirchhoff s voltage law results in 

— ^Th — h]R \ \\ ~ V be ~ + Vee = 0 




FIG. 4.58 

Substituting the Thevenin equivalent circuit. 



Substituting I E = (/3 + 1 )I B gives 



and 



Vee ~ ^Th — V be ~ (P + V)I B R E ~ I B R Th = 0 
j _ Vee ~ ^Th ~ Vbe 
7? X h + (P + 1 We 
_ 20 V - 11.53 y - 0.7 V 
~ 1.73 kO + (121)(1.8 kO) 

7.77 V 

~ 219.53 m 
= 35.39 /ulA 
Ic = Ph 

= (120X35.39 M) 

= 4.25 mA 
Vc = Vcc ~ We 

= 20 V - (4.25 mA)(2.7 kO) 

= 8.53 V 

V B = ~E Th - I B R\h 

= -(11.53 V) - (35.39 /xA)(1.73kn) 

= -11.59 V 



4.10 SUMMARY TABLE 



Table 4.1 is a review of the most common single-stage BJT configurations with their 
respective equations. Note the similarities that exist between the equations for the various 
configurations. 



TABLE 4.1 

BJT Bias Configurations 



Type Configuration Pertinent Equations 




194 DC BIASING— BJTs 



4.11 DESIGN OPERATIONS 



Discussions thus far have focused on the analysis of existing networks. All the elements 
are in place, and it is simply a matter of solving for the current and voltage levels of the 
configuration. The design process is one where a current and/or voltage may be specified 
and the elements required to establish the designated levels must be determined. This syn- 
thesis process requires a clear understanding of the characteristics of the device, the basic 
equations for the network, and a firm understanding of the basic laws of circuit analysis, 
such as Ohm’s law, Kirchhoff’s voltage law, and so on. In most situations the thinking 
process is challenged to a higher degree in the design process than in the analysis sequence. 
The path toward a solution is less defined and in fact may require a number of basic 
assumptions that do not have to be made when simply analyzing a network. 

The design sequence is obviously sensitive to the components that are already specified 
and the elements to be determined. If the transistor and supplies are specified, the design 
process will simply determine the required resistors for a particular design. Once the theo- 
retical values of the resistors are determined, the nearest standard commercial values are 
normally chosen and any variations due to not using the exact resistance values are accepted 
as part of the design. This is certainly a valid approximation considering the tolerances 
normally associated with resistive elements and the transistor parameters. 

If resistive values are to be determined, one of the most powerful equations is simply 
Ohm’s law in the following form: 



( 4 . 49 ) 






V R 



unknown 



In a particular design the voltage across a resistor can often be determined from specified 
levels. If additional specifications define the current level, Eq. (4.49) can then be used to 
calculate the required resistance level. The first few examples will demonstrate how par- 
ticular elements can be determined from the design specifications. A complete design pro- 
cedure will then be introduced for two popular configurations. 



EXAMPLE 4.21 Given the device characteristics of Fig. 4.59a, determine V cc , R& and R c 
for the fixed-bias configuration of Fig. 4.59b. 



Solution: 




(a) 



(b) 



FIG. 4.59 

Example 4.21. 



From the load line 

Vcc 

Ic 

Rc 



20 V 



Vcc 

Rc 

Vcc 

Ic 



v CE =ov 

_ 20 V 
8 mA 



= 2.5 kil 



h 



VCC ~ V BE 

Rb 



Rc 



and 



with 



DESIGN OPERATIONS 



195 



_ Vcc Vbe 

h 

_ 20 V - 0.7 V 
40 ilA 

= 482.5 kil 



Standard resistor values are 

R c = 2.4 kfl 
R b = 470 kll 

Using standard resistor values gives 

I B = 41.1 /iA 

which is well within 5% of the value specified. 



19.3 V 
40 /x, A 



EXAMPLE 4.22 Given that I Cq = 2 mA and V C £ e = 10 V, determine 7?! and R c for the 
network of Fig. 4.60. 



18 V 




FIG. 4.60 

Example 4.22. 



Solution: 



and 



with 

and 



V p — I e Re = IrR 



c A f; 






(2mA)(1.2kH) = 2.4 V 
Vbe + V E = 0.7 V + 2.4 V = 3.1V 
^2 Vcc 



Ri + 7? 2 
(18 kH)(18 V) 
7?i + 18 kfl 



= 3.1V 



= 3.1V 



324 Ml = 3.17?! + 55.8 kll 
3.17?! = 268.2 kll 
268.2 kll 



7?i = 



3.1 






= 86.52 kil 



V CC ~ V c 



L c 



Eq. (4.49): 7? c = — ^ = 

7 C 

Vc = V C £ + V E = 10 V + 2.4 V = 12.4 V 
18 V - 12.4 V 



Rr = 



2 mA 



= 2.8 kil 



196 DC BIASING— BJTs 



The nearest standard commercial values to Ri are 82 kll and 91 k 12. However, using 
the series combination of standard values of 82 kll and 4.7 kll = 86.7 kll would result in 
a value very close to the design level. 




FIG. 4.61 

Example 4.23. 



EXAMPLE 4.23 The emitter-bias configuration of Fig. 4.61 has the following specifica- 
tions: I c = ^/ sat , / Cgat = 8 mA, V c — 18 V, and (3 = 110. Determine R c , R E , and 7?#. 

Solution: 



and 



and 



with 



For standard values, 



Rc 



\i c 

^ ^-sat 

C Q 



= 4mA 
V cc - V c 



Co 



28 V - 18 V 



Ir = 



4 mA 

VV:c 



= 2.5 kil 



Rc + Re 

Re 



R c + r e 
V cc 28 V 

I c 

'-'sat 



8 mA 
3.5 kft - R c 
3.5 kO - 2.5 kfl 

lkft 



= 3.5 kfl 



Ir„ — 



Ir„ — 



Co 



4 mA 



= 36.36 pi A 



j3 110 
^cc Vbe 
Rb + 03 + 1)7?£ 
^cc “ 



+ (P + V)R E — 



Rr = 



Vcc ~ Vbe 



~ 08 + 1)** 






28 V - 0.7 V 



36.36 /xA 
27.3 V 



- (1 1 1)(1 kll) 



36.36 pi A 

639.8 kfl 



- mm 



= 2.4 m 
r e = i m 
/? 5 = 620 m 



The discussion to follow will introduce one technique for designing an entire circuit 
to operate at a specified bias point. Often the manufacturer’s specification (spec) sheets 
provide information on a suggested operating point (or operating region) for a particular 
transistor. In addition, other system components connected to the given amplifier stage may 
also define the current swing, voltage swing, value of common supply voltage, and so on, 
for the design. 

In actual practice, many other factors may have to be considered that may affect the 
selection of the desired operating point. For the moment we concentrate on determining the 
component values to obtain a specified operating point. The discussion will be limited to 
the emitter-bias and voltage-divider bias configurations, although the same procedure can 
be applied to a variety of other transistor circuits. 



DESIGN OPERATIONS 



197 



Design of a Bias Circuit with an Emitter Feedback Resistor 

Consider first the design of the dc bias components of an amplifier circuit having emitter- 
resistor bias stabilization as shown in Fig. 4.62. The supply voltage and operating point 
were selected from the manufacturer’ s information on the transistor used in the amplifier. 

The selection of collector and emitter resistors cannot proceed directly from the infor- 
mation just specified. The equation that relates the voltages around the collector-emitter 
loop has two unknown quantities present — the resistors R E and R E . At this point some en- 
gineering judgment must be made, such as the level of the emitter voltage compared to the 
applied supply voltage. Recall that the need for including a resistor from emitter to ground 
was to provide a means of dc bias stabilization so that the change of collector current due 
to leakage currents in the transistor and the transistor beta would not cause a large shift in 
the operating point. The emitter resistor cannot be unreasonably large because the voltage 
across it limits the range of swing of the voltage from collector to emitter (to be noted when 
the ac response is discussed). The examples examined in this chapter reveal that the voltage 
from emitter to ground is typically around one-fourth to one-tenth of the supply voltage. 
Selecting the conservative case of one-tenth will permit calculating the emitter resistor R E 
and the resistor R c in a manner similar to the examples just completed. In the next example 
we perform a complete design of the network of Fig. 4.62 using the criteria just introduced 
for the emitter voltage. 



V rr = 20 V 




ac 

output 



Emitter- stabilized bias circuit for design consideration. 



EXAMPLE 4.24 Determine the resistor values for the network of Fig. 4.62 for the indicated 
operating point and supply voltage. 



Solution: 

V E 

Re 

Rc 



h 

Rb 



YoVcc = to( 20 V) = 2V 
V E 2 V 



to 



I E 1q 2 mA 

= Vcc - Vq? - V E 

Ic Ic 

4kil 

Ic _ 2 mA 
~p ~ 150 



lkfl 



20 V - 10 V - 2 V 
2 mA 



= 13.33 ilA 



v R 1= V cc - V be -V e _ 20V - 0.7 V - 2V 

h 

i.3 m a 



8 V 
2 mA 



h 



13.33 /jlA 



198 DC BIASING— BJTs 



Design of a Current-Gain-Stabilized (Beta-Independent) Circuit 

The circuit of Fig. 4.63 provides stabilization both for leakage and current gain (beta) 
changes. The four resistor values shown must be obtained for the specified operating point. 
Engineering judgment in selecting a value of emitter voltage Ve, as in the previous design 
consideration, leads to a direct, straightforward solution for all the resistor values. The 
design steps are all demonstrated in the next example. 



EXAMPLE 4.25 Determine the levels of R c , Re , and R 2 for the network of Fig. 4.63 

for the operating point indicated. 



Vrr=20V 




Current- gain- stabilized circuit for design considerations. 



Solution: 



V E = roVcc = ro(20V) = 2V 






v F 



Rf — _ = _ — 



2 V 
10 mA 



- 200 il 



= y Rc = Vcc - Vce - Ve = 20V - 8V - 2V 
I c I c 10 mA 

= ikn 



10V 
10 mA 



Vb = V BE + V E = 0.7 V + 2 V = 2.7 V 



The equations for the calculation of the base resistors Ri and R 2 will require a little 
thought. Using the value of base voltage calculated above and the value of the supply volt- 
age will provide one equation — but there are two unknowns, R\ and R 2 . An additional 
equation can be obtained from an understanding of the operation of these two resistors in 
providing the necessary base voltage. For the circuit to operate efficiently, it is assumed 
that the current through R\ and R 2 should be approximately equal to and much larger than 
the base current (at least 10:1). This fact and the voltage-divider equation for the base volt- 
age provide the two relationships necessary to determine the base resistors. That is, 

r 2 — ToP r e 



and 



V B = 



R 2 

R\ 3“ R 2 



v cc 



Substitution yields 

R 2 < ^(80)(0.2 kft) 

= 1.6 kft 



V B = 2.7 V = 



(1.6kfl)(20 V) 
Ri + 1.6 kfl 



and 



MULTIPLE BJT 199 
NETWORKS 



2.7/?! + 4.32 kO = 32 kft 

2.7/?! = 27.68 kft 

/?! = 10.25 kH (use 10 kH) 



4.12 MULTIPLE BJT NETWORKS ^ 

The BJT networks introduced thus far have only been single-stage configurations. This 
section will cover some of the most popular networks using multiple transistors. It will 
demonstrate how the methods introduced thus far in this chapter can be applied to net- 
works with any number of components. 

The R-C coupling of Fig. 4.64 is probably the most common. The collector output of one 
stage is fed directly into the base of the next stage using a coupling capacitor Q> The capaci- 
tor is chosen to ensure that it will block dc between the stages and act like a short circuit to 
any ac signal. The network of Fig. 4.64 has two voltage-divider stages, but the same coupling 
can be used between any combination of networks such as the fixed-bias or emitter- follower 
configurations. Substituting an open-circuit equivalent for C c and the other capacitors of the 
network will result in the two bias arrangements shown in Fig. 4.65. The methods of analysis 
introduced in this chapter can then be applied to each stage separately since one stage will not 
affect the other. Of course, the 20 V dc supply must be applied to each isolated component. 



v cc 




FIG. 4.64 

R-C coupled BJT amplifiers. 



Vcc Vcc 




200 DC BIASING— BJTs 



The Darlington configuration of Fig. 4.66 feeds the output of one stage directly into 
the input of the succeeding stage. Since the output of Fig. 4.66 is taken directly off the 
emitter terminal, you will find in the next chapter that the ac gain is very close to 1 but 
the input impedance is very high, making it attractive for use in amplifiers operating off 
sources that have a relatively high internal resistance. If a load resistor were added to 
the collector leg and the output taken off the collector terminal, the configuration would 
provide a very high gain. 



+v cc 




v cc 




For the dc analysis of Fig. 4.67 assuming a beta /3i for the first transistor and for the 
second, the base current for the second transistor is 

h 2 ~ Ie ] — (01 + 1 )h t 

and the emitter current for the second transistor is 

h 2 = (& + 1 )h 2 = (02 + 1X01 + 1)/* 

Assuming (3 » 1 for each transistor, we find the net beta for the configuration is 



0d — 0102 



( 4 . 50 ) 



which compares directly with a single-stage amplifier having a gain of /3/> 

Applying an analysis similar to that of Section 4.4 will result in the following equation 
for the base current: 

Vcc V be 1 Vbe 2 

h ' ~ ~R b + (fi D + 1 We 

Defining 



Vbe d ~ VbE\ + Vbe 2 



( 4 . 51 ) 



we have 

_ V C c Vbe d 
h ' ~ ~R b + (Po + 1 We 



( 4 . 52 ) 



The currents 



Ic 2 = h 2 ~ 0d^z?i 



( 4 . 53 ) 





and the dc voltage at the emitter terminal is 



(4.54) 



MULTIPLE BJT 201 
NETWORKS 






Ie 2 Re 



The collector voltage for this configuration is obviously equal to that of the source V. 



Vc 2 = V cc 



(4.55) 



and the voltage across the output of the transistor is 



Vce 2 = V C2 ~ V El 



and 



Vce 2 ~ Vcc Ve 2 



(4.56) 



The Cascode configuration of Fig. 4.68 ties the collector of one transistor to the emitter 
of the other. In essence it is a voltage-divider network with a common-base configuration at 
the collector. The result is a network with a high gain and a reduced Miller capacitance — a 
topic to be examined in Section 9.9. 



v cc 




V» o- 



V^o- 



♦k 



k 



c 2 

02 



v be 2 



yC, 8| 

k 



> v Ci = Ve 2 



-O V E ! 



FIG. 4.69 

DC equivalent of Fig. 4.68. 



The dc analysis is initiated by assuming the current through the bias resistors 7? 2 , and 
7?3 of Fig. 4.69 is much larger than the base current of each transistor. That is, 

h\ — Ir 2 — Ir 3 >:> h\ o r h 2 

The result is that the voltage at the base of the transistor <2i is simply determined by an 
application of the voltage-divider rule: 



V* = 



R 2 



Rl + 7?2 “E R r 



V cc 



(4.57) 



The voltage at the base of the transistor Q 2 is found in the same manner: 






(/? 2 + B 3 ) 

Rl + R 2 + R 3 VCC 



(4.58) 



202 DC BIASING— BJTs 



The emitter voltages are then determined by 



= V* - V BEl 



and 



% = V B? - V BE? 



with the emitter and collector currents determined by: 



1 c 1 = h 2 = ICi = J E t 



V Bl ~ v BEl 

Rf,, + Re 2 



( 4 . 59 ) 

( 4 . 60 ) 



( 4 . 61 ) 



The collector voltage Vc : 



V Cl = V B2 - V BE2 



and the collector voltage Vq 2 - 



Vc 2 ~ Vcc ~ Ic 2 Rc 



( 4 . 62 ) 

( 4 . 63 ) 



The current through the biasing resistors is 



h ' = Ir > = ^ ' Rl + V Rz + R 3 



( 4 . 64 ) 



and each base current is determined by 



with 



J8i 



ft 



( 4 . 65 ) 

( 4 . 66 ) 



The next multistage configuration to be introduced is the Feedback Pair of Fig. 4.70, 
which employs both an npn and pnp transistor. The result is a configuration that provides 
high gain with increased stability. 

The dc version with all the currents labeled appears in Fig. 4.71. 



v cc 




FIG. 4.70 

Feedback Pair amplifier. 



Vcc 




FIG. 4.71 

DC equivalent of Fig. 4.70. 





The base current 



and 
so that 

The collector current 
so that 



h 2 ~ I c ] ~ P\I B{ 
Ic 2 — ftih 2 



Ic 2 = h 2 ~ Pifah, 



Ic ~ h x + h 2 

— P\ I B ] + PlPlh, 

= ^(1 + P 2 )I B{ 



Ic = P1P2 I B{ 



( 4 . 67 ) 



( 4 . 68 ) 



Applying Kirchhoff’ s voltage law down from the source to ground will result in 
Vcc ~ IcRc ~ Ve Bi ~ I B] R B — 0 
or Vcc ~ Veb x ~ P\P2 I Bl Rc ~ I B] R B — 0 



and 



Vcc Veb 1 

1 R B + P1P2 R c 



( 4 . 69 ) 



The base voltage Vg is 
and 

The collector voltage V 
and 

In this case 

and 
so that 




Vc 2 — Vcc IcRc 




Vec x ~ Vc 2 V B e 2 



( 4 . 70 ) 

( 4 . 71 ) 

( 4 . 72 ) 

( 4 . 73 ) 

( 4 . 74 ) 

( 4 . 75 ) 



The last multistage configuration to be introduced is the Direct Coupled amplifier such 
as appearing in Example 4.26. Note the absence of a coupling capacitor to isolate the dc 
levels of each stage. The dc levels in one stage will directly affect the dc levels in succeed- 
ing stages. The benefit is that the coupling capacitor typically limits the low-frequency 
response of the amplifier. Without coupling capacitors, the amplifier can amplify signals of 
very low frequency — in fact down to dc. The disadvantage is that any variation in dc levels 
due to a variety of reasons in one stage can affect the dc levels in the succeeding stages of 
the amplifier. 



MULTIPLE BJT 203 
NETWORKS 



EXAMPLE 4.26 Determine the dc levels for the currents and voltages of the direct-coupled 
amplifier of Fig. 4.72. Note that it is a voltage-divider bias configuration followed by a 
common-collector configuration; one that is excellent in cases wherein the input imped- 
ance of the next stage is quite low. The common-collector amplifier is acting like a buffer 
between stages. 



204 DC BIASING— BJTs 



^cc 




FIG. 4.72 

Direct-coupled amplifier. 



Solution ; The dc equivalent of Fig. 4.72 appears as Fig. 4.73. Note that the load and 
source are no longer part of the picture. For the voltage-divider configuration, the follow- 
ing equations for the base current were developed in Section 4.5. 



with 

and 






E-X h - V; 



BE 



^Th + (fi + 1)^! 

^Th — ^1 11^2 

cc 



E Th — 



Ri + R 2 



14V 14V 




FIG. 4.73 

DC equivalent of Fig. 4. 72. 



In this case, 



R Jh = 33 kft || 10 kft = 7.67 kfl 
10kft(14V) 



^Th 



torn + 33 kn 



= 3.26 V 



and 



so that 



CURRENT MIRRORS 205 



with 



In Fig. 4.73 we find that 



3.26 V - 0.7 V 
7.67 kO + (100 + 1)2.2 Ml 
2.56 V 
229.2 kfl 

11.17 iulA 

I C] = PI Bl 

= 100 (11.17 /xA) 

= 1.12 mA 



Vb 2 ~ Vcc ~ Wc 



and 



resulting in 



Obviously, 



and 



= 14 V - (1.12mA)(6.8kft) 
= 14 V - 7.62 V 
= 6.38 V 
Ve 2 = Vb 2 V B e 2 
= 6.38 V - 0.7 V 
= 5.68 V 




_ 5.68 V 

~ 1.2 kO 

= 4.73 mA 



Vc 2 - Vcc 

= 14 V 

V C £ 2 = V C2 - 

Vce 2 = Vcc ~ Ve 2 



= 14 V f 5.68 V 

= 8.32 V 



( 4 . 76 ) 



( 4 . 77 ) 



( 4 . 78 ) 



( 4 . 79 ) 



4.15 CURRENT MIRRORS ^ 

The current mirror is a dc network in which the current through a load is controlled by a 
current at another point in the network. That is, if the controlling current is raised or low- 
ered the current through the load will change to the same level. The discussion to follow 
will demonstrate that the effectiveness of the design is dependent on the fact that the two 
transistors employed have identical characteristics. The basic configuration appears in 
Fig. 4.74. Note that the two transistors are back to back and the collector of one is con- 
nected to the base of the two transistors. 

Assume identical transistors will result in V BEl = V B e 2 an d I B] = h 2 as defined by the 
base-to-emitter characteristics of Fig. 4.75. Raise the base to emitter voltage, and the current 
of each will rise to the same value. 

Since the base to emitter voltages of the two transistors in Fig. 4.74 are in parallel, they 
must have the same voltage. The result is that I B{ = I Bl at every set base to emitter voltage. 



It is clear from Fig. 4.74 that 


h 


~ h x 


+ h 2 


and if 


E 


= h 2 




then 


h 


= h x 


+ E 



Control 



I L I C2 Control 




FIG. 4.74 

Current mirror using back-to-back BJTs. 




FIG. 4.75 

Base characteristics 
for transistor Q\ 

( and Q 2 ). 



In addition, 

but 

so 

and since /3i is typically » 2, 



^control I Cl ^C\ 21 B{ 

= 

^control = P\h x + 2/ 5l = (fix + 2)1 B] 
^control = P\^B X 



or 






1 control 



/ h 



( 4 . 80 ) 



If the control current is raised, the resulting I B{ will increase as determined by Eq. 4.80. If I Bl 
increases, the voltage V BEl must increase as dictated by the response curve of Fig. 4.75. If V BE] 
increases, then V BEl must increase by the same amount and l Bl will also increase. The result is 
that I L = c = f3I B2 will also increase to the level established by the control current. 

Referring to Fig. 4.74 we find the control current is determined by 



1 control 



Vcc ~ Vbe 

R 



( 4 . 81 ) 



revealing that for a fixed Vqc , the resistor R can be used to set the control current. 

The network also has a measure of built-in control that will try to ensure that any varia- 
tion in load current will be corrected by the configuration itself. For instance, if I E should 
try to increase for whatever reason, the base current of Q 2 will a l so increase due to the 
relationship I B2 = I 02 / P 2 — II/ P 2 • Returning to Fig. 4.101, we find that an increase in I B2 
will cause voltage V BEl to increase also. Because the base of Q 2 is connected directly to the 
collector of Q\, the voltage V EE] will increase also. This action causes the voltage across 
the control resistor R to decrease, causing I R to drop. But if I R drops, the base current I B will 
drop, causing both I Bl and l Bl to drop also. A drop in I Bl will cause the collector current and 
therefore the load current to drop also. The result, therefore, is a sensitivity to unwanted 
changes that the network will make every effort to correct. 

The entire sequence of events just described can be presented on a single line as shown 
below. Note that at one end the load current is trying to increase, and at the end of the se- 
quence the load current is forced to return to its original level. 



h t Ic 2 1 h 2 1 Vbe 2 t Vce x ! /# 2 ! /c 2 ^ 




Note 




EXAMPLE 4.27 Calculate the mirrored current I in the circuit of Fig. 4.76. 



Solution: 



Eq. (4.75): 



I = l 



control 



Vcc Vbe 

R 



12 V - 0.7 V 

1.1 m 



10.27 mA 



+12 Y 



CURRENT MIRRORS 207 




Current mirror circuit for Example 4.27. 



EXAMPLE 4.28 Calculate the current I through each of the transistor Q 2 and g 3 in the 
circuit of Fig. 4.77 . 



Solution: Since 
Substituting 

we have 



Vbe } ~ Vbe 2 ~ Vbe 3 then I Bl — I Bl 
h, = and l Bl = T with I B} = 



/, 



control 



1 _ _ 1 _ 



so I must equal k 



control 



and 



^control 



VCC ~ V; 



BE 



R 



6V - 0.7 V 
1.3 kft 



= 4.08 mA 




P 



+6 V 




Current mirror circuit for Example 4.28. 



Figure 4.78 shows another form of current mirror to provide higher output impedance 
than that of Fig. 4.74. The control current through R is 



l 



V cc ~ 2Vi 



BE 



control 



R 



I c P + 1 

Ir + — = lr 

C P 0 C 



Assuming that Q\ and Q 2 are well matched, we find that the output current I is held 
constant at 



I 1C ^control 



208 DC BIASING— BJTs 



Again we see that the output current I is a mirrored value of the current set by the fixed 
current through R. 

Figure 4.79 shows still another form of current mirror. The junction field effect transistor 
(see Chapter 6) provides a constant current set at the value of I D $s- This current is mirrored, 
resulting in a current through Q 2 of the same value: 

1 = bss 




Current mirror circuit with higher output 
impedance. 



Current mirror connection. 



4.14 CURRENT SOURCE CIRCUITS ^ 

The concept of a power supply provides the starting point in our consideration of current 
source circuits. A practical voltage source (Fig. 4.80a) is a voltage supply in series with a 
resistance. An ideal voltage source has R = 0, whereas a practical source includes some 
small resistance. A practical current source (Fig. 4.80b) is a current supply in parallel with 
a resistance. An ideal current source has R = oofl, whereas a practical current source 
includes some very large resistance. 



R 

AAA/ o o 



+ 



E 






-o 



Practical 
voltage source 



Ideal 

voltage source 




Practical 
current source 





(a) 



(b) 



FIG. 4.80 

Voltage and current sources. 

An ideal current source provides a constant current regardless of the load connected to 
it. There are many uses in electronics for a circuit providing a constant current at a very 
high impedance. Constant-current circuits can be built using bipolar devices, FET devices, 
and a combination of these components. There are circuits used in discrete form and others 
more suitable for operation in integrated circuits. 

Bipolar Transistor Constant-Current Source 



FIG. 4.81 

Discrete constant-current source. 



Bipolar transistors can be connected in a circuit that acts as a constant-current source in a 
number of ways. Figure 4.81 shows a circuit using a few resistors and an npn transistor for 



operation as a constant-current circuit. The current through I E can be determined as fol- 
lows. Assuming that the base input impedance is much larger than Ri or R 2 , we have 



and 



V* = 






Ri + R 2 
V e = V B - 



' ( — Vee) 
0.7 V 



with I E = — — ( VeE> = I c ( 4 . 82 ) 

k e 

where / ( - is the constant current provided by the circuit of Fig. 4.81. 



E II E 4.29 Calculate the constant current I in the circuit of Fig. 4.82. 

Solution: 

Ri .... 5.1 kO 






~(—Vee) 



Ri + R 2 ' 5.1 kO + 5.1 kH 

V E = V B - 0.7 V = 10 V - 0.7 V = -10.7 V 
V e -(-V ee ) -10.7 V - (-20 V) 



(-20 V) = -10 V 



I = I E = 

_ 9.3 V 

~ 2m 



Re 

= 4.65 in A 



2 kfl 



Transistor/Zener Constant-Current Source 



CURRENT SOURCE 209 
CIRCUITS 




FIG. 4.82 

Constant-current source for 
Example 4.29. 



Replacing resistor R 2 with a Zener diode, as shown in Fig. 4.83, provides an improved 
constant-current source over that of Fig. 4.81. The Zener diode results in a constant current 
calculated using the base-emitter KVL (Kirchhoff voltage loop) equation. The value of / 
can be calculated using 



If — 



Vz ~ Vbe 

Rf 



( 4 . 83 ) 



A major point to consider is that the constant current depends on the Zener diode voltage, 
which remains quite constant, and the emitter resistor R E . The voltage supply V EE has no 
effect on the value of I. 



EXAMPLE 4.30 Calculate the constant current I in the circuit of Fig. 4.84. 




FIG. 4.84 

Constant-current circuit for Example 4.30. 




FIG. 4.83 

Constant-current circuit using Zener 
diode. 



Eq. (4.83): I = 



V z - Vi 



BE 



Rf 



6.2 V - 0.7 V 

1.8 m 



= 3.06 mA ~ 3 mA 



Solution: 



210 DC BIASING— BJTs 




pnp transistor in an emitter- 
stabilized configuration. 



4.15 pup TRANSISTORS ^ 

The analysis thus far has been limited totally to npn transistors to ensure that the initial 
analysis of the basic configurations was as clear as possible and uncomplicated by switch- 
ing between types of transistors. Fortunately, the analysis of pnp transistors follows the 
same pattern established for npn transistors. The level of I B is first determined, followed by 
the application of the appropriate transistor relationships to determine the list of unknown 
quantities. In fact, the only difference between the resulting equations for a network in 
which an npn transistor has been replaced by a pnp transistor is the sign associated with 
particular quantities. 

As noted in Fig. 4.85, the double- sub script notation continues as normally defined. The 
current directions, however, have been reversed to reflect the actual conduction directions. 
Using the defined polarities of Fig. 4.85, both V BE and V CE will be negative quantities. 

Applying Kirchhoff ’ s voltage law to the base-emitter loop results in the following equa- 
tion for the network of Fig. 4.85: 

~1eRe + V be ~ + Vcc = 0 

Substituting I E = (J3 + 1 )I B and solving for I B yields 



Vcc + Vbe 
Rb + (P + IWe 



( 4 . 84 ) 



The resulting equation is the same as Eq. (4.17) except for the sign for V BE . However, in 
this case V BE = —0.7 V and the substitution of values results in the same sign for each term 
of Eq. (4.84) as Eq. (4.17). Keep in mind that the direction of I B is now defined opposite of 
that for a pnp transistor as shown in Fig. 4.85. 

For Vce Kirchhoff s voltage law is applied to the collector-emitter loop, resulting in the 
following equation: 

—IeRe + Vce ~ IcRc + fee = 0 

Substituting I E = I c gives 



Vce ~ ~Vcc + Ic(Rc + Re) 



( 4 . 85 ) 



The resulting equation has the same format as Eq. (4.19), but the sign in front of each 
term on the right of the equal sign has changed. Because V E c will be larger than the mag- 
nitude of the succeeding term, the voltage Vce will have a negative sign, as noted in an 
earlier paragraph. 



EXAMPLE 4.31 Determine Vce for the voltage-divider bias configuration of Fig. 4.86. 




FIG. 4.86 

pnp transistor in a voltage-divider bias configuration. 



Solution: Testing the condition 



PRe ^ 10^2 



TRANSISTOR SWITCHING 211 
NETWORKS 



results in 

(120)(1.1 kO) > 10(10 kli) 

132 kfl > loom (. satisfied ) 

Solving for V B , we have 

T7 _ RiVcc _ (iomx-i8V) _ 

v D — — — J, lo V 

B R x + R 2 47 kft + 10 m 

Note the similarity in format of the equation with the resulting negative voltage for V B . 
Applying Kirchhoff’ s voltage law around the base-emitter loop yields 

+v 5 - V BE - V E = 0 

and V B — V B — V BE 

Substituting values, we obtain 

V E = -3.16 V - (-0.7 V) 

= -3.16 V + 0.7 V 
= -2.46 V 



Note in the equation above that the standard single- and double-subscript notation is 
employed. For an npn transistor the equation V E = V B — V BE would be exactly the same. 
The only difference surfaces when the values are substituted. 

The current is 



Ve _ 2.46 V 

r e ~ i.i m 



2.24 mA 



For the collector-emitter loop, 

—Ie r e + Vce ~ I C R C + V C c — 0 

Substituting I E = l c and gathering terms, we have 

Vce = ~Vcc + fcC^c + R E ) 

Substituting values gives 

V CE = -18 V + (2.24 mA)(2.4 kO + 1.1 kO) 
= -18 V + 7.84 V 

= -10.16 V 



4.16 TRANSISTOR SWITCHING NETWORKS ^ 

The application of transistors is not limited solely to the amplification of signals. Through 
proper design, transistors can be used as switches for computer and control applications. 
The network of Fig. 4.87a can be employed as an inverter in computer logic circuitry. Note 
that the output voltage V c is opposite to that applied to the base or input terminal. In addi- 
tion, note the absence of a dc supply connected to the base circuit. The only dc source is 
connected to the collector or output side, and for computer applications is typically equal 
to the magnitude of the “high” side of the applied signal — in this case 5 V. The resistor R B 
will ensure that the full applied voltage of 5 V will not appear across the base-to-emitter 
junction. It will also set the I B level for the “on” condition. 

Proper design for the inversion process requires that the operating point switch from 
cutoff to saturation along the load line depicted in Fig. 4.87b. For our purposes we will 
assume that I c = I CEO = 0 mA when I B = 0 /ul A (an excellent approximation in light of 
improving construction techniques), as shown in Fig. 4.87b. In addition, we will assume 
that V C e ~ VcE sat — 0 V rather than the typical 0.1-V to 0.3-V level. 

When V[ = 5 V, the transistor will be “on” and the design must ensure that the network 
is heavily saturated by a level of I B greater than that associated with the I B curve appearing 



212 DC BIASING— BJTs 



Vcc = 5 V 






FIG. 4.87 

Transistor inverter. 



near the saturation level. In Fig. 4.87b, this requires that I B > 50 /ulA . The saturation level 
for the collector current for the circuit of Fig. 4.87a is defined by 



_ Ycc_ 
sat R c 



( 4 . 86 ) 



The level of I B in the active region just before saturation results can be approximated by 
the following equation: 

/ c 

j ^sat 

u max Q 

Pdc 

For the saturation level we must therefore ensure that the following condition is satisfied: 



h 




( 4 . 87 ) 



For the network of Fig. 4.87b, when V} = 5 V, the resulting level of l g is 
Vi - 0.7 V 5 V - 0.7 V 



Ir = 



Rb 

Vcc 



68 kfl 
5 V 



63 jx A 



Rc 



0.82 kfl 



s 6.1 mA 



and 



Testing Eq. (4.87) gives 



= 63 /iA > — = 

Pdc 



6.1 mA 
125 



TRANSISTOR SWITCHING 213 
NETWORKS 



= 48.8 fiA 



which is satisfied. Certainly, any level of I B greater than 60 /a A will pass through a Q-point 
on the load line that is very close to the vertical axis. 

For V( = 0 V, I B = 0 /mA , and because we are assuming that Iq — Iceo = 0 mA, the 
voltage drop across d c as determined by V R c = 7c^c — 0 V, resulting in V c = +5 V for 
the response indicated in Fig. 4.87a. 

In addition to its contribution to computer logic, the transistor can also be employed as a 
switch using the same extremities of the load line. At saturation, the current Iq is quite high 
and the voltage Vqe very low. The result is a resistance level between the two terminals 
determined by 



^sat 



V CE 



and is depicted in Fig. 4.88. 



lc 







r = on 



FIG. 4.88 

Saturation conditions and the resulting 
terminal resistance. 




s/ R = ooQ 

x 



FIG. 4.89 

Cutoff conditions and the resulting terminal 
resistance. 



Using a typical average value of V CE such as 0.15 V gives 



V, 



deaf 



CE 



0.15 V 



= 24.6 n 



Ir 6.1mA 

^sat 

which is a relatively low value and can be considered as approximately 0 12 when placed 
in series with resistors in the kilohm range. 

For Vi = 0 V, as shown in Fig. 4.89, the cutoff condition results in a resistance level of 
the following magnitude: 

Vcc 5 V 



R t 



cutoff 



I CEO 



0mA 



= ooil 



resulting in the open-circuit equivalence. For a typical value of Iceo = 10 P-A, the magni- 
tude of the cutoff resistance is 



R, 



Vcc 



5 V 



cutoff 



= 500 kil 



2 CEO 10 fiA 

which certainly approaches an open-circuit equivalence for many situations. 



EXAMP L32 Determined# and R c for the transistor inverter of Fig. 4.90 if I c = 10 mA. 






FIG. 4.90 

Inverter for Example 4.32. 



214 DC BIASING— BJTs 



Solution : At saturation, 

and 
so that 

At saturation, 



Ir = 

^sat 

10 mA = 



Ycc 
Rc 
10 V 



Rr 



10 V 

R c = — — r = 1 kO 



10 mA 



I R = 



Ir 

^sat 

/3 dc 



10mA 

250 



= 40 /I A 



Choosing I B = 60 fi A to ensure saturation and using 

Vi ~ 0.7 V 



we obtain 



Rr = 



Rr 



Vi~0.1V 10 V — 0.7 V 



I B 60 ii A 

Choose R b = 150 kll, which is a standard value. Then 

V t - 0.7 V 10 V — 0.7 V 



Ir — 



R 



B 



150 kn 



= 155 kll 



= 62 fxA 



and 



I B = 62 ii A > = 40 fiA 

Pdc 



Therefore, use R B = 150 kfl and R c = 1 kil. 



There are transistors that are referred to as switching transistors due to the speed with 
which they can switch from one voltage level to the other. In Fig. 3.23c the periods of time 
defined as t s , t d , t n and tf are provided versus collector current. Their impact on the speed of 
response of the collector output is defined by the collector current response of Fig. 4.91 . The 
total time required for the transistor to switch from the “off” to the “on” state is designated 
as t on and is defined by 



A i'd 



( 4 . 88 ) 



Transistor "on" Transistor "off" 

\ \ 




FIG. 4.91 

Defining the time intervals of a pulse waveform. 



with td the delay time between the changing state of the input and the beginning of a response TROUBLESHOOTING 215 

at the output. The time element t r is the rise time from 10% to 90% of the final value. TECHNIQUES 

The total time required for a transistor to switch from the “on” to the “off” state is re- 
ferred to as t Q ff and is defined by 



A)ff A tf 



( 4 . 89 ) 



where t s is the storage time and fy the fall time from 90% to 10% of the initial value. 
For the general-purpose transistor of Fig. 3.23c at Iq — 10 mA, we find that 

t« = 120 ns 





t d ~ 




t r 


and 




so that 


Am 


and 


A)ff 



— t r + td = 13 ns + 25 ns = 38 ns 



Comparing the values above with the following parameters of a BSV52L switching tran- 
sistor reveals one of the reasons for choosing a switching transistor when the need arises: 

t on = 12 ns and t 0 ff = 18 ns 



4.17 TROUBLESHOOTING TECHNIQUES ^ 

The art of troubleshooting is such a broad topic that a full range of possibilities and tech- 
niques cannot be covered in a few sections of a book. However, the practitioner should be 
aware of a few basic maneuvers and measurements that can isolate the problem area and 
possibly identify a solution. 

Quite obviously, the first step in being able to troubleshoot a network is to fully under- 
stand the behavior of the network and to have some idea of the expected voltage and current 
levels. For the transistor in the active region, the most important measurable dc level is the 
base-to-emitter voltage. 

For an “on” transistor, the voltage Vbe should be in the neighborhood of 0.7 V. 

The proper connections for measuring Vbe appear in Fig. 4.92. Note that the positive 
(red) lead is connected to the base terminal for an npn transistor and the negative (black) 
lead to the emitter terminal. Any reading totally different from the expected level of about 
0.7 V, such as 0, 4, or 12 V or a negative value, would be suspect and the device or network 
connections should be checked. For a pnp transistor, the same connections can be used, but 
a negative reading should be expected. 

A voltage level of equal importance is the collector- to-emitter voltage. Recall from the 
general characteristics of a BJT that levels of Vet: in the neighborhood of 0.3 V suggest a 
saturated device — a condition that should not exist unless it is being employed in a switch- 
ing mode. However: 

For the typical transistor amplifier in the active region, Vqe is usually about 
25% to 75% of V co 

For Vcc = 20 V, a reading of Vce of 1 V to 2 V or from 18 V to 20 V as measured in Fig. 
4.93 is certainly an uncommon result, and unless the device was knowingly designed for this 
response, the design and operation should be investigated. If Vqe = 20 V (with Vqc = 20 V) 
at least two possibilities exist — either the device (BJT) is damaged and has the characteristics 




0.7 V Si 
0.3 V Ge 
1.2 V GaAs 



Checking the dc level of Vbe- 




0.3 V = saturation 
0 V = short-circuit state 
or poor connection 
Normally a few volts 
or more 



FIG. 4.93 

Checking the dc level of Vqe- 



216 DC BIASING— BJTs 



Vcc = 20 V 




FIG. 4.94 

Effect of a poor connection or 
damaged device. 



Vcc 




FIG. 4.95 

Checking voltage levels with respect 
to ground. 



20 V 




FIG. 4.96 

Network for Example 4.33. 



of an open circuit between collector and emitter terminals or a connection in the collector- 
emitter or base-emitter circuit loop is open as shown in Fig. 4.94, establishing I c at 0 mA and 
V Rc = 0 V. In Fig. 4.94, the black lead of the voltmeter is connected to the common ground 
of the supply and the red lead to the bottom terminal of the resistor. The absence of a collector 
current and a consequent zero voltage drop across R c will result in a reading of 20 V. If the 
meter is connected between the collector terminal and ground of the B JT, the reading will be 
0 V because V cc is blocked from the active device by the open circuit. One of the most 
common errors in the laboratory is the use of the wrong resistance value for a given design. 
Imagine the impact of using a 680-12 resistor for R B rather than the design value of 680 kf2. 
For V C c = 20 V and a fixed-bias configuration, the resulting base current would be 



20 V - 0.7 V 
68012 



28.4 mA 



rather than the desired 28.4 pA — a significant difference! 

A base current of 28.4 mA would certainly place the design in a saturation region and pos- 
sibly damage the device. Because actual resistor values are often different from the nominal 
color-code value (recall the common tolerance levels for resistive elements), it is time well 
spent to measure a resistor before inserting it in the network. The result is measurements closer 
to theoretical levels and some insurance that the correct resistance value is being employed. 

There are times when frustration will develop. You check the device on a curve tracer 
or other BJT testing instrumentation and it looks good. All resistor levels seem correct, 
the connections appear solid, and the proper supply voltage has been applied — what next? 
Now the troubleshooter must strive to attain a higher level of sophistication. Could it be 
that the internal connection of a lead is faulty? How often has simply touching a lead at the 
proper point created a “make or break” situation between connections? Perhaps the supply 
was turned on and set at the proper voltage but the current-limiting knob was left in the 
zero position, preventing the proper level of current as demanded by the network design. 
Obviously, the more sophisticated the system, the broader is the range of possibilities. In 
any case, one of the most effective methods of checking the operation of a network is to 
check various voltage levels with respect to ground by hooking up the black (negative) 
lead of a voltmeter to ground and “touching” the important terminals with the red (posi- 
tive) lead. In Fig. 4.95, if the red lead is connected directly to Vco it should read Vcc v °lts 
because the network has one common ground for the supply and network parameters. At 
Vc the reading should be less, as determined by the drop across Rc , and V E should be less 
than Vc by the collector-emitter voltage Vce- The failure of any of these points to register 
what would appear to be a reasonable level may be sufficient in itself to define the faulty 
connection or element. If V Rc and V Re are reasonable values but Vce i s 0 V, the possibility 
exists that the BJT is damaged and displays a short-circuit equivalence between collector 
and emitter terminals. As noted earlier, if Vce registers a level of about 0.3 V as defined by 
Vce ~ Vc ~ Ve (the difference of the two levels as measured above), the network may be 
in saturation with a device that may or may not be defective. 

It should be somewhat obvious from the discussion above that the voltmeter section of the 
VOM or DMM is quite important in the troubleshooting process. Current levels are usually 
calculated from the voltage levels across resistors rather than “breaking” the network to insert 
the milliammeter section of a multimeter. On large schematics, specific voltage levels are pro- 
vided with respect to ground for easy checking and identification of possible problem areas. 
Of course, for the networks covered in this chapter, one must simply be aware of typical levels 
within the system as defined by the applied potential and general operation of the network. 

All in all, the troubleshooting process is a true test of your clear understanding of the 
proper behavior of a network and the ability to isolate problem areas using a few basic 
measurements with the appropriate instruments. Experience is the key, and that will come 
only with continued exposure to practical circuits. 



EXAMPLE 4.33 Based on the readings provided in Fig. 4.96, determine whether the net- 
work is operating properly and, if not, the probable cause. 

Solution: The 20 V at the collector immediately reveals that I c = 0 mA, due to an open 
circuit or a nonoperating transistor. The level of V Rb = 19.85 V also reveals that the 
transistor is “off” because the difference of Vcc — V Rb = 0.15 V is less than that required 




BIAS STABILIZATION 217 



to turn “on” the transistor and provide some voltage for V E . In fact, if we assume a short- 
circuit condition from base to emitter, we obtain the following current through R B : 



Vcc 20 V 

h R b + R e 252 kfl 



79.4 /xA 



which matches that obtained from 



h R = 



V ^L 

Rr 



19.85 V 
250 kfl 



79.4 /x A 



If the network were operating properly, the base current should be 

_ Vcc ~ Vbe _ 20 V - 0.7 V _ 19.3 V 

B ~ R B + (P + 1 )R e ~ 250 kfl + (101)(2kft) ~~ 452 kfl 



42.7 /X A 



The result, therefore, is that the transistor is in a damaged state, with a short-circuit condi- 
tion between base and emitter. 



EXAMPLE 4.34 Based on the readings appearing in Fig. 4.97, determine whether the tran- 
sistor is “on” and the network is operating properly. 

Solution: Based on the resistor values of Ri and R 2 and the magnitude of V cc , the volt- 
age V B = 4 V seems appropriate (and in fact it is). The 3.3 V at the emitter results in a 
0.7-V drop across the base-to-emitter junction of the transistor, suggesting an “on” transis- 
tor. However, the 20 V at the collector reveals that I c — 0 mA, although the connection to 
the supply must be “solid” or the 20 V would not appear at the collector of the device. Two 
possibilities exist — there can be a poor connection between R c and the collector terminal 
of the transistor or the transistor has an open base-to-collector junction. First, check the 
continuity at the collector junction using an ohm-meter, and if it is okay, check the transis- 
tor using one of the methods described in Chapter 3. 



4.18 BIAS STABILIZATION ^ 

The stability of a system is a measure of the sensitivity of a network to variations in its 
parameters. In any amplifier employing a transistor the collector current I c is sensitive to 
each of the following parameters: 

/ 3 : increases with increase in temperature 

\V B e\ : decreases about 2.5 mV per degree Celsius (°C) increase in temperature 
I co ( reverse saturation current): doubles in value for every 10°C increase in temperature 

Any or all of these factors can cause the bias point to drift from the designed point of 
operation. Table 4.2 reveals how the levels of I C o and Vbe change with increase in tempera- 
ture for a particular transistor. At room temperature (about 25 °C) I C o — 0.1 nA, whereas 
at 100°C (boiling point of water) I co is about 200 times larger, at 20 nA. For the same tem- 
perature variation, (3 increases from 50 to 80 and V BE drops from 0.65 V to 0.48 V. Recall 
that I B is quite sensitive to the level of V BE , especially for levels beyond the threshold value. 



20 V 




FIG. 4.97 

Network for Example 4.34. 



TABLE 4.2 



Variation of Silicon Transistor Parameters 
with Temperature 



T(°C) 


Ico (nA) 


P 


Vhh (V) 


-65 


0.2 X 10“ 3 


20 


0.85 


25 


0.1 


50 


0.65 


100 


20 


80 


0.48 


175 


3.3 X 10 3 


120 


0.3 



The effect of changes in leakage current (Jco) and current gain (/3) on the dc bias point 
is demonstrated by the common-emitter collector characteristics of Fig. 4.98a and b. Fig- 
ure 4.98 shows how the transistor collector characteristics change from a temperature of 




FIG. 4.98 

Shift in dc bias point (Q-point) due to change in temperature: (a) 25°C ; (b) 100°C. 



25 °C to a temperature of 100°C. Note that the significant increase in leakage current not 
only causes the curves to rise, but also causes an increase in beta, as revealed by the larger 
spacing between curves. 

An operating point may be specified by drawing the circuit dc load line on the graph 
of the collector characteristic and noting the intersection of the load line and the dc base 
current set by the input circuit. An arbitrary point is marked in Fig. 4.98a at I B = 30 pt A. 
Because the fixed-bias circuit provides a base current whose value depends approximately 
on the supply voltage and base resistor, neither of which is affected by temperature or the 
change in leakage current or beta, the same base current magnitude will exist at high tem- 
peratures as indicated on the graph of Fig. 4.98b. As the figure shows, this will result in the 
dc bias point’ s shifting to a higher collector current and a lower collector-emitter voltage 
operating point. In the extreme, the transistor could be driven into saturation. In any case, 
the new operating point may not be at all satisfactory, and considerable distortion may result 
because of the bias-point shift. A better bias circuit is one that will stabilize or maintain the 
dc bias initially set, so that the amplifier can be used in a changing-temperature environment. 



Stability Factors S{l co ), S(V BE ), and S(P) 



A stability factor S is defined for each of the parameters affecting bias stability as follows: 



Sdco) 



Sic 

SIco 



S(V BE ) = 



Sic 

S V BE 



SQ S) = 



Sic 

A/3 



( 4 . 90 ) 

( 4 . 91 ) 

( 4 . 92 ) 



218 



In each case, the delta symbol (A) signifies change in that quantity. The numerator of each 
equation is the change in collector current as established by the change in the quantity 



BIAS STABILIZATION 219 



in the denominator. For a particular configuration, if a change in I co fails to produce a 
significant change in I c , the stability factor defined by S(I C o) — A/ C /A / C( 9 will be quite 
small. In other words: 

Networks that are quite stable and relatively insensitive to temperature variations have 
low stability factors . 

In some ways it would seem more appropriate to consider the quantities defined by 
Eqs. (4.90) through (4.92) to be sensitivity factors because: 

The higher the stability factor , the more sensitive is the network to variations in that 
parameter. 

The study of stability factors requires the knowledge of differential calculus. Our pur- 
pose here, however, is to review the results of the mathematical analysis and to form an 
overall assessment of the stability factors for a few of the most popular bias configurations. 
A great deal of literature is available on this subject, and if time permits, you are encour- 
aged to read more on the subject. Our analysis will begin with the S(Jco ) l eve l f° r each 
configuration. 



Wco) 

Fixed-Bias Configuration 

For the fixed-bias configuration, the following equation results: 

Sdco ) = P 



( 4 . 93 ) 



Emitter-Bias Configuration 



For the emitter-bias configuration of Section 4.4, an analysis of the network results in 



Sdco ) 



Pd + Rb/Re) 
P + Rb/B e 



( 4 . 94 ) 



For Rb/Re » /3, Eq. (4.94) reduces to the following: 



Sdco) = P 



Rb/Re^P 



( 4 . 95 ) 



as shown on the graph of Sfco) versus Rb/Re in Fig- 4.99. 

For Rb/Re « 1, Eq. (4.94) will approach the following level (as shown in Fig. 4.99): 



Sdco) = 1 



Rb/Re^ 1 



( 4 . 96 ) 



revealing that the stability factor will approach its lowest level as R E becomes sufficiently 
large. Keep in mind, however, that good bias control normally requires that R B be greater 
than R e . The result therefore is a situation where the best stability levels are associated with 
poor design criteria. Obviously, a trade-off must occur that will satisfy both the stability and 
bias specifications. It is interesting to note in Fig. 4.99 that the lowest value of S(Ico) is b 
revealing that Iq will always increase at a rate equal to or greater than I co . 

For the range where Rb/Re ranges between 1 and (/3 + 1), the stability factor will be 
determined by 



Sdco) 



Rb 

Re 



( 4 . 97 ) 



The results reveal that the emitter-bias configuration is quite stable when the ratio Rb/Re is 
as small as possible and the least stable when the same ratio approaches /3. 

Note that the equation for the fixed-bias configuration matches the maximum value for 
the emitter-bias configuration. The result clearly reveals that the fixed-bias configuration 
has a poor stability factor and a high sensitivity to variations in I co . 



220 DC BIASING— BJTs 




FIG. 4.99 

Variation of stability factor S(I C o) with the resistor ratio Rb/Re 
for the emitter-bias configuration. 




FIG. 4.100 

Equivalent circuit for the voltage- 
divider configuration. 



Voltage-Divider Bias Configuration 



Recall from Section 4.5 the development of the Thevenin equivalent network appearing in 
Fig. 4.100, for the voltage-divider bias configuration. For the network of Fig. 4.100, the 
equation for S(Jco) is the following: 



SVco) 



i8(l + Rjh/R E ) 
P + R Th/ R E 



(4.98) 



Note the similarities with Eq. (4.94), where it was determined that S(Jco) had its low- 
est level and the network had its greatest stability when R E > R B . For Eq. (4.98), the 
corresponding condition is R E > Rj^, or Rj\ 1 /R e should be as small as possible. For the 
voltage-divider bias configuration, R Th can be much less than the corresponding R Th of 
the emitter-bias configuration and still have an effective design. 



Feedback-Bias Configuration {R E = 0(1) 

In this case, 




(4.99) 



Because the equation is similar in format to that obtained for the emitter-bias and voltage-divider 
bias configurations, the same conclusions regarding the ratio R B / R c can he applied here also. 



Physical Impact 

Equations of the type developed above often fail to provide a physical sense for why the 
networks perform as they do. We are now aware of the relative levels of stability and how 
the choice of parameters can affect the sensitivity of the network, but without the equations 
it may be difficult for us to explain in words why one network is more stable than another. 
The next few paragraphs attempt to fill this void through the use of some of the very basic 
relationships associated with each configuration. 

For the fixed-bias configuration of Fig. 4.101a, the equation for the base current is 

T _ Vcc Vbe 

lB ~ R 
K B 

with the collector current determined by 



Ic — Ph + (P + 1 )Ico 



(4.100) 



BIAS STABILIZATION 221 




Review of biasing managements and the stability factor S(Ico)- 



If Iq as defined by Eq. (4.93) should increase due to an increase in I co , there is noth- 
ing in the equation for I B that would attempt to offset this undesirable increase in current 
level (assuming V BE remains constant). In other words, the level of I E would continue 
to rise with temperature, with I B maintaining a fairly constant value — a very unstable 
situation. 

For the emitter-bias configuration of Fig. 4.101b, however, an increase in Ic due to an 
increase in l co will cause the voltage V E = I E R E = I E R E to increase. The result is a drop 
in the level of I B as determined by the following equation: 

= ( 4 . 101 ) 

Rb 



A drop in I B will have the effect of reducing the level of I c through transistor action 
and thereby offset the tendency of I c to increase due to an increase in temperature. In total, 
therefore, the configuration is such that there is a reaction to an increase in I c that will tend 
to oppose the change in bias conditions. 

The feedback configuration of Fig. 4.101c operates in much the same way as the emitter- 
bias configuration when it comes to levels of stability. If I c should increase due to an 
increase in temperature, the level of Vr will increase in the equation 



I B i — 



Vcc - Vbe - V Rc t 



R* 



( 4 . 102 ) 



and the level of I B will decrease. The result is a stabilizing effect as described for the 
emitter-bias configuration. One must be aware that the action described above does not 
happen in a step-by-step sequence. Rather, it is a simultaneous action to maintain the 
established bias conditions. In other words, the very instant I c begins to rise, the network 
will sense the change and the balancing effect described above will take place. 

The most stable of the configurations is the voltage-divider bias network of Fig. 4. 10 Id. 
If the condition (3R E » 10 R 2 is satisfied, the voltage V B will remain fairly constant for 
changing levels of I c . The base-to-emitter voltage of the configuration is determined by 
V BE = V B — V E . If Ic should increase, V E will increase as described above, and for a con- 
stant V B the voltage V BE will drop. A drop in V BE will establish a lower level of I B , which 
will try to offset the increased level of I c . 



EXAMPLE 4.35 Calculate the stability factor and the change in I c from 25 °C to 100°C for 
the transistor defined by Table 4.2 for the following emitter-bias arrangements: 

a. R b /R e = 250 (R b = 250RA 

b. R b /R e = 10 (R b = 10 R e ). 

c. R b /R e = 0.01 (R e = 100 R b ). 



222 DC BIASING— BJTs 



Solution: 



a. S(Ico) 



j3(l + R b /Re) 

ft + Rb/Re 
50(1 + 250) 
50 + 250 

41.83 



which begins to approach the level defined by ft = 50. 

The change in I c is given by 

M c = [ SQco) ] (M C o) = (41.83)(19.9 nA) 



b. S(Ico) 



M c 



c. S(Ico) 



= 0.83 [x A 

ftd + R b /R e ) 

ft + Rb/Re 
50(1 + 10) 

50 + 10 

9.17 

[S(/ C0 )](A/ C0 ) = (9.17)(19.9 nA) 

0.18 /jlA 

ft(l + R b /R e ) 

ft + R b /Re 
50(1 + 0.01) 

50 + 0.01 

1.01 



which is certainly very close to the level of 1 forecast if R b /Re « 1. 
We have 

M c = [Sdco) } (M co ) = 1.01(19.9 nA) 

= 20.1 nA 



Example 4.35 reveals how lower and lower levels of Ico f° r the modern-day BJT 
transistor have improved the stability level of the basic bias configurations. Even though 
the change in I c is considerably different in a circuit having ideal stability (S = 1) from 
one having a stability factor of 41.83, the change in I c is not that significant. For example, 
the amount of change in Ic from a dc bias current set at, say, 2 mA, would be from 2 mA 
to 2.00083 mA in the worst case, which is obviously small enough to be ignored for most 
applications. Some power transistors exhibit larger leakage currents, but for most amplifier 
circuits the lower levels of Ico have had a very positive impact on the stability question. 



S(V BE ) 



The stability factor 5(Vg£ ) ' s defined by 

S(Vhe) 



Fixed-Bias Configuration 

For the fixed-bias configuration: 



Me 



-f3 

S(V BE ) S ML 
k b 

Emitter-Bias Configuration 



For the emitter-bias configuration: 



S(V BE ) 



~We 
P + Rb/Re 



( 4 . 103 ) 



( 4 . 104 ) 



Substituting the condition /3 » Rb/Re results in the following equation for S(V BE ): 



BIAS STABILIZATION 223 





-j8 /Re 1 

p =~r e 


( 4 . 105 ) 


which shows that the larger the resistance R E , the lower is the stability factor and the more 
stable is the system. 

Voltage-Divider Configuration 

For the voltage-divider configuration: 




S(V ) - ~p /Re 


( 4 . 106 ) 


BE 13 + R Th /R E 


Feedback-Bias Configuration 

For the feedback-bias configuration: 






S(v ) - M Rc 


( 4 . 107 ) 


S(V ‘ E> - p + r b /r c 



EXAMPLE 4.36 Determine the stability factor S(V BE ) and the change in I c from 25°C to 
100°C for the transistor defined by Table 4.2 for the following bias arrangements. 

a. Fixed-bias with R B = 240 kfl and [3 = 100. 

b. Emitter-bias with R B = 240 kD, R E = 1 kD, and /3 = 100. 

c. Emitter-bias with R B = 47 k 12, R E = 4.7 kD, and (3 = 100. 



Solution: 

a. Eq. (4.103): 



S(V BE ) = 



Rb 



100 



-3 



and 



240 kO 

= - 0.417 X 10 

A/ c — [ S(V BE ) ] (AV BE ) 



= (-0.417 X 10 _3 )(0.48 V - 0.65 V) 



= (-0.417 X 10 _3 )(— 0.17 V) 

= 70.9 /jlA 

In this case, (3 = 100 and Rb/Re = 240. The condition (3 » Rb/Re i s not satisfied, 
negating the use of Eq. (4.105) and requiring the use of Eq. (4.104). 

-P/Re 



Eq. (4.104): S(V 5i? ) = 



P + Rb/Re 

-(100)/(lkH) 

_ 100 + (240 kD / 1 kD) 

= - 0.294 X 10“ 3 



- 0.1 



100 + 240 



which is about 30% less than the fixed-bias value due to the additional R E term in the 
denominator of the S(V BE ) equation. We have 

A/c = [S(V B£ )](AV B£ ) 

= (-0.294 X 10 -3 )(— 0.17 V) 

= 50 fJL A 

c. In this case, 

R b 47 kD 

13 = 100 » — = — — = 10 ( satisfied) 

R e 4.7 k 12 



224 DC BIASING— BJTs 



Eq. (4.105): 



1 



and 



S(V BE ) = 

k e 

1 

4.7 m 

= - 0.212 X 10 -3 

A I c = [S(V RE )](AV RE ) 

= (-0.212 X 10 _3 )(— 0.17 V) 

= 36.04 fiA 



In Example 4.36, the increase of 70.9 /ulA will have some impact on the level of I Eq . For 
a situation where Iq = 2 mA, the resulting collector current increases to a 3.5% increase. 

Ic Q — 2 mA + 70.9 /ulA 
= 2.0709 mA 

For the voltage-divider configuration, the level of R B will be changed to Rj ^ in Eq. 
(4.104) (as defined by Fig. 4.100). In Example 4.36, the use of R B = 47 kll is a question- 
able design. However, R T h for the voltage-divider configuration can be this level or lower 
and still maintain good design characteristics. The resulting equation for S(V BE ) for the 
feedback network will be similar to that of Eq. (4.104) with R E replaced by R E - 



m 

The last stability factor to be investigated is that of SQ3). The mathematical development is 
more complex than that encountered for S(Jco ) and S(V BE ), as suggested by some of the 
following equations. 



Fixed-Bias Configuration 

For the fixed-bias configuration 



S(P) = 



Ai 

Pi 



(4.108) 



Emitter-Bias Configuration 

For the emitter-bias configuration 



Ale 0 + Rb/Re) 
A)8 “ + R b /R e ) 



(4.109) 



The notation E and fix is used to define their values under one set of network conditions, 
whereas the notation >82 is used to define the new value of beta as established by such causes 
as temperature change, variation in /3 for the same transistor, or a change in transistors. 



EXAMPLE 4.37 Determine I Cq at a temperature of 100°C if I Cq = 2 mA at 25 °C for the 
emitter-bias configuration. Use the transistor described by Table 4.2, where f3\ = 50 and 
/3 2 — 80, and a resistance ratio R B /R E of 20. 



Solution: 

Eq. (4.109): 



S(P) = 



7 Cl (l + R b /R e ) 

P l(l +02 + R B /Re ) 
(2 X 10 _3 )(1 + 20) 
(50)(1 + 80 + 20) 



= 8.32 X 10“ 6 



42 X 10 -3 



5050 



and 



BIAS STABILIZATION 225 



A l c = [ S(fi) ] [ A/3 ] 

= (8.32 X 10“ 6 )(30) 

= 0.25 mA 

In conclusion, therefore, the collector current changed from 2 mA at room temperature to 
2.25 mA at 100°C, representing a change of 12.5%. 



Voltage-Divider Bias Configuration 

For the voltage-divider bias configuration 



/ci(l + ^Th /Re) 
+ Rjh /Re) 



Feedback-bias Configuration 

For the collector feedback-bias configuration 



Ic^Rb + Rc) 
Pi(Rb + Pi R c) 



( 4 . 110 ) 



( 4 . 111 ) 



Summary 

Now that the three stability factors of importance have been introduced, the total effect on 
the collector current can be determined using the following equation for each configuration 



A I c = SdcoWco + S(V BE ) AV be + S(/3)A/3 



( 4 . 112 ) 



The equation may initially appear quite complex, but note that each component is simply 
a stability factor for the configuration multiplied by the resulting change in a parameter 
between the temperature limits of interest. In addition, the A I c to be determined is simply 
the change in I c from the level at room temperature. 

For instance, if we examine the fixed-bias configuration, Eq. (4.78) becomes 



A Ic ~ /3A I co ~ ~~A V B e 
k b 




( 4 . 113 ) 



after substituting the stability factors as derived in this section. Let us now use Table 4.2 to 
find the change in collector current for a temperature change from 25 °C (room temperature) 
to 100°C (the boiling point of water). For this range the table reveals that 

A/co = 20 nA - 0.1 nA = 19.9 nA 
AV be = 0.48 V - 0.65 V = -0.17 V (note the sign) 
and A/3 = 80 - 50 = 30 

Starting with a collector current of 2 mA with an R B of 240 k 12, we obtain the resulting 
change in I c due to an increase in temperature of 75 °C as follows: 

M C = (50,(19.9 nA) - ^(-0.17V) + ^(30) 

= 1 julA + 35.42 (jlA + 1200 julA 
= 1.236 mA 

which is a significant change due primarily to the change in /3. The collector current has 
increased from 2 mA to 3.236 mA, but this was expected in the sense that we recognize 
from the content of this section that the fixed-bias configuration is the least stable. 

If the more stable voltage-divider configuration is employed with a ratio Rt^/Re = 2 
and R e = 4.7 kfl, then 

S(I C0 ) = 2.89, S(V BE ) = -0.2 X 10“ 3 , S(j8) = 1.445 X 10“ 6 



226 DC BIASING— BJTs 



and 



M c = (2.89)(19.9 nA) - 0.2 X 10 _J (-0.17 V) + 1.445 X 10“°(30) 
= 57.51 nA + 34/ulA + 43.4 pA 
= 0.077 mA 



The resulting collector current is 2.077 mA, or essentially 2. 1 mA, compared to the 2.0 mA 
at 25 °C. The network is obviously a great deal more stable than the fixed-bias configuration, 
as mentioned in earlier discussions. In this case, S(J3) did not override the other two factors, 
and the effects of S(V BE ) and S{I C o) were equally important. In fact, at higher temperatures, 
the effects of S(I C o) and S(V BE ) will be greater than S(J3) for the device of Table 4.2. For 
temperatures below 25 °C, I c will decrease with increasingly negative temperature levels. 

The effect of S(I co ) in the design process is becoming a lesser concern because of 
improved manufacturing techniques, which continue to lower the level of I co — Icbo • It 
should also be mentioned that for a particular transistor the variation in levels of I CBO and V BE 
from one transistor to another in a lot is almost negligible compared to the variation in beta. 
In addition, the results of the analysis above support the fact that for a good stabilized design: 

General Conclusion: 

The ratio R B /R E or R n /R E should be as small as possible with due consideration to 
all aspects of the design , including the ac response. 



Although the analysis above may have been clouded by some of the complex equations 
for some of the sensitivities, the purpose here was to develop a higher level of awareness of 
the factors that go into a good design and to be more intimate with the transistor parameters 
and their impact on the network’s performance. The analysis of the earlier sections was for 
idealized situations with nonvarying parameter values. We are now more aware of how the 
dc response of the design can vary with the parameter variations of a transistor. 

4.19 PRACTICAL APPLICATIONS ^ 

As with the diodes in Chapter 2, it would be virtually impossible to provide even a surface 
treatment of the broad areas of application of BJTs. However, a few applications are cho- 
sen here to demonstrate how different facets of the characteristics of BJTs are used to 
perform various functions. 

BIT Diode Usage and Protective Capabilities 

As you begin to scan complex networks you will often find transistors being used where 
all three terminals are not connected in the network — particularly the collector lead. In 
such cases it is most likely being used as a diode rather than a transistor. There are a num- 
ber of reasons for such use, including the fact that it is cheaper to buy a large number of 
transistors rather than a smaller bundle and then pay separately for specific diodes. Also, in 
ICs the manufacturing process may be more direct to make additional transistors that 
introduce the diode construction sequence. Two examples of its use as a diode appear in 
Fig. 4.102. In Fig. 4.102a it is being used in a simple diode network. In Fig. 4.102b it is 
being used to establish a reference level. 

Often times you will see a diode connected directly across a device as shown in Fig. 
4.103 to simply ensure that the voltage across a device or system with the polarity shown 
cannot exceed the forward bias voltage of 0.7 V. In the reverse direction if the breakdown 
strength is sufficiently high it will simply appear as an open circuit. Again, however, only 
two terminals of the BJT are being employed. 

The point to be made is that one should not assume that every BJT transistor in a network 
is being used for amplification or as a buffer between stages. The number of areas of 
application for BJTs beyond these areas is quite extensive. 



Relay Driver 

This application is in some ways a continuation of the discussion introduced for diodes 
about how the effects of inductive kick can be minimized through proper design. In Fig. 
4.104a, a transistor is used to establish the current necessary to energize the relay in the 




Vref 1 = ^ + 2V = 2.7Vo 




(b) 



FIG. 4.102 

BJT applications as a diode: (a) simple series diode circuit; (b) setting a reference level. 



collector circuit. With no input at the base of the transistor, the base current, collector cur- 
rent, and coil current are essentially 0 A, and the relay sits in the unenergized state (nor- 
mally open, NO). However, when a positive pulse is applied to the base, the transistor 
turns on, establishing sufficient current through the coil of the electromagnet to close the 
relay. Problems can now develop when the signal is removed from the base to turn off the 
transistor and deenergize the relay. Ideally, the current through the coil and the transistor 
will quickly drop to zero, the arm of the relay will be released, and the relay will simply 
remain dormant until the next “on” signal. However, we know from our basic circuit 
courses that the current through a coil cannot change instantaneously, and, in fact, the 
more quickly it changes, the greater the induced voltage across the coil as defined by 
v L = L(di L /dt). In this case, the rapidly changing current through the coil will develop a 
large voltage across the coil with the polarity shown in Fig. 4.104a, which will appear 
directly across the output of the transistor. The chances are likely that its magnitude will 
exceed the maximum ratings of the transistor, and the semiconductor device will be per- 
manently damaged. The voltage across the coil will not remain at its highest switching 
level but will oscillate as shown until its level drops to zero as the system settles down. 



PRACTICAL 227 
APPLICATIONS 



9+V 




FIG. 4.103 

Acting as a protective device. 





FIG. 4.104 

Relay driver: (a) absence of protective device; (b) with a diode across the relay coil. 



This destructive action can be subdued by placing a diode across the coil as shown in 
Fig. 4.104b. During the “on” state of the transistor, the diode is back-biased; it sits like an 
open circuit and doesn’t affect a thing. However, when the transistor turns off, the voltage 
across the coil will reverse and will forward-bias the diode, placing the diode in its “on” 
state. The current through the inductor established during the “on” state of the transistor 
can then continue to flow through the diode, eliminating the severe change in current level. 
Because the inductive current is switched to the diode almost instantaneously after the 
“off’ state is established, the diode must have a current rating to match the current through 
the inductor and the transistor when in the “on” state. Eventually, because of the resistive 




228 DC BIASING— BJTs elements in the loop, including the resistance of the coil windings and the diode, the high- 

frequency (quickly oscillating) variation in voltage level across the coil will decay to zero, 
and the system will settle down. 

Light Control 

In Fig. 4.105a, a transistor is used as a switch to control the “on” and “off’ states of the light- 
bulb in the collector branch of the network. When the switch is in the “on” position, we have 
a fixed-bias situation where the base-to-emitter voltage is at its 0.7- V level, and the base cur- 
rent is controlled by the resistor Ri and the input impedance of the transistor. The current 
through the bulb will then be beta times the base current, and the bulb will light up. A prob- 
lem can develop, however, if the bulb has not been on for a while. When a lightbulb is first 
turned on, its resistance is quite low, even though the resistance will increase rapidly the 
longer the bulb is on. This can cause a momentary high level of collector current, which 
could damage the bulb and the transistor over time. In Fig. 4.105b, for instance, the load line 
for the same network with a cold and a hot resistance for the bulb is included. Note that even 
though the base current is set by the base circuit, the intersection with the load line results in 
a higher current for the cold lightbulb. Any concern about the turn-on level can easily be cor- 
rected by inserting an additional small resistor in series with the lightbulb, as shown in Fig. 
43.105c, just to ensure a limit on the initial surge in current when the bulb is first turned on. 




(a) 




(b) 




FIG. 4.105 

Using the transistor as a switch to control the on-off states of a bulb: (a) network; (b) effect of low bulb resistance 

on collector current; (c) limiting resistor. 



Maintaining a Fixed Load Current 

If we assume that the characteristics of a transistor have the ideal appearance of Fig. 4.106a 
(constant beta throughout) a source, fairly independent of the applied load, can be constructed 
using the simple transistor configuration of Fig. 4.106b. The base current is fixed so no matter 
where the load line is, the load or collector current remains the same. In other words, the 
collector current is independent of the load in the collector circuit. However, because the 
actual characteristics are more like those in Fig. 4.106b, where beta will vary from point to 
point, and even though the base current may be fixed by the configuration, the beta will vary 
from point to point with the load intersection, and I c = I L will vary — not characteristic of 
a good current source. Recall, however, that the voltage-divider configuration resulted in a 
low level of sensitivity to beta, so perhaps if that biasing arrangement is used, the current 
source equivalent is closer to reality. In fact, that is the case. If a biasing arrangement such 
as shown in Fig. 4.107 is employed, the sensitivity to changes in operating point due to 
varying loads is much less, and the collector current will remain fairly constant for changes 
in load resistance in the collector branch. In fact, the emitter voltage is determined by 

V E = V B - 0.7 V 

with the collector or load current determined by 

V E V B - 0.7 V 



PRACTICAL 229 
APPLICATIONS 




FIG. 4.106 

Building a constant-current source assuming ideal BJT characteristics: (a) ideal characteristics; 
(b) network; (c) demonstrating why Iq remains constant. 



Using Fig. 4.107, we can describe the improved stability by examining the case where 
Iq may be trying to rise for any number of reasons. The result is that I E = Iq will also rise 
and the voltage V R = I E R E will increase. However, if we assume V B to be fixed (a good 
assumption because its level is determined by two fixed resistors and a voltage source), the 
base-to-emitter voltage V Be = V B — V Re will drop. A drop in V BE will cause I B and there- 
fore Iq (= I3I B ) to drop. The result is a situation where any tendency for I c to increase will 
be met with a network reaction that will work against the change to stabilize the system. 





LOAD I 



Network establishing a fairly constant current source 
due to its reduced sensitivity to changes in beta. 



Alarm System with a CCS 



An alarm system with a constant-current source of the type just introduced appears in Fig. 
4.108. Because /3R E = (100)(1 kkl) = 100 kfl is much greater than R h we can use the 
approximate approach and find the voltage V Rl , 



VRi = 



2kQ(16V) 

2 kll + 4.7 kO 



4.78 V 



and then the voltage across R E , 

Vr e = V Rl ~ 0.7 V = 4.78 V - 0.7 V = 4.08 V 
and finally the emitter and collector current, 



If — 



Vre _ 4.08 V 
R F ~ 1 kQ 



= 4.08 mA — 4 mA = Ir 



1 kQ 





230 DC BIASING— BJTs 



■O +16 V 




An alarm system with a constant-current source and an op-amp comparator. 



Because the collector current is the current through the circuit, the 4-mA current will 
remain fairly constant for slight variations in network loading. Note that the current passes 
through a series of sensor elements and finally into an op-amp designed to compare the 
4-mA level with the set level of 2 mA. (Although the op-amp may be a new device to you, 
it will be discussed in detail in Chapter 10 — you will not need to know the details of its 
behavior for this application.) 

The LM2900 operational amplifier of Fig. 4.108 is one of four found in the dual-in- 
line integrated circuit package appearing in Fig. 4.109a. Pins 2, 3, 4, 7, and 14 were used 



Dual-in-line package 

V+ INPUT 3+ INPUT 4+ INPUT 4 ~ OUTPUT 4 OUTPUT 3 INPUT 3“ 






FIG. 4.109 

LM2900 operational amplifier: (a) dual-in-line package (DIP); (b) components; (c) impact of low-input impedance. 



for the design of Fig. 4.108. For the sake of interest only, note in Fig. 4.109b the number 
of elements required to establish the desired terminal characteristics for the op-amp — as 
mentioned earlier, the details of its internal operation are left for another time. The 2 mA at 
terminal 3 of the op-amp is a reference current established by the 16-V source and 7? ref at 
the negative side of the op-amp input. The 2-mA current level is required as a level against 
which the 4-mA current of the network is to be compared. As long as the 4-mA current on 
the positive input to the op-amp remains constant, the op-amp will provide a “high” output 
voltage, exceeding 13.5 V, with a typical level of 14.2 V (according to the specification 
sheets for the op-amp). However, if the sensor current drops from 4 mA to a level below 
2 mA, the op-amp will respond with a “low” output voltage, typically about 0.1 V. The 
output of the op-amp will then signal the alarm circuit about the disturbance. Note from 
the above that it is not necessary for the sensor current to drop all the way down to 0 mA 
to signal the alarm circuit. Only a variation around the reference level that appears unusual 
is required — a good alarm feature. 

One very important characteristic of this particular op-amp is the low-input impedance 
as shown in Fig. 4.109c. This feature is important because one does not want alarm circuits 
reacting to every voltage spike or turbulence that comes down the line because of some 
external switching action or outside forces such as lightning. In Fig. 4.109c, for instance, 
if a high-voltage spike should appear at the input to the series configuration, most of the 
voltage will appear across the series resistor rather than the op-amp — thus preventing a false 
output and an activation of the alarm. 



Logic Gates 



In this application we will expand on the coverage of transistor switching networks in Sec- 
tion 4.15. To review, the collector-to-emitter impedance of a transistor is quite low near or 
at saturation and large near or at cutoff. For instance, the load line defines saturation as the 
point where the current is quite high and the collector-to-emitter voltage quite low as shown 



in Fig. 4.110. The resulting resistance, defined by R sat 



^C£ sat (low) . 

, is quite low and is olten 

^C sat (high) 



approximated as a short circuit. At cutoff, \ the current is relatively low and the voltage near 
its maximum value as shown in Fig. 4.1 10, resulting in a very high impedance between the 
collector and emitter terminal, which is often approximated by an open circuit. 



PRACTICAL 231 
APPLICATIONS 




FIG. 4.110 

Points of operation for a BJT logic gate. 

The above impedance levels established by “on” and “off’ transistors make it relatively 
easy to understand the operation of the logic gates of Fig. 4.111. Because there are two 
inputs to each gate, there are four possible combinations of voltages at the input to the 
transistors. A 1, or “on,” state is defined by a high voltage at the base terminal to turn the 
transistor on. A 0, or “off,” state is defined by 0 V at the base, ensuring that transistor is off. 
If both A and B of the OR gate of Fig. 4. 1 1 la have a low or 0-V input, both transistors are 
off (cutoff), and the impedance between the collector and the emitter of each transistor can 
be approximated by an open circuit. Mentally replacing both transistors by open circuits 



9 ^ 



232 DC BIASING— BJTs 



between the collector and the emitter will remove any connection between the applied 
bias of 5 V and the output. The result is zero current through each transistor and through 
the 3.3-kfl resistor. The output voltage is therefore 0 V, or “low” — a 0 state. On the other 
hand, if transistor Q \ is on and £>2 is off due to a positive voltage at the base of Q\ and 
0 V at the base of Q 2 > then the short-circuit equivalent between the collector and emitter 
for transistor Q\ can be applied, and the voltage at the output is 5 V, or “high” — a 1 state. 
Finally, if both transistors are turned on by a positive voltage applied to the base of each, 
they will both ensure that the output voltage is 5 V, or “high” — a 1 state. The operation 
of the OR gate is properly defined: an output if either input terminal has applied turn-on 
voltage or if both are in the “on” state. A 0 state exists only if both do not have a 1 state 
at the input terminals. 

The AND gate of Fig. 4.111b requires that the output be high only if both inputs have a 
turn-on voltage applied. If both are in the “on” state, a short-circuit equivalent can be used 
for the connection between the collector and the emitter of each transistor, providing a di- 
rect path from the applied 5-V source to the output — thereby establishing a high, or 1, state 
at the output terminal. If one or both transistors are off due to 0 V at the input terminal, an 
open circuit is placed in series with the path from the 5-V supply voltage to the output, and 
the output voltage is 0 V, or an “off’ state. 



V cc? 5 V 





V cc 9 5V 


*1 K 

-wv — 1 

lOkft ^ 


B R 2 yA 

0 AAA/ 1 

lOkft ^ 

Qi 



OR Gate 



Qi 



-o C = A + B 



A o AAAr 

10 kO 



E o AAAr 

10 kO 



AND Gate 



1 

k 



02 



-o C = A-B 



R e ? 3.3 kO 



r e ? 3.3 m 



A 


B 


c 


A 


B 


c 


0 


0 


0 


0 


0 


0 


0 


1 


1 


0 


1 


0 


1 


0 


1 


1 


0 


0 


1 


1 


1 


1 


1 


1 



1 = high 
0 = low 



(b) 



(a) 



FIG. 4.1 1 1 

BJT logic gates: (a) OR; (b) AND. 



Voltage Level Indicator 

The last application to be introduced in this section, the voltage level indicator, includes 
three of the elements introduced thus far: the transistor, the Zener diode, and the LED. The 
voltage level indicator is a relatively simple network using a green LED to indicate when 
the source voltage is close to its monitoring level of 9 V. In Fig. 4.1 12 the potentiometer is 
set to establish 5.4 V at the point indicated. The result is sufficient voltage to turn on both 



SUMMARY 233 



the 4.7-V Zener and the transistor and establish a collector current through the LED suffi- 
cient in magnitude to turn on the green LED. 

Once the potentiometer is set, the LED will emit its green light as long as the supply 
voltage is near 9 V. However, if the terminal voltage of the 9-V battery should decrease, 
the voltage set up by the voltage-divider network may drop to 5 V from 5.4 V. At 5 V there 
is insufficient voltage to turn on both the Zener and the transistor, and the transistor will be 
in the “off’ state. The LED will immediately turn off, revealing that the supply voltage has 
dropped below 9 V or that the power source has been disconnected. 




4.20 SUMMARY ^ 

Important Conclusions and Concepts 

1. No matter what type of configuration a transistor is used in, the basic relationships 
between the currents are always the same, and the base-to-emitter voltage is the 
threshold value if the transistor is in the “on” state. 

2. The operating point defines where the transistor will operate on its characteristic 
curves under dc conditions. For linear (minimum distortion) amplification, the dc 
operating point should not be too close to the maximum power, voltage, or current 
rating and should avoid the regions of saturation and cutoff. 

3. For most configurations the dc analysis begins with a determination of the base current. 

4. For the dc analysis of a transistor network, all capacitors are replaced by an open- 
circuit equivalent. 

5. The fixed-bias configuration is the simplest of transistor biasing arrangements, but it 
is also quite unstable due its sensitivity to beta at the operating point. 

6. Determining the saturation (maximum) collector current for any configuration can 
usually be done quite easily if an imaginary short circuit is superimposed between 
the collector and emitter terminals of the transistor. The resulting current through the 
short is then the saturation current. 

7. The equation for the load line of a transistor network can be found by applying 
Kirchhoff’s voltage law to the output or collector network. The g-point is then deter- 
mined by finding the intersection between the base current and the load line drawn on 
the device characteristics. 

8. The emitter- stabilized biasing arrangement is less sensitive to changes in beta — 
providing more stability for the network. Keep in mind, however, that any resistance 
in the emitter leg is “seen” at the base of the transistor as a much larger resistor, a 
fact that will reduce the base current of the configuration. 

9. The voltage-divider bias configuration is probably the most common of all the con- 
figurations. Its popularity is due primarily to its low sensitivity to changes in beta 
from one transistor to another of the same lot (with the same transistor label). The 
exact analysis can be applied to any configuration, but the approximate one can be 
applied only if the reflected emitter resistance as seen at the base is much larger than 
the lower resistor of the voltage-divider bias arrangement connected to the base of the 
transistor. 



234 DC BIASING— BJTs 



10. When analyzing the dc bias with a voltage feedback configuration, be sure to 
remember that both the emitter resistor and the collector resistor are reflected 
back to the base circuit by beta. The least sensitivity to beta is obtained when the 
reflected resistance is much larger than the feedback resistor between the base and 
the collector. 

1 1 . For the common-base configuration the emitter current is normally determined 
first due to the presence of the base-to-emitter junction in the same loop. Then the fact 
that the emitter and the collector currents are essentially of the same magnitude is 
employed. 

12. A clear understanding of the procedure employed to analyze a dc transistor network 
will usually permit a design of the same configuration with a minimum of difficulty 
and confusion. Simply start with those relationships that minimize the number of 
unknowns and then proceed to make some decisions about the unknown elements of 
the network. 

13. In a switching configuration, a transistor quickly moves between saturation and cut- 
off, or vice versa. Essentially, the impedance between collector and emitter can be 
approximated as a short circuit for saturation and an open circuit for cutoff. 

14. When checking the operation of a dc transistor network, first check that the base-to- 
emitter voltage is very close to 0.7 V and that the collector-to-emitter voltage is 
between 25% and 75% of the applied voltage Vcc- 

15. The analysis of pnp configurations is exactly the same as that applied to npn transis- 
tors with the exception that current directions will reverse and voltages will have the 
opposite polarities. 

16. Beta is very sensitive to temperature, and V BE decreases about 2.5 mV (0.0025 V) 
for each 1° increase in temperature on a Celsius scale. The reverse saturation current 
typically doubles for every 10° increase in Celsius temperature. 

17. Keep in mind that networks that are the most stable and least sensitive to temperature 
changes have the smallest stability factors. 



Equations 



Fixed bias: 



V BE = 0.7 V, I E =(P + 1 )I B = / c , Ic = Ph 
T Vcc Vbe 

l B ~ 

Emitter stabilized: 



R* 



Ic = Ph 



I R ~ 



Vcc Vbe 
Rb + (P + 1 )Re 



Voltage-divider bias: 



Ri = (P + We 



cc 



^Th “ V BE 



Exact: Rtu — ^ 2 ? Rtu — V7> — , I B — 

Th 1 11 2 Th Rl R x + R 2 R T h + (/3 + We 



Approximate: Test (3R E ^ 10 R 2 



V R = 



RlVcC 
VB ~ R x + Rj 
DC bias with voltage feedback: 

h ~ 

Common base: 



Ve=Vb~ Vbe , 1 E ~ ~ — I C 

k e 



Vcc ~ Vi 



BE 



Rb + P(Rc + Re) 

Vee ~ Vbe 



If — 



Rf 



Ic= I C = I E 



Ic = I E 



Transistor switching networks: 



, _ Vcc , ^ 7 Csa, „ y C£ sa 

7 c sat — „ > l B > n > ^sat — 



Rf 



Pdc 



Ic 



t on t r ~\~ trf, toff t s + tj- 



Stability factors: 



COMPUTER ANALYSIS 235 



Sdco) = 






A// 



CO 



S(V BE ) = —y S((3) = 

A v BE 






Sdco )■ 



Fixed bias: S(Jco ) — P 



Emitter bias: S(J C o) = 



j3(l + W 



* Voltage-divider bias: 
^Feedback bias: 

S(Y BE ): 



P + Rb/Re 

Change R B to R Th in above equation. 
Change R E to R c in above equation. 

P 

Fixed bias: S(V BE ) — 

Rb 

- p/R E f 

Emitter bias: S(V BE ) = 



P + Rb/ r e 

Voltage-divider bias: Change R B to Rju in above equation. 
^Feedback bias: Change R E to Rc in above equation. 

508 ): 



Fixed bias: S(fi) = 

Emitter bias: S(fi) = 



Pi 



7 Cl (l + R b /Re) X 
Pd 1 + Pi + Rb/Re) 

Voltage-divider bias: Change R B to 7?-^, in above equation. 
^Feedback bias: Change R E to R c in above equation. 



4.21 COMPUTER ANALYSIS ^ 

Cadence OrCAD 

Voltage-Divider Configuration The results of Example 4.8 will now be verified using 
Cadence OrCAD. Using methods described in detail in the previous chapters, we can con- 
struct the network of Fig. 4.113. Recall from the previous chapter that the transistor is 
found under the EVAL library, the dc source under the SOURCE library, and the resistors 
under the ANALOG library. The capacitor has not been called up earlier but can also be 
found in the ANALOG library. For the transistor, the list of available transistors can be 
found in the EVAL library. 

The value of beta is changed to 140 to match Example 4.8 by first clicking on the 
transistor symbol on the screen. It will then appear boxed in red to reveal it is in an active 
status. Then proceed with Edit-PSpice Model, and the PSpice Model Editor Demo dialog 
box will appear in which Bf can be changed to 140. As you try to leave the dialog box the 
Model Editor/16.3 dialog box will appear asking if you want to save the changes in the 
network library. Once they are saved, the screen will automatically return with beta set at 
its new value. 

The analysis can then proceed by selecting the New simulation profile key (looks like 
a printout with an asterisk in the top left corner) to obtain the New Simulation dialog box. 
Insert Fig. 4.113 and select Create. The Simulation Settings dialog box will appear in 
which Bias Point is selected under the Analysis Type heading. An OK, and the system is 
ready for simulation. 

Proceed by selecting the Run PSpice key (white arrow in green background) or the se- 
quence PSpice-Run. The bias voltages will appear as shown in Fig. 4.1 13 if the V option 
selected. The collector-to-emitter voltage is 13.19 V - 1.333 V = 11.857 V versus 12.22 V 
of Example 4.8. The difference is primarily due to the fact that we are using an actual 
transistor whose parameters are very sensitive to the operating conditions. Also recall the 
difference in beta from the specification value and the value obtained from the plot of the 
previous chapter. 



236 DC BIASING— BJTs 




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FIG- 4.113 

Applying PSpice Windows to the voltage- 
divider configuration of Example 4.8. 



FIG. 4.114 

Response obtained after changing fifrom 140 
to 255.9 for the network of Fig. 4.113. 



Because the voltage-divider network has a low sensitivity to changes in beta, let us return 
to the transistor specifications and replace beta by the default value of 255.9 and see how 
the results change. The result is the printout of Fig. 4.1 14, with voltage levels very close to 
those obtained in Fig. 4.113. 

Note the distinct advantage of having the network set up in memory . Any parameter 
can now be changed and a new solution obtained almost instantaneously — a wonderful 
advantage in the design process. 

Fixed-Bias Configuration Although the voltage-divider bias network is relatively 
insensitive to changes in the beta value, the fixed-bias configuration is very sensitive to 
beta variations. This can be demonstrated by setting up the fixed-bias configuration of 
Example 4.1 using a beta of 50 for the first run. The results of Fig. 4.115 demonstrate 
that the design is a fairly good one. The collector or collector-to-emitter voltage is 
appropriate for the applied source. The resulting base and collector currents are fairly 
common for a good design. 

However, if we now go back to the transistor specifications and change beta back to the 
default value of 255.9, we obtain the results of Fig. 4. 1 16. The collector voltage is now only 
0.1 13 V at a current of 5.4 mA — a terrible operating point. Any applied ac signal would be 
severely truncated due to the low collector voltage. 




FIG. 4.115 

Fixed-bias configuration with a f3 of 50. 



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FIG. 4.116 

Network of Fig. 4.115 with a /3 of 255.9. 




Clearly, therefore, from the preceding analysis, the voltage-divider configuration is the COMPUTER ANALYSIS 237 
preferred design if there is any concern about beta variations. 

Multisim 

Multisim will now be applied to the fixed-bias network of Example 4.4 to provide an 
opportunity to review the transistor options internal to the software package and to com- 
pare results with the handwritten approximate solution. 

All the components of Fig. 4. 1 17 except the transistor can be entered using the procedure 
described in Chapter 2. Transistors are available through the Transistor key pad, which 
is the fourth option down on the Component toolbar. When it is selected, the Select a 
Component dialog box will appear, from which B JT_NPN is chosen. The result is a Com- 
ponent list, from which 2N2222A can be selected. An OK, and the transistor will appear 
on the screen with the labels Q1 and 2N2222A. The label Bf = 50 can be added by first 
selecting Place in the top toolbar followed by the Text option. Place the resulting marker 
in the area you want to place the text and click once more. The result is a blank space with 
a blinking marker for where the text will appear when entered. When finished, a second 
double-click, and the label is set. To move the label to the position shown in Fig. 4.117, 
simply click on the label to place the four small squares around the device. Then click it 
once more and drag it to the desired position. Release the clicker, and it is in place. Another 
click, and the four small markers will disappear. 




FIG. 4.117 

Verifying the results of Example 4.4 using Multisim. 



Even though the label may say Bf = 50, the transistor will still have the default param- 
eters stored in memory. To change the parameters, the first step is to click on the device 
to establish the device boundaries. Then select Edit, followed by Properties, to obtain 
the BJT_NPN dialog box. If it is not already present, select Value and then Edit Model. 
The result will be the Edit Model dialog box in which (3 and I s can be set to 50 and 1 nA, 
respectively. Then choose Change Part Model to obtain the BJT_NPN dialog box again 
and select OK. The transistor symbol on the screen will now have an asterisk to indicate 
that the default parameters have been modified. One more click to remove the four markers, 
and the transistor is set with its new parameters. 

The indicators appearing in Fig. 4.1 17 were set as described in the previous chapter. 

Finally, the network must be simulated using one of the methods described in Chapter 2. 
For this example the switch was set to the 1 position and then back to the 0 position after the 
Indicator values stabilized. The relatively low levels of current were partially responsible 
for the low level of this voltage. 







DC BIASING— BJTs 



The results are a close match with those of Example 4.4 with I c = 2.217 mA, V B = 
2.636 V, V c = 15.557 V, and V E = 2.26 V. 

The relatively few comments required here to permit the analysis of transistor networks 
is a clear indication that the breadth of analysis using Multisim can be expanded dramati- 
cally without having to learn a whole new set of rules — a very welcome characteristic of 
most technology software packages. 

PROBLEMS ^ 

*Note : Asterisks indicate more difficult problems. 

4.3 Fixed-Bias Configuration 

1. For the fixed-bias configuration of Fig. 4.1 18, determine: 



a. 


V 


b. 


7 qr 


c. 


v ce q - 


d. 


v c - 


e. 


V B - 


f. 


V E . 



16 V 




Problems 1, 4, 6, 7, 14, 65, 69, 
71, and 75. 

2. Given the information appearing in Fig. 4.1 19, determine: 

a. Ir- 

b. R c . 

c. R b . 

d. Vce- 

3. Given the information appearing in Fig. 4.120, determine: 

a. I c . 

b. V co 

c. (3. 

d. R b . 




FIG. 4.119 

Problem 2. 



FIG. 4.120 

Problem 3. 




4. Find the saturation current (/ Cgat ) for the fixed-bias configuration of Fig. 4.118. PROBLEMS 

*5. Given the BJT transistor characteristics of Fig. 4.121: 

a. Draw a load line on the characteristics determined by £ = 21 V and R c = 3 kfl for a 
fixed-bias configuration. 

b. Choose an operating point midway between cutoff and saturation. Determine the value of 
R b to establish the resulting operating point. 

c. What are the resulting values of I Cq and VcEq- 

d. What is the value of / 3 at the operating point? 

e. What is the value of a defined by the operating point? 

f. What is the saturation current (7 C ) for the design? 

g. Sketch the resulting fixed-bias configuration. 

h. What is the dc power dissipated by the device at the operating point? 

i. What is the power supplied by V cc ? 

j. Determine the power dissipated by the resistive elements by taking the difference between 
the results of parts (h) and (i). 




FIG. 4.121 

Problems 5, 6, 9, 13, 24, 44, and 57. 



6. a. Ignoring the provided value of )S(i 2 0) draw the load line for the network of Fig. 4. 1 18 on the 

characteristics of Fig. 4.121. 

b. Find the Q- point and the resulting I Cq and V C e q - 

c. What is the beta value at this g-point? 

7. If the base resistor of Fig. 4.118 is increased to 910 k D, find the new g-point and resulting 
values of I Cq and V CEq - 

4.4 Emitter-Bias Configuration 

8. For the emitter- stabilized bias circuit of Fig. 4. 122, determine: 

a. h Q - 

b- Icq- 

c - V CE q. 

d. V c . 

e. V B . 

f. V E . 



DC BIASING— BJTs 



20 V 




9. a. Draw the load line for the network of Fig. 4. 122 on the characteristics of Fig. 4.121 using (3 
from problem 8 to find I Bq . 

b. Find the g-point and resulting values I c and Vce q - 

c. Find the value of f3 at the g-point. 

d. How does the value of part (c) compare with (3 = 125 in problem 8? 

e. Why are the results for problem 9 different from those of problem 8? 

10. Given the information provided in Fig. 4. 123, determine: 

a. R c . 

b. R E . 

c. R b . 

d. Vce • 

e. V B . 

11. Given the information provided in Fig. 4.124, determine: 

a. /3. 

b. Vcc- 

c. R b . 



12 V 




Vcc; 




FIG. 4.124 

Problem 11. 



12. Determine the saturation current (/c sat ) f° r the network of Fig. 4.122. 

*13. Using the characteristics of Fig. 4.121, determine the following for an emitter-bias configura- 
tion if a g-point is defined at I c = 4 mA and V CEq = 10 V. 

a. R c tfV C c = 24 V and R E = 1.2 kO. 

b. (3 at the operating point. 

c. R b . 

d. Power dissipated by the transistor. 

e. Power dissipated by the resistor R c . 




*14. a. Determine I c and Vqe f° r the network of Fig. 4.118. 

b. Change /3 to 180 and determine the new value of I c and V C e for the network of Fig. 4.1 18. 

c. Determine the magnitude of the percentage change in I c and V C e using the following 
equations: 



%M r = 



I r - I r 

'-"(part b) '-"(part a) 



X 100%, %A V CE = 



t^Cfi^part b) ^-'■^(part a) 



X 100% 



d. Determine I c and Vqe f° r the network of Fig. 4. 122. 

e. Change /3 to 187.5 and determine the new value of I c and V C e for the network of Fig. 4. 122. 

f. Determine the magnitude of the percentage change in I c and V C e using the following 
equations: 



%A I c = 



Ir ~ Ir 

'-"(parte) '-"(partd) 



-"(part d) 



X 100%, %A V CE = 



parte) ^C2?(partd) 



V CE ( 



(part d) 



X 100% 



g. In each of the above, the magnitude of (3 was increased 50%. Compare the percentage 
change in I c and V C e for eac h configuration, and comment on which seems to be less sensi- 
tive to changes in /3. 



4.5 Voltage-Divider Bias Configuration 

15. For the voltage-divider bias configuration of Fig. 4. 125, determine: 

a. / % 
b- f c Q - 
c - v ce q - 

d. V c . 

e. V E . 

f. V B . 

16. a. Repeat problem 15 for (3 = 140 using the general approach (not the approximate). 

b. What levels are affected the most? Why? 

17. Given the information provided in Fig. 4.126, determine: 

a. I c . 

b. V E . 

c. V B . 

d. R h 




16 V 




FIG. 4.125 

Problems 15, 16, 20, 23, 25, 67, 
69, 70, 73, and 77. 




18. Given the information appearing in Fig. 4.127, determine: 

a. Ir- 

b. V E . 
c * Vcc- 

d. Vce- 

e. V B . 

f. R h 



BIASING— BJTs 




19. Determine the saturation current (/ c ) for the network of Fig. 4.125. 

20. a. Repeat problem 16 with (3 = 140 using the approximate approach and compare results, 
b. Is the approximate approach valid? 

*21. Determine the following for the voltage-divider configuration of Fig. 4.128 using the approxi- 
mate approach if the condition established by Eq. (4.33) is satisfied. 



a. 


Ic- 


b. 


VcE- 


c. 


h- 


d. 


V E - 


e. 


V b - 




*22. Repeat Problem 21 using the exact (Thevenin) approach and compare solutions. Based on the 

results, is the approximate approach a valid analysis technique if Eq. (4.33) is satisfied? 

23. a. Determine I Cq , V C e q , and I Bq for the network of Problem 15 (Fig. 4.125) using the approxi- 
mate approach even though the condition established by Eq. (4.33) is not satisfied. 

b. Determine I Cq , V C e q > and I Bq using the exact approach. 

c. Compare solutions and comment on whether the difference is sufficiently large to require 
standing by Eq. (4.33) when determining which approach to employ. 

*24. a. Using the characteristics of Fig. 4.121, determine Rc and R E for a voltage-divider network 
having a Q- point of I c = 5 mA and Vce q = 8 V. Use Vqc — 24 V and R c = 3 R E . 

b. Find V E - 

c. Determine V B . 

d. Find R 2 if R\ = 24 kfl assuming that /3R E > 10/? 2 - 

e. Calculate (3 at the g-point- 

f. Test Eq. (4.33), and note whether the assumption of part (d) is correct. 



*25. a. Determine I c and Vce for the network of Fig. 4.125. 

b. Change p to 120 (50% increase), and determine the new values of I c and V CE f° r the net- 
work of Fig. 4.125. 

c. Determine the magnitude of the percentage change in I c and V EE using the following 
equations: 



%M C = 



I r ~ Ir 

L -(partb) '-'(part a) 



X 100%, %A V CE = 



b) ^C^part a) 



x 100% 



d. Compare the solution to part (c) with the solutions obtained for parts (c) and (f) of Problem 14. 

e. Based on the results of part (d), which configuration is least sensitive to variations in pi 

*26. a. Repeat parts (a) through (e) of Problem 25 for the network of Fig. 4.128. Change p to 180 
in part (b). 

b. What general conclusions can be made about networks in which the condition fiR E > 10i? 2 
is satisfied and the quantities I c and V CE are to be determined in response to a change in pi 



4.6 Collector-Feedback Configuration 

27. For the collector-feedback configuration of Fig. 4. 129, determine: 

a. I B . 

b. 7 C . 

c. V c . +16 V 





28. 



29. 



30. 



* 31 . 



For the network of problem 27 

V' 

a. Determine I c using the equation I c = — 

e u r 



Vcc ~ Vbe 
Rc + r e 



b. Compare with the results of problem 27 for I c . 

c. Compare R r to R E /p. 

d. Is the statement valid that the larger R' is compared with R e /r, the more accurate the 

V' 

equation I Cq = — ? Prove using a short derivation for the exact current I Cq . 

e. Repeat parts (a) and (b) for p = 240 and comment on the new level of I Cq . 



For the voltage feedback network of Fig. 4.130, determine: 

a. 7 C . 

b. V c . 

c. V E . 

d. V EE - 

a. Compare levels of R' = R c + R E to R F /p for the network of Fig. 4.131. 

b. Is the approximation I Cq = V’/R ' valid? 

a. Determine the levels of I c and V CE for the network of Fig. 4. 13 1 . 

b. Change p to 135 (50% increase), and calculate the new levels of I c and V CE . 

c. Determine the magnitude of the percentage change in I c and V CE using the following equations: 



%A7 C = 



Ir - Ir 

'-'■(partb) ^ (part a) 



^(part a) 



X 100%, %\V CE = 



V CE imh) VcE ip 



x 100% 



'CE, 



(part a) 



d. Compare the results of part (c) with those of Problems 14(c), 14(f ), and 25(c). How does 
the collector-feedback network stack up against the other configurations in sensitivity to 
changes in pi 



DC BIASING— BJTs 



30 V 



8.2 kQ 




FIG. 4.130 
Problems 29 and 30. 



+ 22 V 




FIG. 4.131 

Problems 30 and 31. 



32 . Determine the range of possible values for V E for the network of Fig. 4.132 using the 1-MO 
potentiometer. 

* 33 . Given V B = 4 V for the network of Fig. 4.133, determine: 

a. V E . 

b. I c . 

c. V c . 

d. V C e- 

e. I B . 





4.7 Emitter-Follower Configuration 

* 34 . Determine the level of V E and I E for the network of Fig. 4.134. 




FIG. 4.134 
Problem 34. 




35 . For the emitter follower network of Fig. 4. 135 

a. Find I B , 7 C , and I E . 

b. Determine V B , V c , and V E . 

c. Calculate V BC and 



12V 




FIG. 4.135 

Problem 35. 



4.8 Common-Base Configuration 

* 36 . For the network of Fig. 4.136, determine: 

a. I B . 

b. 7 C . 

c. F C£ . 

d. V c . 

* 37 . For the network of Fig. 4.137, determine: 

a. I E . 

b. V c . 

c. V CE . 

38 . For the common-base network of Fig. 4.138 

a. Using the information provided determine the value of Re- 
ly. Find the currents I B and I E . 
c. Determine the voltages V BC and V CE - 




FIG. 4.136 

Problem 36. 



FIG. 4.137 

Problem 37. 



FIG. 4.138 

Problem 38. 











4.9 Miscellaneous Bias Configurations 

* 39 . For the network of Fig. 4.139, determine: 

a. I B . 

b. 7 C . 

c. V E . 

d. V ee - 



DC BIASING— BJTs 



■0+18 V 



18 V 



510 kn 



510 kQ 




FIG. 4.139 

Problem 39. 



3.9 k a 



560 kQ 

-AAAr 




= 8 V 




FIG. 4.140 
Problems 40 and 68. 



40. Given V E = 8 V for the network of Fig. 4.140, determine: 

a. I B . 

b. I c . 

c. (3. 

d. Vce • 

4. 1 1 Design Operations 

41. Determine R c and R B for a fixed-bias configuration if V C c = 12 V, f3 = 80, and/ Ce = 2.5 mA 
with = 6 V. Use standard values. 

42. Design an emitter- stabilized network at I Cq — ^/c sat and Use V C c ~ 20 V, 

/ Csat — 10 mA, (3 = 120, and R c — 4 R E . Use standard values. 

43. Design a voltage-divider bias network using a supply of 24 V, a transistor with a beta of 1 10, 
and an operating point of I Cq — 4 mA and V C e q — 8 V. Choose V E — |Vcc- Use standard 
values. 

*44. Using the characteristics of Fig. 4.121, design a voltage-divider configuration to have a satura- 
tion level of 10 mA and a (Upoint one-half the distance between cutoff and saturation. The 
available supply is 28 V, and V E is to be one-fifth of V C c • The condition established by Eq. 
(4.33) should also be met to provide a high stability factor. Use standard values. 

4.1 2 Multiple BIT Networks 

45. For the 7?-C-coupled amplifier of Fig. 4.141 determine 

a. the voltages V B , V c , and V E for each transistor. 

b. the currents I B , I c , and I E for each transistor 



+20 V 




FIG. 4.141 

Problem 45. 

46. For the Darlington amplifier of Fig. 4.142 determine 

a. the level of fo. 

b. the base current of each transistor. 

c. the collector current of each transistor. 

d. the voltages V Cl , V Cl , V El , and V Er 



PROBLEMS 



18 V 




FIG. 4.142 
Problem 46. 



47 . For the cascode amplifier of Fig. 4. 143 determine 

a. the base and collector currents of each transistor. 

b. the voltages V B| , V B; , V £] , V Cl , V Ev and V Cr 



V CC = 22 V 




FIG. 4.143 

Problem 47. 



48 . For the feedback amplifier of Fig. 4.144 determine 

a. the base and collector current of each transistor. 

b. the base, emitter, and collector voltages of each transistor. 

4. 1 3 Current Mirror Circuits 

49 . Calculate the mirrored current I in the circuit of Fig. 4.145. 





DC BIASING— BJTs 



12 V 





FIG. 4.144 FIG. 4.145 

Problem 48. Problem 49. 



*50. Calculate collector currents for Q\ and Q 2 in Fig. 4.146. 



+12 V 




FIG. 4.146 
Problem 50. 



4. 1 4 Current Source Circuits 

51. Calculate the current through the 2.2-kfl load in the circuit of Fig. 4.147. 

52. For the circuit of Fig. 4. 148, calculate the current I. 



28 V 





FIG. 4.148 

Problem 52. 



- 200 




*53. Calculate the current I in the circuit of Fig. 4. 149. 



PROBLEMS 




FIG. 4.149 

Problem 53. 



4.15 pup Transistors 

54. Determine V& Vce> and I c for the network of Fig. 4.150. 

55. Determine V E and I B for the network of Fig. 4. 15 1 . 



-12 V 




FIG. 4.150 
Problem 54. 



-22 V 




56. Determine I E and Vq for the network of Fig. 4. 152. 




FIG. 4.152 

Problem 56. 



4.1 6 Transistor Switching Networks 

*57. Using the characteristics of Fig. 4.121, determine the appearance of the output waveform for 
the network of Fig. 4.153. Include the effects of Vcf » and determine /», /» , and I r when 

° '^- c, sar D D max’ L 'sat 

Vj = 10 V. Determine the collector-to-emitter resistance at saturation and cutoff. 



DC BIASING— BJTs 



10 V 



10 V 



0 Y 




FIG. 4.153 

Problem 57. 



*58. Design the transistor inverter of Fig. 4.154 to operate with a saturation current of 8 mA using a 
transistor with a beta of 100. Use a level of I B equal to 120% of I B and standard resistor values. 




FIG. 4.154 

Problem 58. 



59. a. Using the characteristics of Fig. 3.23e, determine t on and f 0 ff at a current of 2 mA. Note the 
use of log scales and the possible need to refer to Section 9.2. 

b. Repeat part (a) at a current of 10 mA. How have t on and f 0 ff changed with increase in col- 
lector current? 

c. For parts (a) and (b), sketch the pulse waveform of Fig. 4.91 and compare results. 

4.1 7 Troubleshooting Techniques 

*60. The measurements of Fig. 4.155 all reveal that the network is not functioning correctly. List as 
many reasons as you can for the measurements obtained. 






FIG. 4.155 
Problem 60. 



*61. The measurements appearing in Fig. 4.156 reveal that the networks are not operating properly. 
Be specific in describing why the levels obtained reflect a problem with the expected network 
behavior. In other words, the levels obtained reflect a very specific problem in each case. 



PROBLEMS 





FIG. 4.156 
Problem 61. 



62. For the circuit of Fig. 4.157: 

a. Does V c increase or decrease if R B is increased? 

b. Does I c increase or decrease if /3 is reduced? 

c. What happens to the saturation current if / 3 is increased? 

d. Does the collector current increase or decrease if V C c is reduced? 

e. What happens to V C e if the transistor is replaced by one with smaller /3? 

63. Answer the following questions about the circuit of Fig. 4. 158: 

a. What happens to the voltage V c if the transistor is replaced by one having a larger value of (31 

b. What happens to the voltage V C e if the ground leg of resistor R Bl opens (does not connect 
to ground)? 

c. What happens to I c if the supply voltage is low? 

d. What voltage V C e would occur if the transistor base-emitter junction fails by becoming 
open? 

e. What voltage V C e would result if the transistor base-emitter junction fails by becoming a 
short? 

*64. Answer the following questions about the circuit of Fig. 4. 159: 

a. What happens to the voltage V c if the resistor R B is open? 

b. What should happen to V C e if P increases due to temperature? 

c. How will V B be affected when replacing the collector resistor with one whose resistance is 
at the lower end of the tolerance range? 

d. If the transistor collector connection becomes open, what will happen to V E 1 

e. What might cause V C e t0 become nearly 18 V? 




+ Fcc -16 V 



kQ 



£ = 120 



= 1.5 kQ 



+V CC = 20V 




y cc = + l8V 




FIG. 4.157 

Problem 62. 



FIG. 4.158 

Problem 63. 



FIG. 4.159 

Problem 64. 



252 



DC BIASING— BJTs 




4. 1 8 Bias Stabilization 

65. Determine the following for the network of Fig. 4.118: 
a * S(Jco)- 

b. S(V BE ). 

c. SQ3), using 7\ as the temperature at which the parameter values are specified and /3(T 2 ) as 
25% more than ^(T^). 

d. Determine the net change in I c if a change in operating conditions results in I co increasing 
from 0.2 /jlA to 10 /jlA, V be drops from 0.7 V to 0.5 V, and (3 increases 25%. 

*66. For the network of Fig. 4.122, determine: 
a * SQco)- 

b. S(V BE ). 

c. 5(/3), using 7\ as the temperature at which the parameter values are specified and p(T 2 ) as 
25% more than /3(Ti ). 

d. Determine the net change in I c if a change in operating conditions results in I co increasing 
from 0.2 /jlA to 10 /jlA, V be drops from 0.7 V to 0.5 V, and / 3 increases 25%. 

*67. For the network of Fig. 4.125, determine: 
a * SQco)- 

b. S(V BE ). 

c. SQ3), using 7\ as the temperature at which the parameter values are specified and /3(T 2 ) as 
25% more than (3(Ti ). 

d. Determine the net change in I c if a change in operating conditions results in I co increasing 
from 0.2 /jlA to 10 /jlA , V BE drops from 0.7 V to 0.5 V, and ft increases 25%. 

*68. For the network of Fig. 4.140, determine: 
a * S(Ico). 

b. S(V BE ). 

c. S(p), using T\ as the temperature at which the parameter values are specified and /3(T 2 ) as 
25% more than ^(T^). 

d. Determine the net change in I c if a change in operating conditions results in I co increasing 
from 0.2 /jlA to 10 /jlA , V BE drops from 0.7 V to 0.5 V, and (3 increases 25%. 

*69. Compare the relative values of stability for Problems 65 through 68. The results for Exercises 
65 and 67 can be found in Appendix E. Can any general conclusions be derived from the 
results? 

*70. a. Compare the levels of stability for the fixed-bias configuration of Problem 65. 

b. Compare the levels of stability for the voltage-divider configuration of Problem 67. 

c. Which factors of parts (a) and (b) seem to have the most influence on the stability of the 

system, or is there no general pattern to the results? 

4.2 1 Computer Analysis 

71. Perform a PS pice analysis of the network of Fig. 4.1 18. That is, determine 7 C , V CE , and I B . 

72. Repeat Problem 71 for the network of Fig. 4. 122. 

73. Repeat Problem 71 for the network of Fig. 4. 125. 

74. Repeat Problem 71 for the network of Fig. 4.129. 

75. Repeat Problem 71 using Multisim. 

76. Repeat Problem 72 using Multisim. 

77. Repeat Problem 73 using Multisim. 

78. Repeat Problem 74 using Multisim. 




BJT AC Analysis 




CHAPTER OBJECTIVES ^ 

Become familiar with the r e , hybrid, and hybrid tt models for the BJT transistor. 

Learn to use the equivalent model to find the important ac parameters for an amplifier. 
Understand the effects of a source resistance and load resistor on the overall gain and 
characteristics of an amplifier. 

Become aware of the general ac characteristics of a variety of important BJT 
configurations. 

Begin to understand the advantages associated with the two-port systems approach to 
single- and multistage amplifiers. 

• Develop some skill in troubleshooting ac amplifier networks. 



5.1 INTRODUCTION ^ 

The basic construction, appearance, and characteristics of the transistor were introduced in 
Chapter 3. The dc biasing of the device was then examined in detail in Chapter 4. We now 
begin to examine the ac response of the BJT amplifier by reviewing the models most fre- 
quently used to represent the transistor in the sinusoidal ac domain. 

One of our first concerns in the sinusoidal ac analysis of transistor networks is the mag- 
nitude of the input signal. It will determine whether small-signal or large-signal techniques 
should be applied. There is no set dividing line between the two, but the application — and 
the magnitude of the variables of interest relative to the scales of the device characteristics — 
will usually make it quite clear which method is appropriate. The small- signal technique is 
introduced in this chapter, and large-signal applications are examined in Chapter 12. 

There are three models commonly used in the small- signal ac analysis of transistor 
networks: the r e model, the hybrid tt model, and the hybrid equivalent model. This chapter 
introduces all three but emphasizes the r e model. 



5-2 AMPLIFICATION IN THE AC DOMAIN ^ 

It was demonstrated in Chapter 3 that the transistor can be employed as an amplifying device. 
That is, the output sinusoidal signal is greater than the input sinusoidal signal, or, stated 
another way, the output ac power is greater than the input ac power. The question then arises 
as to how the ac power output can be greater than the input ac power. Conservation of energy 
dictates that over time the total power output, P Q , of a system cannot be greater than its power 





254 BJT AC ANALYSIS 




0 t 



input, P(, and that the efficiency defined by rj = PjPi cannot be greater than 1. The factor 
missing from the discussion above that permits an ac power output greater than the input ac 
power is the applied dc power. It is the principal contributor to the total output power even 
though part of it is dissipated by the device and resistive elements. In other words, there is an 
“exchange” of dc power to the ac domain that permits establishing a higher output ac power. 
In fact, a conversion efficiency is defined by rj = P 0 (ac)/Pi(dcy where P Q ( ac ) is the ac power 
to the load and P^c) is the dc power supplied. 

Perhaps the role of the dc supply can best be described by first considering the simple 
dc network of Fig. 5.1. The resulting direction of flow is indicated in the figure with a plot 
of the current i versus time. Let us now insert a control mechanism such as that shown in 
Fig. 5.2. The control mechanism is such that the application of a relatively small signal to 
the control mechanism can result in a substantial oscillation in the output circuit. 



Control 

mechanism 



r 



AA/V 

T R 



w 




u 





FIG. 5.1 

Steady current established by a 
dc supply. 



FIG. 5.2 

Effect of a control element on the steady-state flow of the electrical 
system of Fig. 5.1. 



That is, for this example, 

Lc(p-p) L(p-p) 

and amplification in the ac domain has been established. The peak-to-peak value of the 
output current far exceeds that of the control current. 

For the system of Fig. 5.2, the peak value of the oscillation in the output circuit is con- 
trolled by the established dc level. Any attempt to exceed the limit set by the dc level will 
result in a “clipping” (flattening) of the peak region at the high and low end of the output 
signal. In general, therefore, proper amplification design requires that the dc and ac com- 
ponents be sensitive to each other’s requirements and limitations. 

However, it is extremely helpful to realize that: 

The superposition theorem is applicable for the analysis and design of the dc and ac 
components of a BJT network , permitting the separation of the analysis of the dc and 
ac responses of the system. 

In other words, one can make a complete dc analysis of a system before considering the 
ac response. Once the dc analysis is complete, the ac response can be determined using a 
completely ac analysis. It happens, however, that one of the components appearing in the 
ac analysis of BJT networks will be determined by the dc conditions, so there is still an 
important link between the two types of analysis. 

5-1 BIT TRANSISTOR MODELING ^ 

The key to transistor small-signal analysis is the use of the equivalent circuits (models) to 
be introduced in this chapter. 

A model is a combination of circuit elements , properly chosen , that best approximates 
the actual behavior of a semiconductor device under specific operating conditions. 

Once the ac equivalent circuit is determined, the schematic symbol for the device can 
be replaced by this equivalent circuit and the basic methods of circuit analysis applied to 
determine the desired quantities of the network. 

In the formative years of transistor network analysis the hybrid equivalent network was 
employed the most frequently. Specification sheets included the parameters in their listing, 
and analysis was simply a matter of inserting the equivalent circuit with the listed values. 




The drawback to using this equivalent circuit, however, is that it is defined for a set of oper- 
ating conditions that might not match the actual operating conditions. In most cases, this is 
not a serious flaw because the actual operating conditions are relatively close to the chosen 
operating conditions on the data sheets. In addition, there is always a variation in actual 
resistor values and given transistor beta values, so as an approximate approach it was quite 
reliable. Manufacturers continue to specify the hybrid parameter values for a particular 
operating point on their specification sheets. They really have no choice. They want to give 
the user some idea of the value of each important parameter so comparisons can be made 
between transistors, but they really do not know the user’s actual operating conditions. 

In time the use of the r e model became the more desirable approach because an impor- 
tant parameter of the equivalent circuit was determined by the actual operating conditions 
rather than using a data sheet value that in some cases could be quite different. Unfortu- 
nately, however, one must still turn to the data sheets for some of the other parameters of 
the equivalent circuit. The r e model also failed to include a feedback term, which in some 
cases can be important if not simply troublesome. 

The r e model is really a reduced version of the hybrid i t model used almost exclusively 
for high-frequency analysis. This model also includes a connection between output and 
input to include the feedback effect of the output voltage and the input quantities. The full 
hybrid model is introduced in Chapter 9. 

Throughout the text the r e model is the model of choice unless the discussion centers 
on the description of each model or a region of examination that predetermines the model 
that should be used. Whenever possible, however, a comparison between models will be 
discussed to show how closely related they really are. It is also important that once you gain 
a proficiency with one model it will carry over to an investigation using a different model, 
so moving from one to another will not be a dramatic undertaking. 

In an effort to demonstrate the effect that the ac equivalent circuit will have on the 
analysis to follow, consider the circuit of Fig. 5.3. Let us assume for the moment that the 
small-signal ac equivalent circuit for the transistor has already been determined. Because 
we are interested only in the ac response of the circuit, all the dc supplies can be replaced 
by a zero-potential equivalent (short circuit) because they determine only the dc (quiescent 
level) of the output voltage and not the magnitude of the swing of the ac output. This is 
clearly demonstrated by Fig. 5.4. The dc levels were simply important for determining the 
proper Q-point of operation. Once determined, the dc levels can be ignored in the ac analy- 
sis of the network. In addition, the coupling capacitors C\ and C 2 and bypass capacitor C 3 
were chosen to have a very small reactance at the frequency of application. Therefore, they, 
too, may for all practical purposes be replaced by a low-resistance path or a short circuit. 
Note that this will result in the “shorting out” of the dc biasing resistor R E . Recall that ca- 
pacitors assume an “open-circuit” equivalent under dc steady- state conditions, permitting 
an isolation between stages for the dc levels and quiescent conditions. 







Transistor circuit under examination in this introductory discussion. 



BJT TRANSISTOR 255 
MODELING 



256 BJT AC ANALYSIS 




FIG. 5.4 

The network of Fig. 5.3 following removal of the dc 
supply and insertion of the short-circuit equivalent 
for the capacitors. 

It is important as you progress through the modifications of the network to define the ac 
equivalent that the parameters of interest such as Z h Z 0 , f, and I 0 as defined by Fig. 5.5 be 
carried through properly. Even though the network appearance may change, you want to be 
sure the quantities you find in the reduced network are the same as defined by the original 
network. In both networks the input impedance is defined from base to ground, the input 
current as the base current of the transistor, the output voltage as the voltage from collector 
to ground, and the output current as the current through the load resistor R c . 



o- 

+ 




Vi 

o- 



Zi 



System 




-o 

+ 

Vo 

-o 




FIG. 5.5 

Defining the important parameters 
of any system. 



FIG. 5.6 

Demonstrating the reason for the defined 
directions and polarities. 



The parameters of Fig. 5.5 can be applied to any system whether it has one or a thou- 
sand components. For all the analysis to follow in this text, the directions of the currents, 
the polarities of the voltages, and the direction of interest for the impedance levels are as 
appearing in Fig. 5.5. In other words, the input current f and output current I 0 are, by defini- 
tion, defined to enter the system. If, in a particular example, the output current is leaving the 
system rather than entering the system as shown in Fig. 5.5, a minus sign must be applied. 
The defined polarities for the input and output voltages are also as appearing in Fig. 5.5. If 
V 0 has the opposite polarity, the minus sign must be applied. Note that Z ; is the impedance 
“looking into” the system, whereas Z Q is the impedance “looking back into” the system 
from the output side. By choosing the defined directions for the currents and voltages as 
appearing in Fig. 5.5, both the input impedance and output impedance are defined as having 
positive values. For example, in Fig. 5.6 the input and output impedances for a particular 
system are both resistive. For the direction of f and I Q the resulting voltage across the resis- 
tive elements will have the same polarity as V t and V 0 , respectively. If I Q had been defined 
as the opposite direction in Fig. 5.5 a minus sign would have to be applied. For each case 
Z t = I i and Z Q = V 0 /I 0 with positive results if they all have the defined directions and 
polarity of Fig. 5.5. If the output current of an actual system has a direction opposite to that 




of Fig. 5.5 a minus sign must be applied to the result because V Q must be defined as appear- 
ing in Fig. 5.5. Keep Fig. 5.5 in mind as you analyze the BJT networks in this chapter. It is 
an important introduction to “System Analysis,” which is becoming so important with the 
expanded use of packaged IC systems. 

If we establish a common ground and rearrange the elements of Fig. 5.4, R j and R 2 will 
be in parallel, and Rc will appear from collector to emitter as shown in Fig. 5.7. Because 
the components of the transistor equivalent circuit appearing in Fig. 5.7 employ familiar 
components such as resistors and independent controlled sources, analysis techniques 
such as superposition, Thevenin’s theorem, and so on, can be applied to determine the 
desired quantities. 



Transistor small-signal 
ac equivalent circuit 




*RA I R 2 



Vs *\j 

-l l 



•Rc V„ 



1 1 



FIG. 5.7 

Circuit of Fig. 5.4 redrawn for small-signal ac analysis. 



Let us further examine Fig. 5.7 and identify the important quantities to be determined 
for the system. Because we know that the transistor is an amplifying device, we would 
expect some indication of how the output voltage V 0 is related to the input voltage Vf — 
the voltage gain. Note in Fig. 5.7 for this configuration that the current gain is defined 
by Ai = I 0 /Ii. 

In summary, therefore, the ac equivalent of a transistor network is obtained by: 

1. Setting all dc sources to zero and replacing them by a short-circuit equivalent 

2. Replacing all capacitors by a short-circuit equivalent 

3. Removing all elements bypassed by the short-circuit equivalents introduced by steps 
1 and 2 

4 . Redrawing the network in a more convenient and logical form 

In the sections to follow, a transistor equivalent model will be introduced to complete 
the ac analysis of the network of Fig. 5.7. 

5-4 THE r e TRANSISTOR MODEL ^ 

The r e model for the CE, CB, and CC BJT transistor configurations will now be introduced 
with a short description of why each is a good approximation to the actual behavior of a 
BJT transistor. 



Common-Emitter Configuration 

The equivalent circuit for the common-emitter configuration will be constructed using the 
device characteristics and a number of approximations. Starting with the input side, we find 
the applied voltage V; is equal to the voltage V\, e with the input current being the base cur- 
rent lb as shown in Fig. 5.8. 

Recall from Chapter 3 that because the current through the forward-biased junction of 
the transistor is I E , the characteristics for the input side appear as shown in Fig. 5.9a for 
various levels of V BE . Taking the average value for the curves of Fig. 5.9a will result in the 
single curve of Fig. 5.9b, which is simply that of a forward-biased diode. 



THE r e TRANSISTOR 257 
MODEL 




FIG. 5.8 

Finding the input equivalent circuit 
for a BJT transistor. 




258 BJT AC ANALYSIS 




FIG. 5.10 

Equivalent circuit for the input side 
of a BJT transistor. 




FIG. 5.13 

Defining the level ofZ t . 




FIG. 5.9 

Defining the average curve for the characteristics of Fig. 5.9a. 



For the equivalent circuit, therefore, the input side is simply a single diode with a current 
I e , as shown in Fig. 5.10. However, we must now add a component to the network that will 
establish the current I e of Fig. 5.10 using the output characteristics. 

If we redraw the collector characteristics to have a constant /3 as shown in Fig. 5.11 
(another approximation), the entire characteristics at the output section can be replaced by 
a controlled source whose magnitude is beta times the base current as shown in Fig. 5.11. 
Because all the input and output parameters of the original configuration are now present, the 
equivalent network for the common-emitter configuration has been established in Fig. 5.12. 




o- 

+ 




o- 




-o 

+ 



FIG. 5.11 

Constant ft characteristics. 



FIG. 5.12 

BJT equivalent circuit. 



The equivalent model of Fig. 5.12 can be awkward to work with due to the direct con- 
nection between input and output networks. It can be improved by first replacing the diode 
by its equivalent resistance as determined by the level of I E , as shown in Fig. 5.13. Recall 
from Section 1.8 that the diode resistance is determined by r D = 26 m\/I D . Using the sub- 
script e because the determining current is the emitter current will result in r e = 26 mV / I E . 



Now, for the input side: 


Z, = 


Solving for V^ e : 


Vbe = 


and 


Z; = 



v E= v^ 
h h 

hr e = ( h + h)r e = (fib + h>e 

08 + 1 )I b r e 

Vbe _ Q3 + i) y e 

h h 



Z t = (fi + 1 )r e = f3r e 



( 5 . 1 ) 



The result is that the impedance seen “looking into” the base of the network is a resistor 
equal to beta times the value of r e , as shown in Fig. 5.14. The collector output current is 
still linked to the input current by beta as shown in the same figure. 



THE r e TRANSISTOR 259 
MODEL 




FIG. 5.14 

Improved BJT equivalent circuit. 

The equivalent circuit has therefore been defined for the ideal characteristics of Fig. 5.11, 
but now the input and output circuits are isolated and only linked by the controlled source — a 
form much easier to work with when analyzing networks. 



Early Voltage 

We now have a good representation for the input circuit, but aside from the collector out- 
put current being defined by the level of beta and I B , we do not have a good representation 
for the output impedance of the device. In reality the characteristics do not have the ideal 
appearance of Fig. 5.11. Rather, they have a slope as shown In Fig. 5.15 that defines the 
output impedance of the device. The steeper the slope, the less the output impedance and 
the less ideal the transistor. In general, it is desirable to have large output impedances to 
avoid loading down the next stage of a design. If the slope of the curves is extended until 
they reach the horizontal axis, it is interesting to note in Fig. 5.15 that they will all intersect 
at a voltage called the Early voltage. This intersection was first discovered by James M. 
Early in 1952. As the base current increases the slope of the line increases, resulting in an 
increase in output impedance with increase in base and collector current. For a particular 
collector and base current as shown in Fig. 5.15, the output impedance can be found using 
the following equation: 



( 5 . 2 ) 





FIG. 5.15 

Defining the Early voltage and the output impedance of a transistor. 




260 BJT AC ANALYSIS 



Typically, however, the Early voltage is sufficiently large compared with the applied 
collector-to-emitter voltage to permit the following approximation. 




( 5 . 3 ) 



Clearly, since V& is a fixed voltage, the larger the collector current, the less the output 
impedance. 

For situations where the Early voltage is not available the output impedance can be found 
from the characteristics at any base or collector current using the following equation: 



Slope = 



Ay 

Ax 



A I c 1 

A Vce r o 



and 



A V CE 

A Ic 



( 5 . 4 ) 



For the same change in voltage in Fig. 5.15 the resulting change in current A I c is signifi- 
cantly less for r Ql than r Ql , resulting in r Ql being much larger than r oy 

In situations where the specification sheets of a transistor do not include the Early volt- 
age or the output characteristics, the output impedance can be determined from the hybrid 
parameter h oe that is normally plotted on every specification sheet. It is a quantity that will 
be described in detail in Section 5.19. 

In any event, an output impedance can now be defined that will appear as a resistor in 
parallel with the output as shown in the equivalent circuit of Fig. 5.16. 



bo 



e o- 




h 





o c 



O e 



FIG. 5.16 

r e model for the common-emitter transistor configuration 
including effects of r Q . 



The equivalent circuit of Fig. 5.16 will be used throughout the analysis to follow for the 
common-emitter configuration. Typical values of beta run from 50 to 200, with values of 
f3r e typically running from a few hundred ohms to a maximum of 6 kfl to 7 kfl. The output 
resistance r is typically in the range of 40 kll to 50 kfl. 



Common-Base Configuration 

The common-base equivalent circuit will be developed in much the same manner as 
applied to the common-emitter configuration. The general characteristics of the input and 
output circuit will generate an equivalent circuit that will approximate the actual behavior 
of the device. Recall for the common-emitter configuration the use of a diode to represent 
the connection from base to emitter. For the common-base configuration of Fig. 5.17a the 
pnp transistor employed will present the same possibility at the input circuit. The result is 
the use of a diode in the equivalent circuit as shown in Fig. 5.17b. For the output circuit, if 
we return to Chapter 3 and review Fig. 3.8, we find that the collector current is related to 
the emitter current by alpha a. In this case, however, the controlled source defining the 
collector current as inserted in Fig. 5.17b is opposite in direction to that of the controlled 
source of the common-emitter configuration. The direction of the collector current in the 
output circuit is now opposite that of the defined output current. 





/, L 



O C E O- 



-o C 



OB B o~ 



^ / c — cx / e 



-OB 



(a) 



(b) 



FIG. 5.17 

(a) Common-base BJT transistor; (b) equivalent circuit for configuration of (a). 



For the ac response, the diode can be replaced by its equivalent ac resistance determined 
by r e = 26 mV /I E as shown in Fig. 5.18. Take note of the fact that the emitter current 
continues to determine the equivalent resistance. An additional output resistance can be 
determined from the characteristics of Fig. 5.19 in much the same manner as applied to the 
common-emitter configuration. The almost horizontal lines clearly reveal that the output 
resistance r Q as appearing in Fig. 5.18 will be quite high and certainly much higher than that 
for the typical common-emitter configuration. 

The network of Fig. 5.18 is therefore an excellent equivalent circuit for the analysis of 
most common-base configurations. It is similar in many ways to that of the common-emitter 
configuration. In general, common-base configurations have very low input impedance 
because it is essentially simply r e . Typical values extend from a few ohms to perhaps 50 12. 
The output impedance r Q will typically extend into the megohm range. Because the output 
current is opposite to the defined I 0 direction, you will find in the analysis to follow that 
there is no phase shift between the input and output voltages. For the common-emitter 
configuration there is a 180° phase shift. 




-o 

+ 



FIG. 5.18 

Common base r e equivalent circuit. 



, I c (mA) 


y Slope = i 


I E = 4 m A 


f 




I E — 3 m A 


r 




I E = 2 m A 


r 




I E = 1 m A 






I E = 0 m A 


V CB 



FIG. 5.19 

Defining Z Q . 



261 





262 BJT AC ANALYSIS 



Common-Collector Configuration 

For the common-collector configuration, the model defined for the common-emitter configu- 
ration of Fig. 5. 16 is normally applied rather than defining a model for the common-collector 
configuration. In subsequent chapters, a number of common-collector configurations will be 
investigated, and the effect of using the same model will become quite apparent. 

npn versus pnp 

The dc analysis of npn and pnp configurations is quite different in the sense that the currents 
will have opposite directions and the voltages opposite polarities. However, for an ac analy- 
sis where the signal will progress between positive and negative values, the ac equivalent 
circuit will be the same. 

5.5 COMMON-EMITTER FIXED-BIAS 

CONFIGURATION ^ 

The transistor models just introduced will now be used to perform a small-signal ac analy- 
sis of a number of standard transistor network configurations. The networks analyzed rep- 
resent the majority of those appearing in practice. Modifications of the standard 
configurations will be relatively easy to examine once the content of this chapter is reviewed 
and understood. For each configuration, the effect of an output impedance is examined for 
completeness. 

The computer analysis section includes a brief description of the transistor model em- 
ployed in the PSpice and Multisim software packages. It demonstrates the range and depth 
of the available computer analysis systems and how relatively easy it is to enter a complex 
network and print out the desired results. The first configuration to be analyzed in detail is 
the common-emitter fixed-bias network of Fig. 5.20. Note that the input signal V/ is applied 
to the base of the transistor, whereas the output V 0 is off the collector. In addition, recognize 
that the input current is not the base current, but the source current, and the output current 
I 0 is the collector current. The small-signal ac analysis begins by removing the dc effects 
of Vcc and replacing the dc blocking capacitors C\ and C 2 by short-circuit equivalents, 
resulting in the network of Fig. 5.21. 



Vcc 





FIG. 5.20 FIG. 5.21 

Common-emitter fixed-bias configuration. Network of Fig. 5.20 following the removal 

of the effects ofVco aR d C^ 

Note in Fig. 5.21 that the common ground of the dc supply and the transistor emitter 
terminal permits the relocation of R B and R c in parallel with the input and output sections 
of the transistor, respectively. In addition, note the placement of the important network 
parameters Z h Z 0 , I b and I 0 on the redrawn network. Substituting the r e model for the 
common-emitter configuration of Fig. 5.21 results in the network of Fig. 5.22. 

The next step is to determine /3, r e , and r Q . The magnitude of (5 is typically obtained 
from a specification sheet or by direct measurement using a curve tracer or transistor 




Substituting the r e model into the network of Fig. 5.21. 



testing instrument. The value of r e must be determined from a dc analysis of the system, 
and the magnitude of r Q is typically obtained from the specification sheet or characteristics. 
Assuming that /3, r e , and r Q have been determined will result in the following equations for 
the important two-port characteristics of the system. 



Zj Figure 5.22 clearly shows that 




ohms 



( 5 . 5 ) 



For the majority of situations R B is greater than fir e by more than a factor of 10 (recall 
from the analysis of parallel elements that the total resistance of two parallel resistors is 
always less than the smallest and very close to the smallest if one is much larger than the 
other), permitting the following approximation: 




R B ^10p r e 



ohms 



( 5 . 6 ) 



Z 0 Recall that the output impedance of any system is defined as the impedance Z 0 
determined when Vj = 0. For Fig. 5.22, when V- L = 0, f = 7^ = 0, resulting in an open- 
circuit equivalence for the current source. The result is the configuration of Fig. 5.23. 
We have 



RcVo 



ohms 



If r Q > 10R C , the approximation RcV 0 = Rc is frequently applied, and 



( 5 . 7 ) 




r o >\0R c 



( 5 . 8 ) 



A v The resistors r Q and R c are in parallel, and 



but 


Vo = - Mficko ) 

1 =Tl 
b (3r e 


so that 




and 


. _ V 0 _ (Rc\\r 0 ) 


*2* 

1 

1 

> 

K 



If r Q > lORc, so that the effect of r Q can be ignored, 




( 5 . 9 ) 



( 5 . 10 ) 



COMMON-EMITTER 263 
FIXED-BIAS 
CONFIGURATION 




FIG. 5.23 

Determining Z Q for the network 
of Fig. 5.22. 



Note the explicit absence of /3 in Eqs. (5.9) and (5.10), although we recognize that /3 must 
be utilized to determine r p . 




264 BJT AC ANALYSIS 



Phase Relationship The negative sign in the resulting equation for A v reveals that a 180° 
phase shift occurs between the input and output signals, as shown in Fig. 5.24. The is a 
result of the fact that establishes a current through R c that will result in a voltage across 
R c , the opposite of that defined by V 0 . 



Vcc 





Demonstrating the 180° phase shift between input and output waveforms. 



EXAMPLE 5.1 For the network of Fig. 5.25: 

a. Determine r e . 

b. Find Z t (with r 0 = o°ft). 

c. Calculate Z Q (with r Q = o°ft). 

d. Determine A v (with r Q = o°ft). 

e. Repeat parts (c) and (d) including r Q = 50 kft in all calculations and compare results. 




FIG. 5.25 

Example 5.1. 



Solution: 

a. DC analysis: 



c. 



V C c - V, 



BE 



12 V - 0.7 V 



L B 



24.04 ii A 



R b 470 kft 

I E = 08 + 1 )I B = (101)(24.04 /x,A) = 2.428 mA 
26 mV 26 mV 

= 10.71 il 



e I E 2.428 mA 
fir e = (100X10.71 ft) = 1.071 kft 

Z ; = R B \fir e = 470 kfl|| 1.071 m = 1.07 kH 



Z 0 = Rc = 3 kil 

_ _Rc _ 3 m 

v ~ r e ~ 10.71 a 



= -280.11 



VOLTAGE-DIVIDER BIAS 265 



e. Z 0 
A v 



= r n \\R r = 50 Mill 3 kO = 2.83 kll vs. 3 M2 



r 0 \\R c _ 2.83 kll 
r e ~ 10.71 12 



= -264.24 vs. -280.11 



5-6 VOLTAGE-DIVIDER BIAS ^ 

The next configuration to be analyzed is the voltage-divider bias network of Fig. 5.26. 
Recall that the name of the configuration is a result of the voltage-divider bias at the input 
side to determine the dc level of V B . 

Substituting the r e equivalent circuit results in the network of Fig. 5.27. Note the absence 
of R e due to the low-impedance shorting effect of the bypass capacitor, C E - That is, at the 
frequency (or frequencies) of operation, the reactance of the capacitor is so small compared 
to R e that it is treated as a short circuit across R E . When Vcc is set to zero, it places one 
end of R\ and Rq at ground potential as shown in Fig. 5.27. In addition, note that R\ and 
7?2 remain part of the input circuit, whereas Rq is part of the output circuit. The parallel 
combination of R\ and R^ is defined by 



R' = 



R\Ri 
R\ R2 



( 5 . 11 ) 



Zj From Fig. 5.27 

z, = R’\\pr e 



( 5 . 12 ) 



V CC 




FIG. 5.26 

Voltage -divider bias configuration. 




FIG. 5.27 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.26. 




266 BJT AC ANALYSIS 



Z 0 From Fig. 5.27 with V 7 , set to 0 V, resulting in I b = 0 ju-A and /3//, = 0 mA, 



Ifr 0 > \0R C , 



RcVo 




r o >10R c 



( 5 . 13 ) 

( 5 . 14 ) 



A v Because R c and r Q are in parallel, 





V 0 = -(plbXRcWO 


and 


i =2l 
b fir e 


so that 


v ° = 


and 


. _ V o _ -RcWo 


25 

1 

1 ^ 
1 

> 



( 5 . 15 ) 



which you will note is an exact duplicate of the equation obtained for the fixed-bias con- 
figuration. 

For r Q > 107? c , 



( 5 . 16 ) 

r o >10R c 

Phase Relationshi The negative sign of Eq. (5.15) reveals a 180° phase shift between 
V 0 and V, 




EXAMPLE 5.2 For the network of Fig. 5.28, determine: 

a. r e . 

b. Z;. 

c. z 0 (r a = oo a). 

d. A v (r 0 = oo Cl). 

e. The parameters of parts (b) through (d) if r Q = 50 kll and compare results. 



22 V 




FIG. 5.28 
Example 5.2. 



Solution: 

a. DC: Testing (3R E > 10/? 2 , 

(90)(1.5 kft) > 10(8.2 kft) 

135 kft > 82 kft {satisfied) 
Using the approximate approach, we obtain 



V B = 
V E = 



R 9 



Vcc — 



(8.2 kft)(22 V) 



R 1 + R 2 " 56 kft + 8.2 kft 

V B - V BE = 2.81 V - 0.7 V = 2.11 V 



= 2.81V 



Ve 



Ie — : t- - — 

Rf 



2.11V 
1.5 kft 



= 1.41 mA 



26 mV 26 mV 



r„ = 



= 18.44 ft 



I E 1.41 mA 
R x \\R 2 = (56 kft)||(8.2 kft) = 7.15 kft 
R'\\l3r e = 7.15 kft ||(90)(18.44 ft) = 7.15 kft || 1.66 kft 

1.35 kft 
R c = 6.8 kft 

Rc _ 6.8 kft 

r e ~ 18.44 ft 

1.35 kft 

R c \\r 0 = 6.8 kft || 50 kft = 5.98 kft vs. 6.8 kft 



b. R' = 

Z, = 

c. Z 0 = 

d. A v = — — = — 

e. Z ( 

Z n 



= -368.76 



A„ = 



Rr 



5.98 kft 
18.44 ft 



= -324.3 vs. -368.76 



There was a measurable difference in the results for Z 0 and A v , because the condition 



r Q > 107? c was not satisfied. 



CE EMITTER-BIAS 267 
CONFIGURATION 



5-7 CE EMITTER-BIAS CONFIGURATION ^ 

The networks examined in this section include an emitter resistor that may or may not be 
bypassed in the ac domain. We first consider the unbypassed situation and then modify the 
resulting equations for the bypassed configuration. 



Unbypassed 

The most fundamental of unbypassed configurations appears in Fig. 5.29. The r e equiva- 
lent model is substituted in Fig. 5.30, but note the absence of the resistance r Q . The effect 
of r Q is to make the analysis a great deal more complicated, and considering the fact that in 



Fee 





FIG. 5.29 

CE emitter-bias configuration. 



FIG. 5.30 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.29. 



268 BJT AC ANALYSIS 




FIG. 5.31 

Defining the input impedance of a 
transistor with an unbypassed 
emitter resistor. 



most situations its effect can be ignored, it will not be included in the present analysis. 
However, the effect of r Q will be discussed later in this section. 

Applying Kirchhoff s voltage law to the input side of Fig. 5.30 results in 

Vi — hP r e + 

or V t = I b f3r e + (/3 + I)I b R E 

and the input impedance looking into the network to the right of R B is 

Zb = ~r = pr e + (p + 1 )R e 

L b 

The result as displayed in Fig. 5.31 reveals that the input impedance of a transistor with 
an unbypassed resistor R E is determined by 



Z b — P r e + (P + 1 )R e 



( 5 . 17 ) 



Because p is normally much greater than 1, the approximate equation is 

Z b = pr e + PRe 



and 



Z b = P(r e + R e ) 



Because R E is usually greater than r e , Eq. (5.18) can be further reduced to 



Z b = pR E 



Zj Returning to Fig. 5.30, we have 



Z[ — Rp \\Z b 



( 5 . 18 ) 

( 5 . 19 ) 

( 5 . 20 ) 



Z 0 With V t set to zero, I b = 0, and pi b can be replaced by an open-circuit equivalent. 
The result is 



A v 



and 



with 




4 z 

z b 

Vo = -l 0 Rc = -piiEc 

- Ad Rc 




PRc 

Z b 



Substituting Z b = P(r e + R E ) gives 

= K s Rc 

V V t r e + R e 



and for the approximation Z b = pR E , 




Rc 

Re 



( 5 . 21 ) 



( 5 . 22 ) 



( 5 . 23 ) 



( 5 . 24 ) 



Note the absence of P from the equation for A v demonstrating an independence in variation 
of p. 



Phase Relationship The negative sign in Eq. (5.22) again reveals a 180° phase shift 
between V 0 and V b 



Effect of r 0 The equations appearing below will clearly reveal the additional complexity 
resulting from including r Q in the analysis. Note in each case, however, that when certain 
conditions are met, the equations return to the form just derived. The derivation of each 
equation is beyond the needs of this text and is left as an exercise for the reader. Each 
equation can be derived through careful application of the basic laws of circuit analysis 
such as Kirchhoff’s voltage and current laws, source conversions, Thevenin’s theorem, 
and so on. The equations were included to remove the nagging question of the effect of r Q 
on the important parameters of a transistor configuration. 








(fi + 1) + Rc/r a 




z b — Pr e + 


. 1 + (Rc + Re) fro . 


Re 



( 5 . 25 ) 



Because the ratio Rc/r 0 is always much less than (fi + 1), 

03 + We 



Z b = P r e + 



For r 0 > 10 (R c + R E ), 



1 + (R c + R E )/r 0 

Z b — P r e + (P + We 



which compares directly with Eq. (5.17). 

In other words, if r g > 10(7? c + R E ), all the equations derived earlier result. Because 
/3 + 1 s= /3, the following equation is an excellent one for most applications: 



z b = Pfre + R e ) 



r 0 —lQ( R c +R E) 



( 5 . 26 ) 



CE EMITTER-BIAS 269 
CONFIGURATION 



Zo 




( 5 . 27 ) 



However, r a » r e , and 



z o = Rc 



1 + 



I 3 



1 + 



Rf 



which can be written as 



RcVo 



1 + 



1 

i + ^ 

/3 Re- 



Typically 1//3 and r e /R E are less than one with a sum usually less than one. The result 
is a multiplying factor for r Q greater than one. For (3 = 100, r e = 10 H, and R E = 1 kft, 



J_ J_ 10H 0.02 

is + r e ioo + iooo a 

and Z 0 = R c \\51r 0 

which is certainly simply R E . Therefore, 




Any level of r Q 



( 5 . 28 ) 



which was obtained earlier. 



270 BJT AC ANALYSIS 



A v 



m c 


r e 

1 + — 

L r o\ 


Rc 

+ — 

r o 


1 

1^ 

1 

IN 


v V: R c 

' 1 + — 
r a 



The ratio — « 1, and 

r 0 




PRc + Rc 

Z b r Q 



1 




For r 0 > 107? c , 




r o >10R c 



( 5 . 29 ) 



( 5 . 30 ) 



as obtained earlier. 

Bypassed 

If R e of Fig. 5.29 is bypassed by an emitter capacitor C E , the complete r e equivalent model 
can be substituted, resulting in the same equivalent network as Fig. 5.22. Equations (5.5) 
to (5.10) are therefore applicable. 



EXAMPLE 5.3 For the network of Fig. 5.32, without C E (unbypassed), determine: 



a. r e . 

b. Z;. 

c. Z 0 . 

d. A v . 



20 V 




Solution: 

a. DC: 

= Vcc ~ Vbe = 20V - 0.7V 

B R B + (P + 1 )R e 470 kl4 + (121)0.56 kft 
I E = U 3 + 1 )I B = (121X35.89 /xA) = 4.34 mA 
26 mV = ^ 6 m^ = 5>99ft 
I E 4.34 mA 



35.89 fiA 



and r. 



b. Testing the condition r 0 > 10(/? c + R E ), we obtain 



40 ka > 10(2.2 ka + 0.56 ka) 

40 ka > 10(2.76 kO) = 27.6 Ml (satisfied) 



CE EMITTER-BIAS 271 
CONFIGURATION 



Therefore, 



and 



Z b = P(r e + Re) = 120(5.99 a + 560 a) 
= 67.92 ka 

Z, = R B \\Z b = 470 ka || 67.92 ka 

= 59.34 kft 



c. Z a = R c = 2.2 ka 

d. r 0 ^ 1 07? c is satisfied. Therefore, 



V 0 f3R c (120)(2.2 ka) 



Vi Z b 67.92 ka 



= -3.89 

compared to —3.93 using Eq. (5.20): A v = —Rq/Re- 



EXAMPLE 5.4 Repeat the analysis of Example 5.3 with C E in place. 

Solution: 

a. The dc analysis is the same, and r e = 5.99 H. 

b. R e is “shorted out” by C E for the ac analysis. Therefore, 

Z, = R B \\Z b = R B \\pr e = 470ka||(120)(5.99 a) 
= 470 ka ||718.8 a = 717.70 a 

c. Z 0 = R c = 2.2 ka 



EXAMPLE 5.5 For the network of Fig. 5.33 (with C E unconnected), determine (using 
appropriate approximations): 




= — 367.28 (a significant increase) 




16 V 




I 



Vi°- 



X 



FIG. 5.33 
Example 5.5. 



272 BJT AC ANALYSIS 



Solution: 



a. Testing f3R E > 107? 2 , 



we have 



(210X0.68 kfl) > 10(10 kft) 
142.8 ka > 100 ka ( satisfied ) 






Ro 



~Vcc ~ 



io ka 



-(16 V) = 1.6 V 



R 1 + R 2 ' ^ 90 ka + 10 ka 

V E = V B - V BE = 1.6 V - 0.7 V = 0.9 V 
V E 0.9 V 



7/7 — — 

h Ri 



0.68 ka 



= 1.324 mA 



= 



26 mV 26 mV 



= 19.64 a 



I E 1.324 mA 

b. The ac equivalent circuit is provided in Fig. 5.34. The resulting configuration is differ- 
ent from Fig. 5.30 only by the fact that now 

R B = R' = /?! ||/? 2 = 9ka 




FIG. 5.34 

The ac equivalent circuit of Fig. 5.33. 



The testing conditions of r 0 S 1 0(R E + R E ) and r a s I QR C are both satisfied. Using 
the appropriate approximations yields 

s j3R E = 142.8 ka 
Z ( - = R B \\Z b = 9 ka|| 142.8 ka 

= 8.47 kft 



c. Z 0 = R c = 2.2 ka 



d. A v 



R c 

Re 



2.2 ka 
0.68 ka 



EXAMPLE 5.6 Repeat Example 5.5 with C E in place. 



Solution: 



a. The dc analysis is the same, and r e = 19.64 a. 

b. Z b = (3r e = (210X19.64 a) = 4.12 ka 

Z ; = R B \\z b = 9ka||4.12ka 

= 2.83 ka 

c. Z 0 = R c = 2.2 ka 



d. A v 




2.2 ka 
19.64 a 



— 112.02 (a significant increase) 



Another variation of an emitter-bias configuration is shown in Fig. 5.35. For the dc 
analysis, the emitter resistance is R El + R El , whereas for the ac analysis, the resistor R E in 
the equations above is simply R El with R El bypassed by C E . 



EMITTER-FOLLOWER 273 
CONFIGURATION 




i 



FIG. 5.35 

An emitter-bias configuration with a 
portion of the emitter-bias resistance 
bypassed in the ac domain. 



5.8 EMITTER-FOLLOWER CONFIGURATION 




When the output is taken from the emitter terminal of the transistor as shown in Fig. 5.36, 
the network is referred to as an emitter-follower. The output voltage is always slightly less 
than the input signal due to the drop from base to emitter, but the approximation A v = 1 
is usually a good one. Unlike the collector voltage, the emitter voltage is in phase with the 
signal Vf. That is, both V 0 and V; attain their positive and negative peak values at the same 
time. The fact that V 0 “follows” the magnitude of V; with an in-phase relationship accounts 
for the terminology emitter-follower. 



The most common emitter-follower configuration appears in Fig. 5.36. In fact, because 
the collector is grounded for ac analysis, it is actually a common-collector configuration. 
Other variations of Fig. 5.36 that draw the output off the emitter with V 0 = V t will appear 
later in this section. 

The emitter-follower configuration is frequently used for impedance-matching pur- 
poses. It presents a high impedance at the input and a low impedance at the output, which 
is the direct opposite of the standard fixed-bias configuration. The resulting effect is much 
the same as that obtained with a transformer, where a load is matched to the source imped- 
ance for maximum power transfer through the system. 

Substituting the r e equivalent circuit into the network of Fig. 5.36 results in the network 
of Fig. 5.37. The effect of r Q will be examined later in the section. 




FIG. 5.36 

Emitter-follower configuration. 



274 BJT AC ANALYSIS 




Substituting the r e equivalent circuit into the ac 
equivalent network of Fig. 5.36. 




Zj The input impedance is determined in the same manner as described in the preceding 
section: 



Z/ — RsWZb 



with 



or 



and 



Z b ~ P r e + (P + IWe 



Z b = P(r e + R e ) 



Z b = (3 R e 



Rt7^>v p 



(5.31) 

(5.32) 

(5.33) 

(5.34) 



Z 0 The output impedance is best described by first writing the equation for the current l b , 

Zb 

and then multiplying by Q3 + 1) to establish I e . That is, 



4 = 03 + 1)4 = 03 + \yf 



Substituting for Z b gives 

or 

but 

and 

so that 



4 = 



os + m 



4 = 



P>'e + (P + 1 We 

Vi 

\P r e/(P + 1 )] + Re 

(13 + 1) = 13 

13 1 ' e _ (3r e = 

j3 + 1 _ j3 Ve 



4 



Vi 



>' e + R e 



(5.35) 



If we now construct the network defined by Eq. (5.35), the configuration of Fig. 5.38 
results. 

To determine Z Q , V t is set to zero and 



Zo = Re \\ r e 



FIG. 5.38 

Defining the output impedance for 
the emitter-follower configuration. 



(5.36) 




Because R E is typically much greater than r e , the following approximation is often applied: 



EMITTER-FOLLOWER 275 
CONFIGURATION 




( 5 . 37 ) 



A v Figure 5.38 can be used to determine the voltage gain through an application of the 
voltage-divider rule: 






R E Vi 

Re + r e 



and 



A 



y 0 Re 

Vi R E + r e 



Because R E is usually much greater than r e , R E + r e = R E and 




( 5 . 38 ) 



( 5 . 39 ) 



Phase Relationship As revealed by Eq. (5.38) and earlier discussions of this section, V„ 
and Vf are in phase for the emitter-follower configuration. 



Effect of r 0 

Z; 




If the condition r 0 > 107? £ is satisfied, 

Zb = fir e + (fi + 1 )R e 
which matches earlier conclusions with 



Zb = fi(r e + R e ) 



r„^lOR E 



( 5 . 40 ) 



( 5 . 41 ) 



Z 0 



Zo 



r o II Re 



(fi + 1 ) 



Using /3 + 1 = /3, we obtain 
and because r 0 » r e , 



Zq r 0 ||/0i|| v e 



Z 0 ^ 



Rf 



Any 



A v 




( 5 . 42 ) 



( 5 . 43 ) 



( 5 . 44 ) 



If the condition r 0 > 107?^ is satisfied and we use the approximation (3 + 1 = /3, we find 



A = 



fiRs 

Zb 



276 BJT AC ANALYSIS 



But 



so that 



and 



= p(r e + R e ) 

A a PR E 

v (3(r e + R e ) 



A v = 



+ R E 



r o >10/f £ 



( 5 . 45 ) 



EXAMPLE 5.7 For the emitter-follower network of Fig. 5.39, determine: 



b. Z,. 

c. Z 0 . 

d. Ay. 

e. Repeat parts (b) through (d) with r 0 = 25 kfl and compare results. 



12 V 




FIG. 5.39 
Example 5. 7. 



Solution: 



a. Ir — 



Vcc - V, 



BE 



R B + (P + 1)^£ 
12 V - 0.7 V 



= 20.42 nA 



220 kfl + (101)3.3 kfl 

h = 03 + l)/s 

= (101)(20.42 /rA) = 2.062 mA 
26 mV 26 mV 

r e = = = 12.61 fl 

e 1 E 2.062 mA 

b. Z b = (ir e + (ft + 1 )R e 

= (100X12.61 fl) + (101X3.3 kfl) 
= 1.261 kfl + 333.3 kfl 
= 334.56 kfl = /3R e 
Z i = R B \\Z b = 220 kfl || 334.56 kfl 
= 132.72 kfl 

c. Z c = R E \\r e = 3.3 kfl || 12.61 fl 

= 12.56 fl = r„ 



" O 



Rt. 



3.3 kfl 



Vi Re + r e 

= 0.996 s 1 



3.3 kfl + 12.61 fl 



d. A, 



COMMON-BASE 277 
CONFIGURATION 



e. Checking the condition r Q > 107?£, we have 

25 kll > 10(3.3 kll) = 33 kll 

which is /tor satisfied. Therefore, 

08 + i)/?£ (ioo + 1)3.3 m 

Z b = f3r e + — ^ = (100)(12.61 12) + 



with 



Re 

1 + — 
r n 



1 + 



3.3 kI2 



0 25 kll 

= 1.261 kll + 294.43 kll 
= 295.7 kll 

Z, = R B \z b = 220 kfl || 295.7 kll 

= 126.15 kil vs. 132.72 kll obtained earlier 
Z 0 = Tag'll r e = 12.5612 as obtained earlier 

08 + 1 )R E /Z b (100 + 1)(3.3 kI2)/295.7 kll 



R E 

1 + — 
r o J 

0.996 = 1 



1 + 



3.3 kll 
25 kll 



matching the earlier result. 



In general, therefore, even though the condition r Q > 107? £ is not satisfied, the results 
for Z Q and A v are the same, with Z t only slightly less. The results suggest that for most ap- 
plications a good approximation for the actual results can be obtained by simply ignoring 
the effects of r Q for this configuration. 

The network of Fig. 5.40 is a variation of the network of Fig. 5.36, which employs 
a voltage-divider input section to set the bias conditions. Equations (5.31) to (5.34) are 
changed only by replacing R B by R f = Ri ||/? 2 . 

The network of Fig. 5.41 also provides the input/output characteristics of an emitter- 
follower, but includes a collector resistor R c . In this case R B is again replaced by the parallel 
combination of Ri and R 2 . The input impedance Z t and output impedance Z Q are unaffected 
by R c because it is not reflected into the base or emitter equivalent networks. In fact, the 
only effect of R c is to determine the g-point of operation. 



v cc 




FIG. 5.40 

Emitter-follower configuration with a 
voltage -divider biasing arrangement. 



v cc 




Emitter-follower configuration with 
a collector resistor R c . 



5-9 COMMON-BASE CONFIGURATION ^ 

The common-base configuration is characterized as having a relatively low input and a high 
output impedance and a current gain less than 1 . The voltage gain, however, can be quite 
large. The standard configuration appears in Fig. 5.42, with the common-base r e equivalent 
model substituted in Fig. 5.43. The transistor output impedance r Q is not included for the 



— T 





FIG. 5.42 

Common-base configuration. 



FIG. 5.43 

Substituting the r e equivalent circuit into the ac equivalent network 
of Fig. 5.44. 



common-base configuration because it is typically in the megohm range and can be ignored 
in parallel with the resistor R c . 



h 



Z; — ReVc 



Z n — Rc 



( 5 . 46 ) 

( 5 . 47 ) 



with 
so that 

and 



Vo ~ ~ ( h)Rc ~ OtI e Rc 

i = * 

1 p 



v n = a\ y )R C 



A _ Yo_ _ a ^c __ Rc 

v ~~ V: ~ r e - r e 



4 = h 



Aj Assuming that R E r e yields 
and I n = —otl,, = —a/, 

with 



In 



A; = — = -a = -1 

h 



( 5 . 48 ) 



( 5 . 49 ) 



Phase Relationship The fact that A v is a positive number shows that V 0 and V t are in 
phase for the common-base configuration. 



Effect of r 0 For the common-base configuration, r Q = 1 jh^ is typically in the megohm 
range and sufficiently larger than the parallel resistance R c to permit the approximation 

r o\\ R c — Rc 



EXAMPLE 5.8 For the network of Fig. 5.44, determine: 



a. r e . 

b. Z;. 

c. Z Q . 

d. A v . 

e. A t . 




V 

a =0.98 R 



r Q = 1 MQ 



10 pF 




3+ 



-o 

+ 



-o 



278 



FIG. 5.44 

Example 5.8. 




Solution: 



a. Ip — 



Vee-Vbe 2 V — 0.7 V 1.3 V 



Re 
26 mV 



lkO 



lkO 



= 1.3 rnA 



26 mV 



e I E 1.3 mA 

b. Z t = R E \\r e = lkft||20n 

= 19.61 n = r e 

c. Z 0 = R c = 5 kll 

R c 5 kll 

d. A v = — — — — = 250 

v r e 20 12 

e. A 7 = -0.98 = -1 



= 2011 



5-10 COLLECTOR FEEDBACK CONFIGURATION ^ 

The collector feedback network of Fig. 5.45 employs a feedback path from collector to 
base to increase the stability of the system as discussed in Section 4.6. However, the sim- 
ple maneuver of connecting a resistor from base to collector rather than base to dc supply 
has a significant effect on the level of difficulty encountered when analyzing the network. 

Some of the steps to be performed below are the result of experience working with 
such configurations. It is not expected that a new student of the subject would choose 
the sequence of steps described below without taking a wrong step or two. Substituting the 
equivalent circuit and redrawing the network results in the configuration of Fig. 5.46. The 
effects of a transistor output resistance r Q will be discussed later in the section. 



COLLECTOR FEEDBACK 279 
CONFIGURATION 




FIG. 5.45 

Collector feedback configuration. 



Pr e \ PI„ 

1 






* Vn 



FIG. 5.46 

Substituting the r e equivalent circuit into the ac 
equivalent network of Fig. 5.45. 






and 

but 

with 

so that 



/. = /'+ p I b 

r = v "- Vi 



r = - 



r f 

Vo = -I 0 R C = -(/' + Pb)Rc 
Vi = I b pr e 

(/' + p Ib)R c ~ hPr e I'Rc PhRc hPr e 



Rf 



Rf 



Rf 



Rf 



which when rearranged in the following: 

( Rc\ 



(Rc + r e) 



280 BJT AC ANALYSIS 



and finally, 



(Rc + r e) 



/' = ~Ph 



Rr + Rf 



Vi 

Now Z, = — : 
J-i 



and 



/; . = i b - 7' = 4 + pi b 



(Re + r e) 
+ Rf 



or 



Ii = I b 1 + j8 



, (*C + r e) 



R c + Rf , 

Substituting for V,- in the above equation for Z, leaves 



I-*- 



hfir e 



fir e 



h\ 1 + P 



(*c + r e ) 



1 + )8 



(j?c + r e ) 

*C + ^F 



Since 



or 



Z/ = 



)8r e 



P Rc 

Rc + ^F 



1 + 




( 5 . 50 ) 



Z 0 If we set V; to zero as required to define Z 0 , the network will appear as shown in Fig. 5.47. 
The effect of f3r e is removed, and R F appears in parallel with R c and 



Z 0 = Rc\\Rf 



( 5 . 51 ) 



Rf 




FIG. 5.47 

Defining Z 0 for the collector feedback configuration. 



A v 



or 

Then 



For R c » r e 



V 0 = -i 0 Rc = + Ph)Rc 

( (Rc + r e ) 

= - -Pb n , „ + Ph 



v 0 = 



-Ph\ i 



Rc + r f 

_ (R C + r e 
Rc + Rf 



Rr 



I R c 



A v 



Yfl 

V, 




(R C + r e) 
Rc + r f 







A _ + >' e ) \Rc 

V Rc + R F J r e 



V 



V Rc + Rp 



Rc 

r e 



A, 



or 



and 



A„ = - 



(*£ + Rf ~ ^)/?c 

tfc + r e 



A v = ~ 



( R r ) 


\— 


\R C + Rf) 


] r e 



For Rf ''i :> /\* ( ■ 



R c 

A '-~f 

' P 



( 5 . 52 ) 



( 5 . 53 ) 



COLLECTOR FEEDBACK 281 
CONFIGURATION 



Phase Relationship The negative sign of Eq. (5.52) indicates a 180° phase shift between 
V 0 and V r 



Effect of r 0 

Zj A complete analysis without applying approximations results in 



1 + 



RcWo 



z, = 



Rf 



J_ J_ Rc Vo RAtq 

P r e Rf fir e R F R F r e 



Applying the condition r 0 > 107? c , we obtain 

Z; = 



Rc 

l + — 

R f 



l l 

— + h 



Rc 



Applying R c » r e and — , 

Rc 



Z, = 



1 + 



7? 



fJ 



+ 



Rf + 

Rf 



r e 


R c] 

1 + — 
R F - 




1 1 


Rc 


" 


— + 


r e + — 


+ R F 


(3 R f 


P 


_ 



1 | *c 

P Rf 



R f + (1R C 1 / R 






Rr 



( 5 . 54 ) 



but, since R F typically » R c , R F + R c = R F and 



/ 3\R f + Rc J Rc “L R F 

R f 



R f + R c 



= 1 




( 5 . 55 ) 



r 0 »i? c , R F >R C 



as obtained earlier. 



Z 0 Including r Q in parallel with R c in Fig. 5.47 results in 

— r o\\^c\\^F 



For r 0 > 107? c , 



Z 0 = 



r o >10R c 



as obtained earlier. For the common condition of R F » R& 




y 0 ^- 10 Rp,Rp^> Rp 



( 5 . 56 ) 

( 5 . 57 ) 

( 5 . 58 ) 



282 BJT AC ANALYSIS 



For r Q > 10 R c , 



and for R F » R c 



as obtained earlier. 



A v = - 



rf yelk 

RcWo + Rf) r e 



Rr \R ( 



R C + RfJ r e 



r o ^l0R c 



Rc 

K = 

r P 



r o— 10 Rc, Rf— r c 



( 5 . 59 ) 



( 5 . 60 ) 



( 5 . 61 ) 



EXAMPLE 5.9 For the network of Fig. 5.48. determine: 

a. r„. 

b. Z ; . 

C. Zg. 

d. A,. 

e. Repeat parts (b) through (d) with r a = 20 kQ and compare results. 



9 V 




Solution: 



a. In = 



Vcc _ Vbe 



9 V - 0.7 V 



R f + (3R C 1 80 k.Q + (200)2.7 kH 

= 11.53 ju-A 

Ie= (fi + l)/s = (201X11.53 il A) = 2.32 mA 
26 mV 26 mV 



b. Z, = 



= 11.21 ft 

I F 2.32 mA 

r. 11.21ft 



11.21 ft 



1 

- + 



R 



c 



1 2.7 kft 0.005 + 0.0148 

+ 



13 R c + R f 200 182.7 kft 

11.21ft 

= — — — = 566.16 ft 

0.0198 

c. Z 0 = Relief = 2.7 kft || 180 kft = 2.66 kft 

R c 2.7 kft 

d. A v = — - = — = -240.86 

v r e 11.21ft 



COLLECTOR FEEDBACK 283 
CONFIGURATION 



e. Z{. The condition r Q > 107? c is not satisfied. Therefore, 

RcWo 



1 + 



z, = 



Rf 



1 + 



2.7 kn || 20 kfl 

180 m 



1 ! 1 | R cVo , R c\Vo 



1 



1 



2.7 kfl II 20 kfl 



j3r e R f j3r e R F R F r e (200)(1 1.21) 180kfl (200)(1 1.21 fl)(180 kfl) 

2.38 kfl 

180 kfl 1+0.013 



1 + 



0.45 X 10“ 3 + 0.006 X 10“ 3 + 5.91 X 10“ 6 + 1.18 X 10“ 3 1.64 X 10“ 3 

= 617.7 fl vs. 566.16 fl above 



u 

Z 0 = rJ/? c ||tf F = 20 kfl || 2.7 kfl || 180 kfl 



= 2.35 kfl vs. 2.66 kll above 






Ay 






1 

1 


180 kfl 


2.38 kfl 


r o "b RpJ r e 


.2.38 kfl + 180 kfl. 


11.21 



= -[0.987] 212.3 

= -209.54 



For the configuration of Fig. 5.49, Eqs. (5.61) through (5.63) determine the variables of 
interest. The derivations are left as an exercise at the end of the chapter. 



v cc 




FIG. 5.49 

Collector feedback configuration with an emitter resistor R E . 






Zo 



A v 



J_ ( Re + Rc) 

_P RjT 



( 5 . 62 ) 




( 5 . 63 ) 



( 5 . 64 ) 



2.7 kfl || 20 kfl 
(180 kfl)(l 1 .21 fl) 



284 BJT AC ANALYSIS 



5.1 1 COLLECTOR DC FEEDBACK CONFIGURATION 



The network of Fig. 5.50 has a dc feedback resistor for increased stability, yet the capacitor 
C 3 will shift portions of the feedback resistance to the input and output sections of the net- 
work in the ac domain. The portion of R F shifted to the input or output side will be deter- 
mined by the desired ac input and output resistance levels. 



Fee 




At the frequency or frequencies of operation, the capacitor will assume a short-circuit 
equivalent to ground due to its low impedance level compared to the other elements of the 
network. The small-signal ac equivalent circuit will then appear as shown in Fig. 5.51. 



I t 




R' 



FIG. 5.51 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.50. 



A = RfMe 

*0 

Z o = Rc\\ R F 2 \\ r o 



For r a s ] 0R C , 



A v 

and 



Z 0 = *cll*F2 



r o >10/f c 



R' — r o\\RF 2 \\Rc 

v 0 = ~pi h R' 



( 5 . 65 ) 

( 5 . 66 ) 

( 5 . 67 ) 



but 



and V„ = ~/3 R' 

fir e 

so that 



COLLECTOR 285 
DC FEEDBACK 
CONFIGURATION 






Vo 

Vi 



r o\\ R F 2 \\ R C 

r e 



( 5 . 68 ) 



For r 0 > 107? c , 



( 5 . 69 ) 

r o >\0R c 

Phase Relationship The negative sign in Eq. (5.68) clearly reveals a 180° phase shift 
between input and output voltages. 



V, 



Rf 2 || R C 



EXAMPLE 5.10 For the network of Fig. 5.52, determine: 



a. r„. 

b. Z ( . 

c. Z 0 . 

d. A v . 

e. V 0 if Vj = 2 mV 



12 V 




Solution: 

^ , Vcc ~ Vbe 

a. DC: Id = 

R f + f3R c 

_ 12 V - 0.7 V 

~~ (120 ka + 68 kfl) + (140)3 kD 

= iL3V =18 . 6M 

608 ka ^ 

Ie= 08 + 1 )I B = (141X18.6 /rA) 

= 2.62 mA 

26 mV 26 mV 

r e = — = — — - = 9.92 ft 

I F 2.62 mA 

b. /3r e = (140)(9.92a) = 1.39 ka 

The ac equivalent network appears in Fig. 5.53. 
Z ; = R F] \\/3r e = 120 ka|| 1.39 ka 

= 1.37 kft 



286 BJT AC ANALYSIS 




FIG. 5.53 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.52. 



c. Testing the condition r Q > 10 R& we find 

30 kll > 10(3 kO) = 30 m 

which is satisfied through the equals sign in the condition. Therefore, 
Z 0 = R c \\Rf 2 = 3 kll 1 68 kll 

= 2.87 kil 

d. r Q > 1 07? c ; therefore, 

Rf 2 \\R c 68 kll || 3 kll 
Av “ ~i~ = 9.92 n 

2.87 k D, 

= ~ 9.92 a 

= -289.3 

V 0 

e. | A v | = 289.3 = -y 

w 

V 0 = 289.3 V/ = 289.3(2 mV) = 0.579 V 



5-12 EFFECT OF R L AND R s ^ 

All the parameters determined in the last few sections have been for an unloaded amplifier 
with the input voltage connected directly to a terminal of the transistor. In this section the 
effect of applying a load to the output terminal and the effect of using a source with an 
internal resistance will be investigated. The network of Fig. 5.54a is typical of those inves- 
tigated in the previous section. Because a resistive load was not attached to the output ter- 
minal, the gain is commonly referred to as the no-load gain and given the following 
notation: 



V NL 



Vi 



( 5 . 70 ) 



In Fig. 5.54b a load has been added in the form of a resistor R L , which will change the 
overall gain of the system. This loaded gain is typically given the following notation: 



( 5 . 71 ) 

with R l 

In Fig. 5.54c both a load and a source resistance have been introduced, which will have 
an additional effect on the gain of the system. The resulting gain is typically given the fol- 
lowing notation: 



( 5 . 72 ) 

with R l and R s 

The analysis to follow will show that: 

The loaded voltage gain of an amplifier is always less than the no-load gain. 






(a) (b) (c) 

FIG. 5.54 

Amplifier configurations: (a) unloaded; (b) loaded; (c) loaded with a source resistance. 



In other words, the addition of a load resistor R L to the configuration of Fig. 5.54a will 
always have the effect of reducing the gain below the no-load level. 

Furthermore: 

The gain obtained with a source resistance in place will always be less than that 
obtained under loaded or unloaded conditions due to the drop in applied voltage across 
the source resistance. 

In total, therefore, the highest gain is obtained under no-load conditions and the lowest 
gain with a source impedance and load in place. That is: 

For the same configuration A Vnl > A Vl > A Vg . 

It will also be interesting to verify that: 

For a particular design , the larger the level of R h the greater is the level of ac gain. 

In other words, the larger the load resistance, the closer it is to an open-circuit approxi- 
mation that would result in the higher no-load gain. 

In addition: 

For a particular amplifier , the smaller the internal resistance of the signal source , the 
greater is the overall gain. 

In other words, the closer the source resistance is to a short-circuit approximation, the 
greater is the gain because the effect of R s will essentially be eliminated. 

For any network , such as those shown in Fig. 5.54 that have coupling capacitors, the 
source and load resistance do not affect the dc biasing levels. 

The conclusions listed above are all quite important in the amplifier design process. 
When one purchases a packaged amplifier, the listed gain and all the other parameters are 
for the unloaded situation. The gain that results due to the application of a load or source 
resistance can have a dramatic effect on all the amplifier parameters, as will be demon- 
strated in the examples to follow. 

In general, there are two directions one can take to analyze networks with an applied 
load and/or source resistance. One approach is to simply insert the equivalent circuit, as 
was demonstrated in Section 5.11, and use methods of analysis to determine the quantities 
of interest. The second is to define a two-port equivalent model and use the parameters 
determined for the no-load situation. The analysis to follow in this section will use the first 
approach, leaving the second method for Section 5.14. 

For the fixed-bias transistor amplifier of Fig. 5.54c, substituting the r e equivalent circuit 
for the transistor and removing the dc parameters results in the configuration of Fig. 5.55. 



287 






288 BJT AC ANALYSIS 



+ 




V. % 








R L =r 0 \\R c \\R L = R c \\R L 



-o 

+ 






FIG. 5.55 

The ac equivalent network for the network of Fig. 5.54c. 



It is particularly interesting that Fig. 5.55 is exactly the same in appearance as Fig. 5.22 
except that now there is a load resistance in parallel with R c and a source resistance has 
been introduced in series with a source V s . 

The parallel combination of 

R'l — r o\\Rc\\RL — Rc\\Rl 

and V a = ~[3I h R' L = -(3I h (R c \\R L ) 



with 



gives 



h = 



A 

P>'e 




so that 




Rc II R-l 



(5.73) 



The only difference in the gain equation using V/ as the input voltage is the fact that Rc 
of Eq. (5.10) has been replaced by the parallel combination of Rc and R L . This makes good 
sense because the output voltage of Fig. 5.55 is now across the parallel combination of the 
two resistors. 

The input impedance is 




as before, and the output impedance is 






RcVo 



(5.74) 



(5.75) 



as before. 

If the overall gain from signal source V x to output voltage V„ is desired, it is only neces- 
sary to apply the voltage-divider rule as follows: 



and 



or 



Vi = 

V L = 

Vs 



ZjVs 

Zi + R s 

Zj 

Zi + R s 






Vo 

Vs 



Vo Vi 
Vi ' v s 



'V’L 



Zj 

Zi + R s 



so that 



Zi 

A = A 

Vs Zi + R s VL 



(5.76) 



Because the factor Z,/(Z ( - + R s ) must always be less than one, Eq. (5.76) clearly supports 
the fact that the signal gain A Vs is always less than the loaded gain A v . 




289 



EXAMPLE5.il Using the parameter values for the fixed-bias configuration of Example 5.1 
with an applied load of 4.7 k II and a source resistance of 0.3 kft, determine the following 
and compare to the no-load values: 



a. A Vl . 

b. A Vj . 

c. Z ( . 

d. Z 0 . 



Solution: 



a. Eq. (5.73): A Vi = - 






3 kH || 4.7 kH 

io.7i a 



1.831 ka 
io.7i a 



= -170.98 



which is significantly less than the no-load gain of —280.11. 
b. Eq.(5.76):A Vj = ^-^A Vi 

With = 1.07 kfl from Example 5.1, we have 

1.07 m 

A v = — ——(—170.98) = -133.54 

1.07 kO + 0.3 m 



which again is significantly less than A Vnl or A Vl . 

c. Zf = 1.07 k 11 as obtained for the no-load situation. 

d. Z Q = R c = 3 kil as obtained for the no-load situation. 
The example clearly demonstrates that A Vnl > A Vl > A v/ 



EFFECT OF R L AND R s 



For the voltage-divider configuration of Fig. 5.56 with an applied load and series source 
resistor the ac equivalent network is as shown in Fig. 5.57. 




FIG. 5.56 

Voltage -divider bias configuration with R s and R^. 




FIG. 5.57 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.56. 





290 BJT AC ANALYSIS 



First note the strong similarities with Fig. 5.55, with the only difference being the par- 
allel connection of Ri and R 2 instead of just R B . Everything else is exactly the same. The 
following equations result for the important parameters of the configuration: 



, v 0 * C ||/? L 
VL = Vi = c - 



Zi = Ri\R 2 \Pr e 



Z 0 = R c \\r 0 



(5.77) 

(5.78) 

(5.79) 



For the emitter-follower configuration of Fig. 5.58 the small-signal ac equivalent net- 
work is as shown in Fig. 5.59. The only difference between Fig. 5.59 and the unloaded 
configuration of Fig. 5.37 is the parallel combination of R E and R L and the addition of the 
source resistor R s . The equations for the quantities of interest can therefore be determined 
by simply replacing R E by R e \\R e wherever R E appears. If R E does not appear in an equation, 
the load resistor R L does not affect that parameter. That is, 



A 



Vl 



v 0 _ Re\\Rl 

Vi Re\\Rl + r e 



(5.80) 



Fee 




FIG. 5.58 

Emitter-follower configuration with R s and R L . 




FIG. 5.59 

Substituting the r e equivalent circuit into the ac equivalent network of Fig. 5.58. 




Z; — RslZb 



Z b = P(R e \\Rl) 




(5.81) 

(5.82) 

(5.83) 



The effect of a load resistor and a source impedance on the remaining BJT configura- 
tions will not be examined in detail here, although Table 5.1 in Section 5.14 will review 
the results for each configuration. 



5-15 DETERMINING THE CURRENT CAIN ^ 

You may have noticed in the previous sections that the current gain was not determined for 
each configuration. Earlier editions of this text did have the details of finding that gain, but 
in reality the voltage gain is usually the gain of most importance. The absence of the deri- 
vations should not cause concern because: 

For each transistor configuration , the current gain can be determined directly from the 
voltage gain, the defined load, and the input impedance. 

The derivation of the equation linking the voltage and current gains can be derived using 
the two-port configuration of Fig. 5.60. 



DETERMINING THE 291 
CURRENT GAIN 



°r 



System 



Jo 

+ 

v Q 




Rl 



FIG. 5.60 

Determining the current gain using the voltage gain. 



The current gain is defined by 



A t = ~ 
1 h 



(5.84) 



Applying Ohm’s law to the input and output circuits results in 
/, = — and I 0 = 

Z, Rl 

The minus sign associated with the output equation is simply there to indicate that the polar- 
ity of the output voltage is determined by an output current having the opposite direction. By 
definition, the input and output currents have a direction entering the two-port configuration. 
Substituting into Eq. (5.84) then results in 



A;, = - = 



Vo 

Rl 

V, 

z, 



V ; ' R, 



and the following important equation: 




(5.85) 



The value of R L is defined by the location of V a and 1 0 . 




292 BJT AC ANALYSIS 



To demonstrate the validity of Eq. (5.82), consider the voltage-divider bias configura- 
tion of Fig. 5.28. 

Using the results of Example 5.2, we find 



so that 




1.35 kft 



and I 0 



v_o _ 

R l 6.8 kft 




(~ — 
V 6.8 kn 

Vi 

1.35 kQ 



(Vo\( 1-35 kH \ 

V Vi A 6.8 kll ) 



= -(-368.76) 



1.35 kfl\ 

6.8 m ) 



73.2 



Using Eq. 5.82: 




-(-368.76) 



1.35 kU\ 

6.8 kfl J 



73.2 



which has the same format as the resulting equation above and the same result. 

The solution to the current gain in terms of the network parameters will be more com- 
plicated for some configurations if a solution is desired in terms of the network parameters. 
However, if a numerical solution is all that is desired, it is simply a matter of substituting 
the value of the three parameters from an analysis of the voltage gain. 

As a second example, consider the common-base bias configuration of Section 5.9. In 
this case the voltage gain is 



and the input impedance is 



A 



Vl — 



Rc 

r e 



A = R-EVe = r e 



with R l defined as R c due to the location of I Q . 
The result is the following: 






-1 



which agrees with the solution of that section because I c = I e . Note, in this case, that the 
output current has the opposite direction to that appearing in the networks of that section 
due to the minus sign. 



5-14 SUMMARY TABLES ^ 

The last few sections have included a number of derivations for unloaded and loaded BJT 
configurations. The material is so extensive that it seemed appropriate to review most of 
the conclusions for the various configurations in summary tables for quick comparisons. 
Although the equations using the hybrid parameters have not been discussed in detail at 
this point, they are included to make the tables complete. The use of hybrid parameters 
will be considered in a later section of this chapter. In each case the waveforms included 
demonstrate the phase relationship between input and output voltages. They also reveal the 
relative magnitude of the voltages at the input and output terminals. 

Table 5.1 is for the unloaded situation, whereas Table 5.2 includes the effect of R s and R L . 



5-15 TWO-PORT SYSTEMS APPROACH ^ 

In the design process, it is often necessary to work with the terminal characteristics of a 
device rather then the individual components of the system. In other words, the designer is 
handed a packaged product with a list of data regarding its characteristics but has no access 
to the internal construction. This section will relate the important parameters determined 
for a number of configurations in the previous sections to the important parameters of this 
packaged system. The result will be an understanding of how each parameter of the 



TABLE 5.1 

Unloaded BJT Transistor Amplifiers 




293 



TABLE 5.2 

BJT Transistor Amplifiers Including the Effect ofR s and Ri 




294 



TABLE 5.2 (Continued) 

BJT Transistor Amplifiers Including the Effect ofR s and Ri 




packaged system relates to the actual amplifier or network. The system of Fig. 5.61 is 
called a two-port system because there are two sets of terminals — one at the input and the 
other at the output. At this point it is particularly important to realize that 

the data surrounding a packaged system is the no-load data. 

This should be fairly obvious because the load has not been applied, nor does it come with 
the load attached to the package. 



K 




Thevenin 



FIG. 5.61 

Two-port system. 



295 




296 BJT AC ANALYSIS 



For the two-port system of Fig. 5.61 the polarity of the voltages and the direction of 
the currents are as defined. If the currents have a different direction or the voltages have 
a different polarity from that appearing in Fig. 5.61, a negative sign must be applied. 
Note again the use of the label A Vnl to indicate that the provided voltage gain will be the 
no-load value. 

For amplifiers the parameters of importance have been sketched within the boundaries 
of the two-port system as shown in Fig. 5.62. The input and output resistance of a packaged 
amplifier are normally provided along with the no-load gain. They can then be inserted as 
shown in Fig. 5.62 to represent the seated package. 



+ 

V; 



'Ri 



+ r j w\r 

% *,« 

d 




O 



+ 





FIG. 5.62 

Substituting the internal elements for the two-port system of Fig. 5.61. 



For the no-load situation the output voltage is 






( 5 . 86 ) 



due to the fact that I = 0 A, resulting in I 0 R 0 = OV. 

The output resistance is defined by V t = OV. Under such conditions the quantity A Vnl V* 
is zero volts also and can be replaced by a short-circuit equivalent. The result is 




( 5 . 87 ) 



Finally, the input impedance Z t simply relates the applied voltage to the resulting input 
current and 




( 5 . 88 ) 



For the no-load situation, the current gain is undefined because the load current is zero. 
There is, however, a no-load voltage gain equal to A Vnl . 

The effect of applying a load to a two-port system will result in the configuration of 
Fig. 5.63. Ideally, all the parameters of the model are unaffected by changing loads and 
levels of source resistance. However, for some transistor configurations the applied load 
can affect the input resistance, whereas for others the output resistance can be affected by 
the source resistance. In all cases, however, by simple definition, the no-load gain is unaf- 
fected by the application of any load. In any case, once A Vnl , R b and R 0 are defined for a 
particular configuration, the equations about to be derived can be employed. 




FIG. 5.63 

Applying a load to the two-port system of Fig. 5.62. 





Applying the voltage-divider rule to the output circuit results in 

R lA Vnl V l 



v n = 



R, + Rn 



and 



A =^ = 
V; 



Rl 

R, + R r Avm 



TWO-PORT SYSTEMS 297 
APPROACH 



( 5 . 89 ) 



Because the ratio Rl/(Rl + R 0 ) is always less than 1, we have further evidence that the 
loaded voltage gain of an amplifier is always less than the no-load level. 

The current gain is then determined by 

= h = -Vq/Rl = V. Zj 
iL h Vi/Zi v t r l 



and 




( 5 . 90 ) 



as obtained earlier. In general, therefore, the current gain can be obtained from the voltage 
gain and impedance parameters and R L . The next example will demonstrate the useful- 
ness and validity of Eqs. (5.89) and (5.90). 

Our attention will now turn to the input side of the two-port system and the effect of an 
internal source resistance on the gain of an amplifier. In Fig. 5.64, a source with an internal 
resistance has been applied to the basic two-port system. The definitions of Z t and A Vnl are 
such that: 

The parameters Z t and A Vy/ of a two-port system are unaffected by the internal resis- 
tance of the applied source . 




FIG. 5.64 

Including the effects of the source resistance R s . 



However: 

The output impedance may be affected by the magnitude of R s . 

The fraction of the applied signal reaching the input terminals of the amplifier of Fig. 5.64 
is determined by the voltage-divider rule. That is, 



V; 



RjV s 

Ri + R s 



( 5 . 91 ) 



Equation (5.91) clearly shows that the larger the magnitude of R s , the lower is the voltage 
at the input terminals of the amplifier. In general, therefore, as mentioned earlier, for a 
particular amplifier, the larger the internal resistance of a signal source, the lower is the 
overall gain of the system. 

For the two-port system of Fig. 5.64, 

v <> = 



and 




298 BJT AC ANALYSIS 



so that 



V Q — A 



and 



V NL 



Rj 

Ri + ^ 






A 






K = Rj 

V s R t + 7?, VNL 



( 5 . 92 ) 



The effects of R s and R L have now been demonstrated on an individual basis. The next 
natural question is how the presence of both factors in the same network will affect the 
total gain. In Fig. 5.65, a source with an internal resistance R s and a load R L have been 
applied to a two-port system for which the parameters Z b A Vnl , and Z Q have been specified. 
For the moment, let us assume that Z, and Z Q are unaffected by R L and R s , respectively. 




FIG. 5.65 

Considering the effects of R s and R^ on the gain of an amplifier. 



At the input side we find 

RiV s 

Eq - (5 - 91): y '- = ^ 



Vf _ Rj 

Vs R i + Rs 



and at the output side, 



or 



* V L 



V 0 

Vi " 



= — A V- 

Rl + Ro NL ' 

^Vbl _ Rj 
R l + R 0 ~ R l + R 0 VNL 



( 5 . 93 ) 



( 5 . 94 ) 



For the total gain A Vj = V 0 /V s , the following mathematical steps can be performed: 



= Yo = Yo.Yl 

" V s Vi ' v s 



( 5 . 95 ) 



and substituting Eqs. (5.93) and (5.94) results in 



Rj Rl a 

v, Ri + R s ' R l + R 0 VNL 



( 5 . 96 ) 



Because /, = VjR r as before, 




( 5 . 97 ) 



or, using I s = VJ(R S + R,), 



Ai = -Ay 



Rs + Rj 

Rl 



( 5 . 98 ) 



However, I t = I s , so Eqs. (5.97) and (5.98) generate the same result. Equation (5.96) TWO-PORT SYSTEMS 299 

clearly reveals that both the source and the load resistance will reduce the overall gain of APPROACH 

the system. 

The two reduction factors of Eq. (5.96) form a product that has to be carefully consid- 
ered in any design procedure. It is not sufficient to ensure that R s is relatively small if the 
effect of the magnitude of R L is ignored. For instance, in Eq. (5.96), if the first factor is 0.9 
and the second factor is 0.2, the product of the two results in an overall reduction factor 
equal to (0.9)(0.2) = 0.18, which is close to the lower factor. The effect of the excellent 
0.9 level was completely wiped out by the significantly lower second multiplier. If both 
were 0.9-level factors, the net result would be (0.9)(0.9) = 0.81, which is still quite high. 

Even if the first were 0.9 and the second 0.7, the net result of 0.63 would still be respect- 
able. In general, therefore, for good overall gain the effects of R s and R L must be evaluated 
individually and as a product. 



EXAMPLE 5.12 Determine A Vl and A Vs for the network of Example 5.11 and compare 
solutions. Example 5.1 showed that A Vnl = -280, Z t = 1.07 Ml, and Z Q = 3 kfl. In 
Example 5.11, R L = 4.7 kfl and R s = 0.3 kfl. 



Solution: 

a. Eq. (5.89): A Vl 



Rl 

Rt + R n 



V NL 



4.7 kQ 

4.7 kn + 3 m 

- 170.98 



(-280.11) 



as in Example 5.11. 

b. Eq.(5.96):A Vs = ^^ 



R L 

— A 

r l + Ro 



V NL 



1.07 kn 4.7 kn 

1.07 kfl + 0.3 kn 4.7 kfl + 3 kfl V 
= (0.781)(0.610)(— 280.11) 

= - 133.45 



as in Example 5.11. 



EXAMPLE 5.13 Given the packaged (no-entry-possible) amplifier of Fig. 5.66: 

a. Determine the gain A Vl and compare it to the no-load value with R L = 1.2 kn. 

b. Repeat part (a) with R L = 5.6 kfl and compare solutions. 

c. Determine A v with R L = 1.2 kn. 

I 0 lo 

d. Find the current gain A t = — = — with R L = 5.6 kn. 

h is 



Rs !> 

0.2 kQ 

% Vi 



f 



A v = -480 

V NL 

Z; = 4kQ 
Z Q = 2 kQ 




+ 

V 0 



FIG. 5.66 

Amplifier for Example 5.13. 




300 BJT AC ANALYSIS 



Solution: 



a. Eq.(5.89):A Vi = ^-^-A VNL 




= -180 



which is a dramatic drop from the no-load value. 



b. Eq. (5.89): A Vi = L A 

K L + 




= -353.76 



which clearly reveals that the larger the load resistor, the better is the gain. 




4 kll 



1.2 Ml 



4 Ml + 0.2 Ml 1.2 Ml + 2 Ml 
= (0.952)(0.375)(— 480) 

= -171.36 



(-480) 



which is fairly close to the loaded gain A v because the input impedance is considerably 
more than the source resistance. In other words, the source resistance is relatively 
small compared to the input impedance of the amplifier. 



It is important to realize that when using the two-port equations in some configurations 
the input impedance is sensitive to the applied load (such as the emitter-follower and collec- 
tor feedback) and in some the output impedance is sensitive to the applied source resistance 
(such as the emitter-follower). In such cases the no-load parameters for Z z and Z 0 have to 
first be calculated before substituting into the two-port equations. For most packaged sys- 
tems such as op-amps this sensitivity of the input and output parameters to the applied load 
or source resistance is minimized to eliminate the need to be concerned about changes from 
the no-load levels when using the two-port equations. 



The two-port systems approach is particularly useful for cascaded systems such as that 
appearing in Fig. 5.67, where A Vl , A V2 , A v , and so on, are the voltage gains of each stage 
under loaded conditions. That is, A V{ is determined with the input impedance to A V2 acting 
as the load on A Vl . For A V2 , A Vl will determine the signal strength and source impedance at 
the input to A vr The total gain of the system is then determined by the product of the indi- 
vidual gains as follows: 




= 252.6 



5.16 CASCADED SYSTEMS 





( 5 . 99 ) 



and the total current gain is given by 




( 5 . 100 ) 



CASCADED SYSTEMS 301 



No matter how perfect the system design, the application of a succeeding stage or load 
to a two-port system will affect the voltage gain. Therefore, there is no possibility of a 
situation where A v , A V2 , and so on, of Fig. 5.67 are simply the no-load values. The no-load 
parameters can be used to determine the loaded gains of each stage, but Eq. (5.99) requires 
the loaded values. The load on stage 1 is Z i2 , on stage 2 Z iv on stage 3 Z in , and so on. 




FIG. 5.67 

Cascaded system. 



EXAMPLE 5.14 The two-stage system of Fig. 5.68 employs a transistor emitter-follower 
configuration prior to a common-base configuration to ensure that the maximum percentage 
of the applied signal appears at the input terminals of the common-base amplifier. In Fig. 
5.68, the no-load values are provided for each system, with the exception of Z t and Z G for the 
emitter-follower, which are the loaded values. For the configuration of Fig. 5.68, determine: 

a. The loaded gain for each stage. 

b. The total gain for the system, A v and A v . 

c. The total current gain for the system. 

d. The total gain for the system if the emitter-follower configuration were removed. 



+ 



v s 




FIG. 5.68 

Example 5. 14. 



Solution: 

a. For the emitter-follower configuration, the loaded gain is (by Eq. (5.94)) 



z i 2 , _ 26 n 

Vo1 ~ z,- + z,„ Al ’ N| V '' 1 “ 26 n + 12 n 



(1) V h = 0.684 V h 



- 0 1 



and 






"i 



A v . = — = 0.684 



For the common-base configuration, 

R, 



8.2 kft 



V ° 2 R, + R, Avnl Vil 8.2 kO + 5.1 kQ 



(240) V h = 147.97 V h 



"O 2 






°2 



and A V2 = — ^ = 147.97 

b. Eq. (5.99): A Vr = A Vl A V2 

= (0.684)(147.97) 

= 101.20 








302 BJT AC ANALYSIS 



(10kn)(101.20) 

10 kO + I kfl 



V, = 25|iVo 



Eq. (5.91): A Vj 
c. Eq. (5.100): A h 



d. Eq. (5.91): 



and 



X 

V , 
V, 



and A v 

v s 



a = 

Z h + Rs VT 

92 



-A ^1 = 
Vt Rl 

- 123.41 

Zj C B 
ZicB + 



0.025 



—( 101 . 20 ) 



iom \ 

8.2 m ) 



Vs = 
with 



26 H 

2611 + lkft^ 

Vo 

y = 147.97 



0.025 V, 
from above 



Vo Vi v 0 

— = —•—= (0.025X147.97) = 3.7 
V\ Xv V; 



In total, therefore, the gain is about 25 times greater with the emitter-follower configuration 
to draw the signal to the amplifier stages. Note, however, that it is also important that the 
output impedance of the first stage is relatively close to the input impedance of the second 
stage, otherwise the signal would have been “lost” again by the voltage-divider action. 



RC - Coupled BIT Amplifiers 

One popular connection of amplifier stages is the 7?C-coupled variety shown in Fig. 5.69 in 
the next example. The name is derived from the capacitive coupling capacitor C c and the 
fact that the load on the first stage is an RC combination. The coupling capacitor isolates 
the two stages from a dc viewpoint but acts as a short-circuit equivalent for the ac response. 
The input impedance of the second stage acts as a load on the first stage, permitting the 
same approach to the analysis as described in the last two sections. 



EXAMPLE 5.15 

a. Calculate the no-load voltage gain and output voltage of the 7?C-coupled transistor 
amplifiers of Fig. 5.69. 

b. Calculate the overall gain and output voltage if a 4.7 kfl load is applied to the second 
stage, and compare to the results of part (a). 

c. Calculate the input impedance of the first stage and the output impedance of the second 
stage. 



+20 V 




FIG. 5.69 

RC-coupled BJT amplifier for Example 5.15. 



Solution: 

a. The dc bias analysis results in the following for each transistor: 

V 5 = 4.8V, V £ = 4.1V, V c = 11V, / £ = 4.1mA 



At the bias point, 



CASCADED SYSTEMS 303 



26 mV 26 mV 



e I E 4.1mA 
The loading of the second stage is 

Z ,- 2 = RllfylPre 

which results in the following gain for the first stage: 

RcURilRilfc) 



= 6.34 D, 



^Vi 



(2.2 kI2) | [15 kI2 1 4.7 kI2 || (200)(6.34 II)] 



6.34 n 



659.2 12 



_ = -104 
6.3412 

For the unloaded second stage the gain is 

R c _ 2.2 kI2 

^2(NL) ~ ~ ~ 

' e 

resulting in an overall gain of 



= -347 



A = A A 

V T( NL) v l /ly 2(NL) 



6.3412 

= ( — 104)( — 347) = 36.1 X 10 3 



The output voltage is then 



V„ = A 



V T( NL) 



V t = (36.1 X 10 3 )(25 /jlV) = 902.5 mV 



b. The overall gain with the 10-kO load applied is 

4.7 kfl 



_ V 0 _ R l 
Vt Vi r l + z 0 Vr(NL > 



4.7 kfl + 2.2 kl2 



(36.1 X 10 3 ) s 24.6 X 10 3 



which is considerably less than the unloaded gain because R L is relatively close to Rc- 

V 0 = A VT V t 

= (24.6 X 10 3 )(25 ixV) 

= 615 mV 

c. The input impedance of the first stage is 

z h = R x \\R 2 \pr e = 4.7 kil||l5 kft|| (200)(6.34 CL) = 0.94 kil 
whereas the output impedance for the second stage is 

Z 02 = R c = 2.2 kft 



Cascode Connection 

The cascode configuration has one of two configurations. In each case the collector of the 
leading transistor is connected to the emitter of the following transistor. One possible 
arrangement appears in Fig. 5.70; the second is shown in Fig. 5.71 in the following example. 



Tec 




304 BJT AC ANALYSIS 



The arrangements provide a relatively high-input impedance with low voltage gain for the 
first stage to ensure the input Miller capacitance (to be discussed in Section 9.9) is at a 
minimum, whereas the following CB stage provides an excellent high-frequency response. 



EXAMPLE 5.16 Calculate the no-load voltage gain for the cascode configuration of Fig. 5.71. 



V cc = 18V 




FIG. 5.71 

Practical cascode circuit for Example 5.16. 



Solution: The dc analysis results in 



V Bl = 4.9 V, V Bl = 10.8 V, 7 Cl 



Iq 2 = 3.8 mA 



because I E = I E the dynamic resistance for each transistor is 



26 mV 26 mV 



r P = 



h 



3.8 mA 



= 6.8 12 



The loading on the transistor Qi is the input impedance of the Q 2 transistor in the CB 
configuration as shown by r e in Fig 5.72. 

The result is the replacement of Rc in the basic no-load equation for the gain of the CB 
configuration, with the input impedance of a CB configuration as follows: 



R c tr e 

Ku = -1 

r P r p 



X V\ 



with the voltage gain for the second stage (common base) of 



Rc 

A Vn = — = 
r P 



^2 



1.8 kn 

6.8 12 



= 265 



Vi 



1 






oV r 



°2 



FIG. 5.72 

Defining the load of Q\. 





The overall no-load gain is 

A Vr = A Vl A V2 = (—1)(265) = -265 

As expected, in Example 5.16, the CE stage provides a higher input impedance than can 
be expected from the CB stage. With a voltage gain of about 1 for the first stage, the 
Miller-effect input capacitance is kept quite low to support a good high-frequency response. 
A large voltage gain of 265 was provided by the CB stage to give the overall design a good 
input impedance level with desirable gain levels. 



5-17 DARLINGTON CONNECTION ^ 

A very popular connection of two bipolar junction transistors for operation as one “super- 
beta” transistor is the Darlington connection shown in Fig. 5.73. The main feature of the 
Darlington connection is that the composite transistor acts as a single unit with a current 
gain that is the product of the current gains of the individual transistors. If the connection 
is made using two separate transistors having current gains of /3i and the Darlington 
connection provides a current gain of 



Pd ~ P1P2 



( 5 . 101 ) 




The configuration was first introduced by Dr. Sidney Darlington in 1953. A short biog- 
raphy appears as Fig 5.74. 

Emitter-Follower Configuration 

A Darlington amplifier used in an emitter-follower configuration appears in Fig. 5.75. The 
primary impact of using the Darlington configuration is an input impedance much larger than 




FIG. 5.75 

Emitter-follower configuration with a Darlington amplifier. 




American (Pittsburgh, PA; Exeter, NH) 

( 1906 - 1997 ) 

Department Head at Bell Laboratories 
Professor, Department of Electrical and 
Computer Engineering, University of 
New Hampshire 

Dr. Sidney Darlington earned his B.S. in 
physics at Harvard, his B.S. in electrical 
communication at MIT, and his Ph.D. at 
Columbia University. In 1929 he joined 
Bell Laboratories, where he was head of 
the Circuits and Control Department. Dur- 
ing that period he became good friends 
with other important contributors such as 
Edward Norton and Hendrik Bode. A 
holder of 24 U.S. patents, he was awarded 
the Presidential Medal of Freedom, the 
highest civilian honor in the United States, 
in 1945 for his contributions to network 
design during World War II. An elected 
member of the National Academy of 
Engineering, he also received the IEEE 
Edison Medal in 1975 and the IEEE 
Medal of Honor in 1981. His U.S. patent 
2 663 806 titled “Semiconductor Signal 
Translating Device” was issued on Decem- 
ber 22, 1953, describing how two transis- 
tors could be constructed in the Darlington 
configuration on the same substrate — 
often looked upon as the beginnings of 
compound IC construction. Dr. Darlington 
was also responsible for the introduction 
and development of the Chirp technique, 
used throughout the world in waveguide 
transmission and radar systems. He is a 
primary contributor to the Bell Laborato- 
ries Command Guidance System that 
guides most of the rockets used today to 
place satellites in orbit. It uses a combina- 
tion of radar tracking on the ground with 
inertial control in the rocket itself. Dr. 
Darlington was an avid outdoorsman as a 
hiker and member of the Appalachian 
Mountain Club. One of his proudest 
accomplishments was being able to climb 
Mt. Washington at the age of 80. 

FIG. 5.74 

Sidney Darlington ( Courtesy of 
AT&T Archives and History Center.) 



305 




306 BJT AC ANALYSIS 



that obtained with a single-transistor network. The current gain is also larger, but the voltage 
gain for a single-transistor or Darlington configuration remains slightly less than one. 



DC Bias The case current is determined using a modified version of Eq. 4.44. There are 
now two base-to-emitter voltage drops to include and the beta of a single transistor is 
replaced by the Darlington combination of Eq. 5.101. 



Vcc ~ V BEl ~ Vbe 2 
Rb + Pd^e 



( 5 . 102 ) 



The emitter current of Qj is equal to the base current of Q 2 so that 



resulting in 



h 2 ~ Pih 2 ~ fiihx — Pi(P\Ie^) — PifclBx 



Ic 2 = h 2 ~ PdIb x 



The collector voltage of both transistors is 

V Cl = V C2 = V cc 



the emitter voltage of Q 2 

Ve 2 — Ie 2 Re 



( 5 . 103 ) 

( 5 . 104 ) 

( 5 . 105 ) 



the base voltage of Q\ 

Vb\ — Vcc ~ h^B — Ve 2 + V B Ei + Vbe 2 



( 5 . 106 ) 



the collector-emitter voltage of Q 



V C e 2 = V C2 ~ V E2 = V cc ~ Ve 2 



( 5 . 107 ) 



EXAMPLE 5.17 Calculate the dc bias voltages and currents for the Darlington configura- 
tion of Fig. 5.76. 



+18 V 




FIG. 5.76 

Circuit for Example 5. 1 7. 



Solution: 



DARLINGTON 307 
CONNECTION 



Pd = Pi Pi = (50)(100) = 5000 
_ V cc ~ V BE] - V B e 2 _ 18 V - 0.7 V - 0.7 V 

Ib ' ~ R b + p D R E ~ 3.3 MO + (5000)(390 17) 

18 V -1.4 V 16.6 V 

3.3 MU + 1.95 MU 5.25 MU ^ 

I Ci = l Ei = (3 d I Bi = (5000)(3.16mA) = 15.80 mA 
V Cl = Vc 2 = 18 V 

Ve 2 = Ie 2 Re = (15.80 mA)(390 ft) = 6.16 V 
V Bl = Ve 2 + V BEl + V B e 2 = 6.16 V + 0.7 V + 0.7 V = 7.56 V 
V C e 2 = V cc ~ Ve 2 = 18 V - 6.16 V = 11.84 V 



AC Input Impedance The ac input impedance can be determined using the ac equivalent 
network of Fig. 5.77. 




As defined in Fig. 5.77: 





2/2 = Pi(r e2 + Re) 




= Pl( r e, + Z i 2 ) 


so that 


2/, = Pi(r ei + P2(r e2 + Re)) 


Assuming 


r e ^ r e 2 


and 


z h = Pi(r ei + PiRr) 


Since 


P 2 R e :>> 'V 




2/j = P\P 2 Rr 


and since 


2, = R[j\\Zj 



— RbWPiPiRe ~ RbWPdRe 



( 5 . 108 ) 



For the network of Fig. 5.76 

Z[ — RbWPdRe 

= 3.3 Mft || (5000)(390 ft) = 3.3 Mft|| 1.95 Mft 

= 1.38 Mft 

Note in the preceding analysis that the values of r e were not compared but dropped com- 
pared to much larger quantites. In a Darlington configuration the values of r e will be differ- 
ent because the emitter current through each transistor will be different. Also, keep in mind 
that chances are the beta values for each transistor will be different because thay deal with 
different current levels. The fact remains, however, that the product of the two beta values 
will equal /3/> as indicated on the specification sheet. 



308 BJT AC ANALYSIS 



AC Current Gain The current gain can be determined from the equivalent network of 
Fig. 5.78. The output impedance of each transistor is ignored and the parameters for each 
transistor are employed. 



P\ r e x 

-AAAr- 



Pl r e 2 

-VSAr 



Pih, 









FIG. 5.78 

Determining A t for the network of Fig. 5. 75. 
Solving for the output current: I 0 = I bl + /3 2 4 2 = (/3 2 + 1)4 2 

with 4 2 = P\I h] + 4, = (/3i + 1 )I bl 

Then I 0 = 0 3 2 + 1)03! + 1)4, 

Using the current-divider rule on the input circuit: 

Rb t Rb 



h x = 



and 
so that 

Using /3 h /3 2 » 1 



Rb + zf 

(fi 2 + DOSi + l) 



Rb + P1P2 Re 

Rb 



/, 



A' = — = 

h 



Rb + P\P 2 r e 
(P i + D(fe + D*b 
Rb + P1P2 Re 



A: = — = 



H^iRr 



Rb + P1P2 Re 



or 



A _ 4 __ HdRr 

h Rb + PdRe 



For Fig. 5.76: 



4 



PdRb 



A; = — = 

h Rb + Pd Re 

= 3.14 X 10 3 



(5000)(3.3 MO) 
3.3 Mil + 1.95 MO 



(5.109) 

(5.110) 



AC Voltage Gain The voltage gain can be determined using Fig. 5.77 and the following 
derivation: 



and 



and 



Vo = We 
Vi = Ii(R B \\Zd 

Rb\\Zi = RbWPdRe = 

A _V 0 _ Ip Re 

V Vi Ii(R B \\Zi) 

PdRb 

Rb + Pd r e 



PdRbRe 
Rb + PdRe 
Re 



(Ad 



Rf 



Rb || %i 



PdRbRe 



_ L Rb + PdRe - 



A v = 1 (in reality less than one) 



(5.111) 



an expected result for the emitter-follower configuration. 



DARLINGTON 309 
CONNECTION 



AC Output Impedance The output impedance will be determined by going back to Fig. 5.78 
and setting V t to zero volts as shown in Fig. 5.79. The resistor R B is “shorted out,” resulting 
in the configuration of Fig. 5.80. Note in Figs. 5.82 and 5.83 that the output current has 
been redefined to match standard nomenclature and properly defined Z Q . 







FIG. 5.79 
Determining Z Q . 




FIG. 5.80 

Redrawn of network of Fig. 5.79. 



At point a Kirchhoff’ s current law will result in I 0 + + 1 )Ib 2 — I e - 

h = h- (ft + m 2 

Applying Kirchhoff’ s voltage law around the entire outside loop will result in 

e\ ~ 4 2 /Ve 2 — Vo 0 
and V„ = 4,/Ve, + 4 2 /Ve 2 

Substituting I bl = (Pi + 1)4 1 

Vo = ~hfi\r e , ~ (Pi + D4,/V, 2 
= ~ l b l lP\ r e l + (Pi + 1 )/Ve 2 ] 



and 4, 

with 4 2 

so that 4 2 

Going back I Q 





P\ r e, + (Pi + 1 )P2 r e 2 

(Pi + 1)4, = (Pi + l) 

P i + l 



- Pl r e, + (Pi + 1 )Pl r e 2 - 



V„ 



-P l r e, + (Pi + 1)/Ve 2 
4 - (P 2 + i)4 2 = 4 - (Pi + 1)1 - 



(Pi + 1)V 0 



Pl r ei + (Pi + 1 ) Ve 2 



Vq | (Pi + ixfe + m, 
R E /Ve, + (Pi + 1 )/4'V, 



310 BJT AC ANALYSIS 



Ci 

( h +Vl 



e 2 




FIG. 5.81 

Resulting network defined by Z Q . 



Because /3 1? » 1 



V, 



I 0 = — + 
° Rf 



Pi Wo _ V 0 1 V 0 

J8ir ei + /3l/Ve 2 Z 3 !^! + ty^Tei 

PIP 2 Pll32 



/ 0 =L + 



r «. 4. 

L 



ft e2 

which defines the parallel resistance network of Fig. 5.81. 



In general, R E » ( — — I- r 6l ) so the output impedance is defined by 



z °=s +r - 



( 5 . 112 ) 



Using the dc results, the value of r e2 and r e can be determined as follows. 



and 



' e 2 



I E ] 



26 mV _ 26 mV 

I El ~ 15.80 mA ~~ 
_ Ie 2 _ 15.80 mA 
100 



i.65 ft 
= 0.158 mA 



so that 



26 mV 

e> ~ 0.158 mA 



164.5 ft 



The output impedance for the network of Fig. 5.78 is therefore: 

Z 0 = — + r e = 164 5 — + 1.65 ft = 1.645 ft + 1.65 ft = 3.30 ft 
0 j3 2 2 100 

In general, the output impedance for the configuration of Fig. 5.78 is very low — in the 
order of a few ohms at most. 



Voltage-Divider Amplifier 

DC Bias Let us now investigate the effect of the Darlington configuration in a basic 
amplifier configuration as shown in Fig. 5.82. Note that now there is a collector resistor 
Rc, and the emitter terminal of the Darlington circuit is connected to ground for ac condi- 
tions. As noted on Fig. 5.82, the beta of each transistor is provided along with the resulting 
voltage from base to emitter. 



V cc = 27 V 




FIG. 5.82 

Amplifier configuration using a Darlington pair. 



DARLINGTON 311 
CONNECTION 



The dc analysis can proceed as follows: 



V n 



P D = P1P2 = (110 X 110) = 12,100 
R 2 220 kll(27 V) 



-Vcc 



= 8.61 V 



R 2 + Rx "" 220 kfl + 470 k!2 

V E = V B - V BE = 8.61 V - 1.5 V = 7.11 V 



I E 

E Rf 



V E 7.11V 



680 n 



= 10.46 mA 



I E 10.46 mA 

I B = — = = 0.864 uA 

B 12,100 ^ 



Using the preceding results the values of r ei and r e can be determined: 



and 



_ 26 mV _ 26 mV 

rei ~~ I E ,, ~ 10.46 mA 

_ _ (e 2 _ 10.46 mA 

h, ~ h 2 ~ ~^T ~ 110 

_ 26 mV _ 26 mV 

re ' _ / £l ~ 0.095 mA _ 



= 2.49 n 

= 0.095 mA 

273.7 il 



AC Input Impedance The ac equivalent of Fig. 5.82 appears as Fig. 5.83. The resistors Ri 
and R 2 are in parallel with the input impedance to the Darlington pair, assuming the second 
transistor found by assuming the second transistor acts like an R E load on the first as 
shown in Fig. 5.83. 

That is, Z- = $ x r ex + Pi(J3 2 r e2 ) 




FIG. 5.83 

Defining Z' z - and Z r 



and 



z/ = P\[r ei + /3 2 r e2 ] 



For the network of Fig. 5.82: 

Z[ = 110[273.7 fl + (110X2.4912)] 
= 110[273.7 12 + 273.9 12] 

= 110[547.6 12] 

= 60.24 kil 

Z/ = rAr 2 \\z! 

= 470 k!2 1| 220 k!2 1| 60.24 k!2 
= 149.86 k!2 1|60.24 k!2 

= 42.97 kil 



( 5 . 113 ) 



and 



312 BJT AC ANALYSIS 



AC Current Gain The complete ac equivalent of Fig. 5.82 appears as Fig. 5.84. 



i; \ Pihi 

B\ — ► — ► Ei,B 2 C x C 2 




FIG. 5.84 

ac equivalent network for Fig. 5.82. 



The output current 
with 
so that 
and with 
we find 

and 



and finally 



For the original structure: 
but 



so that 



4 — 0i4, + 02 h 2 
h 2 = OSi + 1)4, 

4 = 0i4, + 02(0i + 1)4, 

4, = 4 

4 = M + 02(j3i + 1)4 

a;- = j = 0 i + 02(0 + i) 

= P\ + PlP\ = ^l(l + fo) 
s P1P2 



M = I f = P1P2 = Pd 

* i 



// = 



*i||*2 + Z/ 





fo(*l||*2) 
7 ? i ||/?2 + z / 



^1 1|^2 
*l||*2 + Zj 



For Fig. 5.82 



(12,100)(149.86 kfl) 
149.86 kQ + 60.24 kQ 



= 8630.7 

Note the significant drop in current gain due to R\ and AS- 



( 5 . 114 ) 



( 5 . 115 ) 



AC Voltage Cain The input voltage is the same across R\ and R 2 and at the base of the 
first transistor as shown in Fig. 5.84. 

The result is 



A v = 




= (Rc\ 
1'iZ'i \Z}J 



and 




( 5 . 116 ) 



For the network of Fig. 5.82, 

4 Prftc 



(12,000)(1.2 kfl) 
60.24 kfl 



- 241.04 



AC Output Impedence Because the output impedance in R c is parallel with the collector 
to emitter terminals of the transistor, we can look back on similar situations and find that 
the output impedance is defined by 



DARLINGTON 313 
CONNECTION 



z 0 = Rc\\r 0l 



( 5 . 117 ) 



where r 02 is the output resistance of the transistor Q 2 . 

Packaged Darlington Amplifier 

Because the Darlington connection is so popular, a number of manufacturers provide 
packaged units such as shown in Fig. 5.85. Typically, the two BJTs are constructed on a 
single chip rather than separate BJT units. Note that only one set of collector, base, and 
emitter terminals is provided for each configuration. These, of course, are the base of the 
transistor Q h the collector of Q\ and Q 2 , and the emitter of Q 2 . 




FIG. 5.85 

Packaged Darlington amplifiers: (a) TO-92 package; 
(b) Super SOT™-3 package. 



In Fig. 5.86 some of the ratings for an MPSA28 Fairchild Semiconductor Darlington 
amplifier are provided. In particular, note that the maximum collector-to-emitter voltage of 
80 V is also the breakdown voltage. The same is true for the collector-to-base and emitter- 
to-base voltages, although notice how much lower the maximum ratings are for the base- 
to-emitter junction. Because of the Darlington configuration, the maximum current rating 
for the collector current has jumped to 800 mA — far exceeding levels we have encountered 



Absolute Maximum Ratings 


V CES 


Collector-Emitter Voltage 


80 V 


VCBO 


Collector-Base Voltage 


80 V 


Vebo 


Emitter-Base Voltage 


12 V 


Ic 


Collector Current-Continuous 


800 mA 



Electrical Characteristics 


V(BR)CES 


Collector-Emitter Breakdown Voltage 


80 V 


V(BR)CBO 


Collector-Base Breakdown Voltage 


80 V 


V(BR)EBO 


Emitter-Base Breakdown Voltage 


12 V 


ICBO 


Collector Cutoff Current 


100 mA 


Iebo 


Emitter Cutoff Current 


100 mA 



On Characteristics 


hpE 


DC Current Gain 


10,000 


Fc£(sat) 


Collector-Emitter Saturation Voltage 


1.2 V 


Tfi£(on) 


Base-Emitter on Voltage 


2.0 V 



FIG. 5.86 

MPSA 28 Fairchild Semiconductor Darlington amplifier ratings. 




314 BJT AC ANALYSIS 



C 




E 

FIG. 5.88 

Feedback pair connection. 



for single-transistor networks. The dc current gain is rated at the high level of 10,000 and 
the base-to-emitter potential in the “on” state is 2 V, which certainly exceeds the 1.4 V we 
have used for individual transistors. Finally, it is interesting to note that the level of I CE0 is 
much higher at 500 nA than for a typical single-transistor unit. 

In the packaged format the network of Fig. 5.75 would appear as shown in Fig. 5.87. 
Using p D and the provided value of V be (=V B e x + Vbe 2 ), all the equations appearing in 
this section can be applied. 



+V CC (+18 V) 




FIG. 5.87 

Darlington emitter -follower circuit. 



5-18 FEEDBACK PAIR ^ 

The feedback pair connection (see Fig. 5.88) is a two-transistor circuit that operates like 
the Darlington circuit. Notice that the feedback pair uses a pnp transistor driving an npn 
transistor, the two devices acting effectively much like one pnp transistor. As with a Dar- 
lington connection, the feedback pair provides very high current gain (the product of the 
transistor current gains), high input impedance, low output impedance, and a voltage gain 
slightly less than one. Initially, it may appear that it would have a high voltage gain because 
the output is taken off the collector with a resistor R c in place. However, the pnp-npn 
combination results in terminal characteristics very similar to that of the emitter-follower 
configuration. A typical application (see Chapter 12) uses a Darlington and a feedback-pair 
connection to provide complementary transistor operation. A practical network employing a 
feedback pair is provided in Fig. 5.89 for investigation. 



DC Bias 



The dc bias calculations that follow use practical simplifications wherever possible to pro- 
vide simpler results. From the Q\ base-emitter loop, one obtains 

Vcc ~ We ~ V EBl ~ — 0 

Vcc (PiPihJRc ~ V EBl ~ Ib x Rb — 0 

The base current is then 



Vcc V BEj 
1 “ ¥ b + fafoRc 



( 5 . 118 ) 



The collector current of Q i is 

Ic x = — h 2 

which is also the base Q 2 current. The transistor Q 2 collector current is 

Ic 2 ~ Pih 2 ~ Ie 2 





FEEDBACK PAIR 315 




FIG. 5.89 

Operation of a feedback pair. 



so that the current through R c is 



! c - ^E\ + i c 1 ~ h 2 + I c 2 



The voltages 
and 



Vc 2 — V El — V C c IcRc 



Vbi — 



with 



V 5Cl = V Bl - V BE2 = V Bl ~ 0.7 V 



( 5 . 119 ) 

( 5 . 120 ) 

( 5 . 121 ) 

( 5 . 122 ) 



EXAMPLE 5.18 Calculate the dc bias currents and voltages for the circuit of Fig. 5.89 to 
provide V 0 at one-half the supply voltage (9 V). 

Solution: 

18 V -0.7 V 17.3 V 

In, = — — — = ~z — 4.45 uA 

B ' 2Mfl + (140)(180)(75 Cl) 3.89 X 10 6 

The base £>2 current is then 

Ib 2 = I Cx = PiI Bl = 140(4.45 jlA) = 0.623 mA 

resulting in a Q 2 collector current of 

Ic 2 = Pih 2 = 180(0.623 mA) = 112.1mA 

and the current through Rc is then 

Eq. (5.119): I c = I El + ^c 2 = 0.623 mA + 112.1 mA « I Cl = 112.1 mA 
V C2 = V El = 18 V - (112.1 mA)(75 II) 

= 18 V - 8.41V 

= 9.59 V 

^ 1 =/i ?1 ^ = (4.45/iA)(2Mn) 

= 8.9 V 

V BC] = V Bl ~ 0.7 V = 8.9 V - 0.7 V 

= 8.2 V 



316 BJT AC ANALYSIS 



AC Operation 

The ac equivalent circuit for that of Fig. 5.89 is drawn in Fig. 5.90. 




FIG. 5.90 

ac equivalent for the network of Fig. 5.89. 



Input Impedance, Z/ The ac input impedance seen looking into the base of transistor Q\ 
is determined as follows: 

1 i. i 

Applying Kirchhoff’ s current law at node a and defining l c = l a : 

hi + Pihi ~ Pih 2 + h = 0 

with 4 2 = — /3 1 // 7| as noted in Fig. 5.90. 

The result is 4, + /Vfc, - j8 2 (-j8i I b ) + h = 0 

and 4 = -/,,, - Z44, - PiP 2 I hl 

or h = “4^1 + /4) “ Pi@2hi 

but /3] » 1 

and 4 = -/3,4, “ PiPihi = ~hSfii + P 1 P 2 ) 

= -i bl m + Pi) 



resulting in: 

Now, I bl = 
and 

so 

Rearranging: 

and 

so 

and 

so that 
In general, 
and 



4 = /4/44i 



V,- - v„ 



Pl r e 



from Fig. 5.90 

V 0 = ~I 0 R c = ~i~P\Pih) R c = P\Pihi R c 

Vi ~ PxPihfic 

4, = o ~ 

P\r ei 

h t Pl r ei = Vj ~ P\P 2 !„ I R C 
4 1 (/4 r e 1 + P\Pl R c) = Vi 



hi = n = 



V'. = — = 

1 I'i 



P\ r e x + PlPl R C 
Vi Vi 



P\ r e + P\Pl R C 



n = P\Tei + PlPl R C 



PlP2 R C >:> Pl r t 



«i 



z/ = P\Pi R c 



( 5 . 123 ) 



( 5 . 124 ) 



( 5 . 125 ) 



with 



Zi = r b \\z / 



( 5 . 126 ) 



26 mV 26 mV 

For the network of Fig. 5.89: r e = — 7 = 7 - = 41.73 12 



If 



0.623 mA 



and 



Z[ — P\r ex + PiPiRc 

= (140)(41.73 12) + (140)(180)(75 12) 

= 5842.212 + 1.89 M12 

= 1.895 MU 

where Eq. (5.125) results in Z/ = PifcRc — (140)(180)(75 12) = 1.89 MO, validating 
the above approximations. 



FEEDBACK PAIR 317 



Current Gain 

Defining = // as shown in Fig. 5.90 will permit finding the current gain A\ — I 0 /I 
Looking back on the derivation of we found I 0 = h x ~ ~P\^2 1\ 



resulting in 



A i=Ji = -P 1 P 2 

*i 



( 5 . 127 ) 



The current gain A , = I,,/ 1, can be determined using the fact that 



, h h n 

Ai = T = v'T 

L i L i 1 i 



For the input side: 
Substituting: 

So that 



// = 



R B h 



R B h 



R b + 7 \ R b + PifaRc 

l a i[ ( R B \ 

— ■— = r-fl, fi.il ' 

i\ h 



A ‘ ’ ( ^ 2 \r b + PxPjRc) 



A _ l_o_ _ ~Pl 
' li R B + P1P2 R C 



( 5 . 128 ) 



The negative sign appears because both l i and I 0 are defined as entering the network. 

I Q 

For the network of Fig. 5.89: A' t = — = — /3|/X 

li 

= -(140)(180) 

= -25.2 X 10 3 

= = (140)(180)(2 Mil) 

‘ R B + j8i/3 2 R c 2 Mfl + 1.89 Mn 
50,400 Mil 
3.89 MU 

= -12.96 X 10 3 (= half of A/) 

Voltage Gain 

The voltage gain can quickly be determined using the results obtained above. 

That is, 



. -IJtc 

A,, = — = 



r;z; 

(-PiM)Rc 

IKP l r e, + Pi P 2 Rc) 



A v = 



r e , + P 2 Rc 



( 5 . 129 ) 



318 BJT AC ANALYSIS 



which is simply the following if we apply the approximation: (3 2 Rc ^ r e 



A v ^ ^ = 1 



For the network of Fig. 5.89: A v = 



(180)(75 D) 



&2 R C 



r ex + fi 2 R c ~ 41.73 VL + (180)(75 11) 

13.5 X 10 3 n 



41.73 11 + 13.5 X io 3 n 
= 0.997 = 1 (as indicated above) 



Output Impedance 

The output impedance Z' Q is defined in Fig. 5.91 when V t is set to zero volts. 



V 0 




Using the fact that I 0 

but 

and 

so that 
with 



FIG. 5.91 

Determining Z' Q and Z Q . 



—PiP 2 Ijy from calculations above, we find that 

T = Y± = 



In 



_ 0i02 h x 



I h , = 



y _ o 

P\ r e 



7 ' = 



-0102 - 



Vn 



P\r, 



«i 



01 ^! 

0102 



Z' = — 
0 02 



Rc 



02 



However, 



leaving 



R c » 



02 




(5.130) 

(5.131) 



(5.132) 



which will be a very low value. 
For the network of Fig. 5.89: 



41.73 n 
180 



= 0.23 n 



The preceding analysis shows that the feedback pair connection of Fig. 5.89 provides 
operation with voltage gain very near 1 (just as with a Darlington emitter-follower), a very 
high current gain, a very low output impedance, and a high input impedance. 



THE HYBRID 319 
EQUIVALENT MODEL 



5-19 THE HYBRID EQUIVALENT MODEL ^ 

The hybrid equivalent model was mentioned in the earlier sections of this chapter as one 
that was used in the early years before the popularity of the r e model developed. Today 
there is a mix of usage depending on the level and direction of the investigation. 

The r e model has the advantage that the parameters are defined by the actual operating 
conditions, 

whereas 

the parameters of the hybrid equivalent circuit are defined in general terms for any 
operating conditions. 

In other words, the hybrid parameters may not reflect the actual operating conditions 
but simply provide an indication of the level of each parameter to expect for general use. 
The r e model suffers from the fact that parameters such as the output impedance and the 
feedback elements are not available, whereas the hybrid parameters provide the entire set 
on the specification sheet. In most cases, if the r e model is employed, the investigator will 
simply examine the specification sheet to have some idea of what the additional elements 
might be. This section will show how one can go from one model to the other and how the 
parameters are related. Because all specification sheets provide the hybrid parameters and 
the model is still extensively used, it is important to be aware of both models. The hybrid 
parameters as shown in Fig. 5.92 are derived from the specification sheet for the 2N4400 
transistor described in Chapter 3. The values are provided at a dc collector current of 1 mA 
and a collector- to-emitter voltage of 10 V. In addition, a range of values is provided for 
each parameter for guidance in the initial design or analysis of a system. One obvious ad- 
vantage of the specification sheet listing is the immediate knowledge of typical levels for 
the parameters of the device as compared to other transistors. 



Min. Max. 



Input impedance 

{1 c = I mA dc, V CE = 10 V dc,/ = 1 kHz) 


h ie 


0.5 


7.5 


kn 


Voltage feedback ratio 

(/ c = 1 mA dc, V CE = 10 V dc ,/= 1 kHz) 


h„ 


0.1 


8.0 


X10 -4 


Small-signal current gain 

(/ c = 1 mA dc, V CE = 10 V dc,/= 1 kHz) 


hfe 


20 


250 


— 


Output admittance 

Uc = 1 mA dc, V CE = 10 V dc,/= 1 kHz) 


h oe 


1.0 


30 


1 jxS 



FIG. 5.92 

Hybrid parameters for the 2N4400 transistor. 



The description of the hybrid equivalent model will begin with the general two-port 
system of Fig. 5.93. The following set of equations (5.131) and (5.132) is only one of 
a number of ways in which the four variables of Fig. 5.93 can be related. It is the most 
frequently employed in transistor circuit analysis, however, and therefore is discussed in 
detail in this chapter. 



1 o- 

+ 




Vi 






o 2 

+ 



~o T 



FIG. 5.93 

Two-port system. 




320 BJT AC ANALYSIS 



( 5 . 133 ) 



v* = h n Ii + h u v 0 



( 5 . 134 ) 



The parameters relating the four variables are called h-parameters , from the word 
“hybrid.” The term hybrid was chosen because the mixture of variables ( V and I) in each 
equation results in a “hybrid” set of units of measurement for the /^-parameters. A clearer 
understanding of what the various /^-parameters represent and how we can determine their 
magnitude can be developed by isolating each and examining the resulting relationship. 



I 0 ~ *21 Ii + A 22 V 0 



An If we arbitrarily set V 0 = 0 (short circuit the output terminals) and solve for h\\ in 
Eq. (5.133), we find 



. _ ^ 

h\\ — — 

* i 



V n =0 



ohms 



( 5 . 135 ) 



The ratio indicates that the parameter h\\ is an impedance parameter with the units of ohms. 
Because it is the ratio of the input voltage to the input current with the output terminals 
shorted , it is called the short-circuit input-impedance parameter. The subscript 11 of An 
refers to the fact that the parameter is determined by a ratio of quantities measured at the 
input terminals. 



Au If I i is set equal to zero by opening the input leads, the following results for 



*12 — 



V/ 

Vo 



A=o 



unitless 



( 5 . 136 ) 



The parameter A 12 , therefore, is the ratio of the input voltage to the output voltage with 
the input current equal to zero. It has no units because it is a ratio of voltage levels and is 
called the open-circuit reverse transfer voltage ratio parameter. The subscript 12 of A 12 
indicates that the parameter is a transfer quantity determined by a ratio of input (1) to out- 
put (2) measurements. The first integer of the subscript defines the measured quantity to 
appear in the numerator; the second integer defines the source of the quantity to appear in 
the denominator. The term reverse is included because the ratio is an input voltage over an 
output voltage rather than the reverse ratio typically of interest. 



a 2 . If in Eq. (5.134) V 0 is set equal to zero by again shorting the output terminals, the 
following results for A 21 : 



*21 = T 



v„=o 



unitless 



( 5 . 137 ) 



Note that we now have the ratio of an output quantity to an input quantity. The term forward 
will now be used rather than reverse as indicated for Ai 2 . The parameter A 2 i is the ratio of 
the output current to the input current with the output terminals shorted. This parameter, 
like Ai 2 , has no units because it is the ratio of current levels. It is formally called the short- 
circuit forward transfer current ratio parameter. The subscript 21 again indicates that it 
is a transfer parameter with the output quantity (2) in the numerator and the input quantity 
(1) in the denominator. 

h 22 The last parameter, A 22 , can be found by again opening the input leads to set f = 0 
and solving for A 22 in Eq. (5.134): 



*22 = VP 



siemens 



A=0 



( 5 . 138 ) 



Because it is the ratio of the output current to the output voltage, it is the output conductance 
parameter, and it is measured in siemens (S). It is called the open-circuit output admittance 
parameter. The subscript 22 indicates that it is determined by a ratio of output quantities. 



Because each term of Eq. (5.133) has the unit volt, let us apply Kirchhoff s voltage law 
“in reverse” to find a circuit that “fits” the equation. Performing this operation results in 
the circuit of Fig. 5.94. Because the parameter h n has the unit ohm, it is represented by a 
resistor in Fig. 5.94. The quantity h\ 2 is dimensionless and therefore simply appears as a 
multiplying factor of the “feedback” term in the input circuit. 

Because each term of Eq. (5.134) has the units of current, let us now apply Kirchhoff s 
current law “in reverse” to obtain the circuit of Fig. 5.95. Because h 2 2 has the units of 
admittance, which for the transistor model is conductance, it is represented by the resistor 
symbol. Keep in mind, however, that the resistance in ohms of this resistor is equal to the 
reciprocal of conductance (1/ ^ 22 )* 

The complete “ac” equivalent circuit for the basic three-terminal linear device is indi- 
cated in Fig. 5.96 with a new set of subscripts for the /z-parameters. The notation of Fig. 
5.96 is of a more practical nature because it relates the /z-parameters to the resulting ratio ob- 
tained in the last few paragraphs. The choice of letters is obvious from the following listing: 

h\\ input resistance — > h t 

/ii 2 — > reverse transfer voltage ratio — > h r 
h 2 1 —forward transfer current ratio — > hf 
h 22 — > output conductance — > h 0 



n 




+ 



Vi 




hi 



AAA/ 1 

+ 

KV„ % 






THE HYBRID 321 
EQUIVALENT MODEL 



I, 

O VW 1 

*.i + I 

hnV 0 % 



FIG. 5.94 

Hybrid input equivalent circuit. 




FIG. 5.95 

Hybrid output equivalent circuit. 



FIG. 5.96 

Complete hybrid equivalent circuit. 



The circuit of Fig. 5.96 is applicable to any linear three-terminal electronic device or system 
with no internal independent sources. For the transistor, therefore, even though it has 
three basic configurations, they are all three-terminal configurations , so that the resulting 
equivalent circuit will have the same format as shown in Fig. 5.96. In each case, the bottom 
of the input and output sections of the network of Fig. 5.96 can be connected as shown in 
Fig. 5.97 because the potential level is the same. Essentially, therefore, the transistor model 
is a three-terminal two-port system. The /^-parameters, however, will change with each 
configuration. To distinguish which parameter has been used or which is available, a second 




(a) 




(b) 



FIG. 5.97 

Common-emitter configuration: (a) graphical symbol ; (b) hybrid equivalent circuit. 



? + 







322 BJT AC ANALYSIS 



subscript has been added to the /z-parameter notation. For the common-base configuration, 
the lowercase letter b was added, whereas for the common-emitter and common-collector 
configurations, the letters e and c were added, respectively. The hybrid equivalent network 
for the common-emitter configuration appears with the standard notation in Fig. 5.97. Note 
that 7/ = I h , I Q = I c , and, through an application of Kirchhoff ’ s current law, I e = I b + I c . 
The input voltage is now V be , with the output voltage V ce . For the common-base configura- 
tion of Fig. 5.98, I t = I e , I 0 = I c with V eb = V t and V cb = V Q . The networks of Figs. 5.97 
and 5.98 are applicable for pnp or npn transistors. 



1* 




Ic 


E 

+ 




JT 


C 

+ 


Veb 


■'*t 


!> 


V cb 



B 



(a) 




(b) 



FIG. 5.98 

Common-base configuration: (a) graphical symbol; (b) hybrid equivalent circuit. 



The fact that both a Thevenin and a Norton circuit appear in the circuit of Fig. 5.96 was 
further impetus for calling the resultant circuit a hybrid equivalent circuit. Two additional 
transistor equivalent circuits, not to be discussed in this text, called the z-parameter and 
y-parameter equivalent circuits, use either the voltage source or the current source, but not 
both, in the same equivalent circuit. In Appendix A the magnitudes of the various param- 
eters will be found from the transistor characteristics in the region of operation resulting in 
the desired small-signal equivalent network for the transistor. 

For the common-emitter and common-base configurations, the magnitude of h r and h Q 
is often such that the results obtained for the important parameters such as Z h Z Q , A v , and 
Af are only slightly affected if h r and h Q are not included in the model. 

Because h r is normally a relatively small quantity, its removal is approximated by 
h r = 0 and h r V 0 = 0, resulting in a short-circuit equivalent for the feedback element as 
shown in Fig. 5.99. The resistance determined by 1 /h 0 is often large enough to be ignored 
in comparison to a parallel load, permitting its replacement by an open-circuit equivalent 
for the CE and CB models, as shown in Fig. 5.99. 

The resulting equivalent of Fig. 5.100 is quite similar to the general structure of the 
common-base and common-emitter equivalent circuits obtained with the r e model. In fact, 




FIG. 5.99 

Effect of removing h re and h oe from the hybird 
equivalent circuit. 



FIG. 5.100 

Approximate hybrid equivalent model. 







the hybrid equivalent and the r e models for each configuration are repeated in Fig. 5.101 
for comparison. It should be reasonably clear from Fig. 5.101a that 



THE HYBRID 323 
EQUIVALENT MODEL 



and 



hie fi r e 



hfe Pac 



From Fig. 5.101b, 



and 



hib r e 



h fb = -U = 



(5.139) 

(5.140) 

(5.141) 

(5.142) 



In particular, note that the minus sign in Eq. (5.142) accounts for the fact that the current 
source of the standard hybrid equivalent circuit is pointing down rather than in the actual 
direction as shown in the r e model of Fig. 5.101b. 




(a) 




(b) 

FIG. 5.101 

Hybrid versus r e model: (a) common- emitter configuration; (b) common-base configuration. 



EXAMPLE 5.19 Given I E = 2.5 mA ,hf e = 140, h oe = 20 /jlS (^trnho), and h ob = 0.5 /jlS, 
determine: 

a. The common-emitter hybrid equivalent circuit. 

b. The common-base r e model. 



Solution: 



26 mV 26 mV 



a. r p = 



10.4 il 



I E 2.5 mA 
h ie = p r e = (140)(10.4 O) = 1.456 kH 
J_ _ 1 

9 h oe 20 /ulS 



= 50 kH 










324 BJT AC ANALYSIS 



Note Fig. 5.102. 




FIG. 5.102 

Common-emitter hybrid equivalent circuit for the parameters of Example 5.19. 



b. r e = 10.4 il 



Note Fig. 5.103. 



1 

0.5 ilS 



2 Mil 




FIG. 5.103 

Common-base r e model for the parameters of Example 5.19. 



A series of equations relating the parameters of each configuration for the hybrid 
equivalent circuit is provided in Appendix B. In Section 5.23 it is demonstrated that the 
hybrid parameter hf e (/3 ac ) is the least sensitive of the hybrid parameters to a change in col- 
lector current. Assuming, therefore, that hf e = /3 is a constant for the range of interest, is 
a fairly good approximation. It is h ie = (3r e that will vary significantly with I c and should 
be determined at operating levels because it can have a real effect on the gain levels of a 
transistor amplifier. 

5-20 APPROXIMATE HYBRID EQUIVALENT CIRCUIT ^ 

The analysis using the approximate hybrid equivalent circuit of Fig. 5.104 for the common- 
emitter configuration and of Fig. 5.105 for the common-base configuration is very similar 
to that just performed using the r e model. A brief overview of some of the most important 
configurations will be included in this section to demonstrate the similarities in approach 
and the resulting equations. 




oC 



oE 




FIG. 5.104 

Approximate common- emitter hybrid equivalent circuit. 



FIG. 5.105 

Approximate common-base hybrid equivalent circuit. 







Because the various parameters of the hybrid model are specified by a data sheet or APPROXIMATE HYBRID 325 
experimental analysis, the dc analysis associated with use of the r e model is not an integral EQUI VALENT CIRCUIT 

part of the use of the hybrid parameters. In other words, when the problem is presented, the 
parameters such as h ie , hf e , and so on, are specified. Keep in mind, however, that the 
hybrid parameters and components of the r e model are related by the following equations, as 
discussed earlier in this chapter: h ie = fir e , hf e = fi,h oe = l/r Q ,hfi 7 = — a, and = r e . 

Fixed-Bias Configuration 

For the fixed-bias configuration of Fig. 5.106, the small-signal ac equivalent network will 
appear as shown in Fig. 5.107 using the approximate common-emitter hybrid equivalent 
model. Compare the similarities in appearance with Fig. 5.22 and the r e model analysis. 

The similarities suggest that the analyses will be quite similar, and the results of one can be 
directly related to the other. 



Vcc 





FIG. 5.107 

Substituting the approximate hybrid equivalent circuit into the ac 
equivalent network of Fig. 5.106. 



Zj From Fig. 5.107, 

Z-i “ RpWhie 



Z 0 From Fig. 5.107, 



Z 0 = Rcll/ha 



A v Using/?' = l/h oe \\R c , we obtain 



and 

with 



V. = -I 0 R' = -I C R' 

— -hfehR' 

I =Tl 

b h ie 

Vi 

Vo = -hfefR' 

rijf, 



so that 



A = Vo = _h ie (R c \\l/h oe ) 



V 



h:. 



( 5 . 143 ) 

( 5 . 144 ) 



( 5 . 145 ) 



Aj Assuming that R B ?5> h ie and 1 /h oe s 10/?c, we find //, = /,• and I 0 = l c = 
hfeh = hf e Ij, and so 



A; = ~r — h 



I, 



ife 



( 5 . 146 ) 



? + 




326 BJT AC ANALYSIS 



EXAMPLE 5.20 For the network of Fig. 5.108, determine: 



a. 


Z, 


b. 


z 0 . 


c. 


A v . 


d. 


A/. 




FIG. 5.108 

Example 5.20. 



Solution: 

a. Z, = R B \\h ie = 330 kO || 1.175 kO 

= h* = 1.171 kfl 



b. r n = — — = 



1 



h oe 20 /iA /V 

1 



= 50kH 



Z 0 = — \\R C = 50 kn||2.7 kO = 2.56 kli s R, 
h np 



c 



hfe(R c II 1 /hoe) (120)(2.7 kH || 50 kft) 
c. A v = = — — — — = —262.34 



hie 

d. A t = h fe = 120 



1.171 kfl 



Voltage-Divider Configuration 

For the voltage-divider bias configuration of Fig. 5.109, the resulting small-signal ac 
equivalent network will have the same appearance as Fig. 5.107, with R B replaced by 
R' = Ri\\R 2 . 



v cc 




FIG. 5.109 

Voltage -divider bias configuration. 



Z/ From Fig. 5.107 with R B = R ' , 



( 5 . 147 ) 



APPROXIMATE HYBRID 327 
EQUIVALENT CIRCUIT 



Z[ — R\\R2\h ie 



Z 0 From Fig. 5.107, 

z 0 — Rc 



A v 

h fe (R c \\l/h oe ) 



hfe(Rl\\R2) 

R\ || R2 + h ie 



( 5 . 148 ) 



( 5 . 149 ) 



( 5 . 150 ) 



Unbypassed Emitter-Bias Configuration 

For the CE unbypassed emitter-bias configuration of Fig. 5.110, the small-signal ac model 
will be the same as Fig. 5.30, with (3r e replaced by h ie and (31 b by hf e I E The analysis will 
proceed in the same manner. 



Vcc 




FIG. 5.110 

CE unbypassed emitter-bias configuration. 



z-, 



and 

Zo 



A v 



Zb = hf e R E 



Zi — R B \\Z b 



( 5 . 151 ) 

( 5 . 152 ) 




hfeRc hfeRc 

Z b hf e R E 




( 5 . 153 ) 



and 



( 5 . 154 ) 



328 BJT AC ANALYSIS 



A 



or 



hf e R B 
R b + Z b 



( 5 . 155 ) 




( 5 . 156 ) 



Emitter-Follower Configuration 

For the emitter-follower of Fig. 5.38, the small-signal ac model will match that of Fig. 
5.111, with (3r e = h ie and /3 = hf e . The resulting equations will therefore be quite similar. 




FIG. 5.111 

Emitter-follower configuration. 



i, 



Z b hf e R E 



Zi — R B \\Z h 



( 5 . 157 ) 

( 5 . 158 ) 



Z 0 For Z 0 , the output network defined by the resulting equations will appear as shown in 
Fig. 5.112. Review the development of the equations in Section 5.8 and 



or, because 1 + hf e = hf e , 



— R e 



hie 

1 + hf e 



II hie 

z c s Re W-t 

hfe 



( 5 . 159 ) 




FIG. 5.112 

Defining Z 0 for the emitter-follower configuration. 



APPROXIMATE HYBRID 329 
EQUIVALENT CIRCUIT 



A v For the voltage gain, the voltage-divider rule can be applied to Fig. 5. 1 12 as follows: 



but, since 1 + hf e = hf e . 



V n 



R E (Vi) 

R E + h ie /(l + hfe ) 



Yo __ 

Vi Re + h ie /hf e 



( 5 . 160 ) 



A, 



hfe Rfi 

r b + z b 



( 5 . 161 ) 



or 




( 5 . 162 ) 



Common-Base Configuration 

The last configuration to be examined with the approximate hybrid equivalent circuit will be 
the common-base amplifier of Fig. 5.113. Substituting the approximate common-base hybrid 
equivalent model results in the network of Fig. 5.114, which is very similar to Fig. 5.44. 



Kb< V 





Substituting the approximate hybrid equivalent circuit into the ac equivalent network 

of Fig. 5.113. 



We have the following results from Fig. 5.1 14. 






Z, — r e\\ hjh 



( 5 . 163 ) 



Z„ 




( 5 . 164 ) 




330 BJT AC ANALYSIS 



Av 



with 



so that 



Ai 



V 0 = -I 0 R C = 

, V > A 

4 = — and 

h ih 



—{hf b I e )R c 

Vo = ~hf b — L R c 

h ib 




hf b R c 

hib 



( 5 . 165 ) 



A; = — = h 



h 



Ifb 



-1 



( 5 . 166 ) 



EXAMPLE 5.21 For the network of Fig. 5.115, determine: 



a. 


Z, 


b. 


z 0 . 


c. 


A v . 


d. 


A/. 




Solution: 



a. Z ( 

b. r a 

c. A v 

d. Aj 



R E \\h ib = 2.2 kft|| 14.3 ft = 14.21 ft = h ib 

— = — — = 2 Mft 

h ob 0.5 /jb A/V 

— — — ||/?c = R c = 3.3 kft 

"ob 

hfb R C _ 
hib 

h fb = “ 1 



(—0.99X3.3 kll) 
14.21 



= 229.91 



The remaining configurations that were not analyzed in this section are left as an exercise 
in the problem section of this chapter. It is assumed that the analysis above clearly reveals the 
similarities in approach using the r e or approximate hybrid equivalent models, thereby 
removing any real difficulty with analyzing the remaining networks of the earlier sections. 

5-21 COMPLETE HYBRID EQUIVALENT MODEL ^ 

The analysis of Section 5.20 was limited to the approximate hybrid equivalent circuit with 
some discussion about the output impedance. In this section, we employ the complete 
equivalent circuit to show the effect of h r and define in more specific terms the effect of h Q . 
It is important to realize that because the hybrid equivalent model has the same appearance 
for the common-base, common-emitter, and common-collector configurations, the equa- 
tions developed in this section can be applied to each configuration. It is only necessary to 



insert the parameters defined for each configuration. That is, for a common-base configu- COMPLETE HYBRID 331 

ration, h h ib , and so on, are employed, whereas for a common-emitter configuration, hf e , EQUIVALENT MODEL 

h ie , and so on, are used. Recall that Appendix A permits a conversion from one set to the 
other if one set is provided and the other is required. 

Consider the general configuration of Fig. 5.116 with the two-port parameters of particu- 
lar interest. The complete hybrid equivalent model is then substituted in Fig. 5.117 using 
parameters that do not specify the type of configuration. In other words, the solutions will 
be in terms of h b h r , hp and h Q . Unlike the analysis of previous sections of this chapter, 
here the current gain A t will be determined first because the equations developed will prove 
useful in the determination of the other parameters. 




FIG. 5.116 

Two-port system. 




FIG. 5.117 

Substituting the complete hybrid equivalent circuit into the two-port system of Fig. 5.116. 

Current Gain, A-, = l 0 /lj 

Applying Kirchhoff’ s current law to the output circuit yields 

I 0 = hfl b + I = hff + = hfl t + h 0 V 0 

Substituting V 0 = ~I 0 Rl gives 

Iq tyli h() RJo 
Rewriting the equation above, we have 

Iq KRJo tyli 
and I 0 (\ + h 0 R L ) = hff 



so that 





h f 


A> ~ h ~ 


1 + h 0 R L 



( 5 . 167 ) 



Note that the current gain reduces to the familiar result of A t = hf if the factor h 0 R L is suf- 
ficiently small compared to 1 . 



Voltage Gain, A v = VJVj 

Applying Kirchhoff s voltage law to the input circuit results in 

Vi = iA + h r v a 





332 BJT AC ANALYSIS 



Substituting I t = (1 + h 0 R L )I 0 /hf from Eq. (5.167) and I 0 = ~V 0 /Rl from above 
results in 



V/ = 

Solving for the ratio V 0 / V t yields 



-(1 + h 0 R L )hj 
h f R L 



V 0 + h r y o 




~ ll f R L 

hi + (hfhg — hfh r )R L 



( 5 . 168 ) 



In this case, the familiar form of A v = —hfR L /hi returns if the factor ( hih 0 — hfh r )R L is 
sufficiently small compared to h t . 



Input Impedance, 1-, = !/>/#/ 



For the input circuit, 

Substituting 
we have 

Because 



Vi = hilt + h r V 0 
Vo = -IoRl 
Vi = hJi - h r R L I 0 



h = M 



so that the equation above becomes 

Vi = hjli - hyRjAJi 

Solving for the ratio V, •//,•, we obtain 



and substituting 



Vi 

Z, = — = hi - h r R L Ai 

' i 



A, = 



h _j 

1 + h 0 R L 



yields 



Vi _ h f h r R L 

Ti~ hi ~ i + kr l 



( 5 . 169 ) 



The familiar form of Z ( - = /), is obtained if the second factor in the denominator {h 0 R£) is 
sufficiently smaller than one. 



Output Impedance, Z 0 = V 0 /l 0 

The output impedance of an amplifier is defined to be the ratio of the output voltage to the 
output current with the signal V s set to zero. For the input circuit with V s = 0, 

7 = KV 0 

R s + hi 

Substituting this relationship into the equation from the output circuit yields 



Iq fyli T h 0 V 0 

+ h n V n 



hfhyV q 



Rs + ^ 



and 



Zo 



Vo = 1 

Io h 0 - \ h f h r /(hi + R s )] 



( 5 . 170 ) 



In this case, the output impedance is reduced to the familiar form Z 0 = l/h 0 for the transis- 
tor when the second factor in the denominator is sufficiently smaller than the first. 



COMPLETE HYBRID 333 
EQUIVALENT MODEL 



EXAMPLE 5.22 For the network of Fig. 5.118, determine the following parameters using 
the complete hybrid equivalent model and compare to the results obtained using the 
approximate model. 

a. Zj and Z\. 

b. A v . 

c. A f = I 0 /I, 

d. Z' 0 (within R c ) and Z Q (including R c ). 




Solution: Now that the basic equations for each quantity have been derived, the order in 
which they are calculated is arbitrary. However, the input impedance is often a useful quan- 
tity to know, and therefore will be calculated first. The complete common-emitter hybrid 
equivalent circuit has been substituted and the network redrawn as shown in Fig. 5.119. A 
Thevenin equivalent circuit for the input section of Fig. 5.119 results in the input equivalent 
of Fig. 5.120 because E Th = V s and R Th = R s = 1 kll (a result of R B = 470 kll being 
much greater than R s = 1 kll). In this example, R L = R c , and I 0 is defined as the current 
through R c as in previous examples of this chapter. The output impedance Z Q as defined 
by Eq. (5.170) is for the output transistor terminals only. It does not include the effects 
of R c . Z 0 is simply the parallel combination of Z 0 and R L . The resulting configuration of 




% 2x10~ 4 V o | 110 I b >50k£2 4.7 



FIG. 5.119 

Substituting the complete hybrid equivalent circuit into the ac equivalent network of Fig. 5.118. 



? + 





2 x 10" 4 V n 




FIG. 5.120 

Replacing the input section of Fig. 5.119 with a Thevenin equivalent circuit. 



Fig. 5.120 is then an exact duplicate of the defining network of Fig. 5.117, and the equa- 
tions derived above can be applied. 



a. Eq. (5.169): 



Z, = 



Vi hjJfl re Rp 

T t ~ hie ~ 1 + KeR L 



, „ (110)(2 X 10“ 4 )(4.7 kil) 

= 1.6 kil — — 

1 + (20 fx S)(4.7 kil) 

= 1.6 kil - 94.52 il 

= 1.51 kil 



versus 1.6 kil using simply h ie \ and 

Z; = 470 kil || Z ; = Z, = 1.51 kil 

b. Eq. (5.168): 

A _ V o_ _ ~ h fe R L 

k) hie 4" (hjji 0e hf e h re )Ri 

_ -(110X4.7 kil) 

1.6 kil + [(1.6 kil)(20 yuS) - (110)(2 X 10" 4 )]4.7 kil 

_ -517 X 10 3 il 

_ 1.6 kil + (0.032 - 0.022)4.7 kil 
_ -517 X 10 3 il 
~~ 1.6 kil + 47 il 



= -313.9 

versus —323.125 using A v = —hf e Rp/h ie . 
c. Eq. (5.167): 

I n hfe 



A' = — = 

1 /• 1 + h np R 



110 



110 

1 + 0.094 



oe is L 1 + (20 ^S)(4.7 kil) 

= 100.55 



versus 110 using simply hf e . Because 470 kfl » Z-, = /• and A t = 100.55 also, 

d. Eq. (5.170): 



lo hoe \hf e h re / ( 'Hie "E Rg)~\ 

1 

20 - [(110)(2 X 10 _4 )/(1.6 kil + 1 kil)] 

1 

20 pi S — 8.46 pi S 
1 



334 



11.54 pi S 

= 86.66 kil 




COMPLETE HYBRID 335 
EQUIVALENT MODEL 



which is greater than the value determined from 1 / h oe , 50 kft; and 
Z 0 = R C \\Z' = 4.7 m|| 86.66 kO = 4.46 kll 
versus 4.7 kll using only 7? c . 



Note from the results above that the approximate solutions for A v and were very close 

to those calculated with the complete equivalent model. In fact, even A/ was off by less than 
10%. The higher value of Z' Q only contributed to our earlier conclusion that Z' Q is often so 
high that it can be ignored compared to the applied load. However, keep in mind that when 
there is a need to determine the effect of h re and h oe , the complete hybrid equivalent model 
must be used, as described earlier. 

The specification sheet for a particular transistor typically provides the common-emitter 
parameters as noted in Fig. 5.92. The next example will employ the same transistor pa- 
rameters appearing in Fig. 5.118 in a pnp common-base configuration to introduce the 
parameter conversion procedure and emphasize the fact that the hybrid equivalent model 
maintains the same layout. 



EXAMPLE 5.23 For the common-base amplifier of Fig. 5.121, determine the following 
parameters using the complete hybrid equivalent model and compare the results to those 
obtained using the approximate model. 

a. Z 

b. A i 

c. A v . 

d. Z 0 




FIG. 5.121 

Example 5.23. 



Solution: The common-base hybrid parameters are derived from the common-emitter 
parameters using the approximate equations of Appendix B: 



Kb 



hie 

1 + hf e 



1.6 kll 
1 + 110 



= 14.41 il 



Note how closely the magnitude compares with the value determined from 



Also, 



h ie 1.6 kfl _ 

Kb ~ r e ~ ~ ,, ^ — 14.55 O 

w e p no 

KeKe j (1.6kH)(20 fxS) ^ w __ 4 

h rh = h rp = 2 X 10 

rb 1 + hf e re 1 + 110 



= 0.883 X 10“ 4 



-h 



Ife 



n fb 



hob 



-110 



1 + hfe 1 + 110 

^ 20 llS 



-0.991 



1 + hfe 1 + 110 



= 0.18 iulS 





FIG. 5.122 

Small-signal equivalent for the network of Fig. 5.121. 



Substituting the common-base hybrid equivalent circuit into the network of Fig. 5.121 
results in the small-signal equivalent network of Fig. 5.122. The Thevenin network for the 
input circuit results in 7? Th = 3 kll || 1 kI2 = 0.75 kll for R s in the equation for Z 0 . 

a. Eq. (5.169): 

_Vj__ _ hfbhrbRL 

l ~n~ ib ~ 1 + h ob R L 

(— 1.991)(0.883 X 10 _4 )(2.2 kft) 

= 14.41 ft - 

1 + (0.18 fjiS)(2.2 kft) 

= 14.41 12 + 0.1912 

= 14.6012 



versus 14.41 12 using Z, = h ib , and 

Z ; = 3 kft||Z< = Z'i = 14.60 ft 



b. Eq. (5.167): 




h fl> 

1 + h ob R, 



_ -0.991 

” 1 + (0.18 /jlS)(2.2 kft) 
= -0.991 



Because 3 kll » Z-, I t = /• and A t = I 0 /Ii = — 1. 

c. Eq. (5.168): 



Vo = -hfb R L 

Vi hjb "E (hi b h nb hfbh rb )Ri 

-(-0.991X2.2 kft) 

14.41 ft + [(14.4112X0.18 fiS) - (-0.991)(0.883 X 10“ 4 )]2.2kft 



= 149.25 



versus 151.3 using A v = —h^Ri/huy. 

d. Eq. (5.170): 



hob \hfbh r b / ( 'Hib Rs) \ 

_ 1 

0.18 /xS - [(-0.991X0.883 X 10 _4 )/(14.41 12 + 0.75 kO)] 
_L 

~~ 0.295 /I S 

= 3.39 Mil 



versus 5.56 Mil using Z' Q = 1/ h^. For Z Q as defined by Fig. 5.122, 
Z 0 = R C \\Z' 0 = 2.2 kll || 3.39 Mil = 2.199 
versus 2.2 kll using Z 0 = R c . 



336 




5.22 HYBRID tt MODEL 



HYBRID 77 MODEL 337 



The last transistor model to be introduced is the hybrid 77 model of Fig. 5.123 which 
includes parameters that do not appear in the other two models primarily to provide a more 
accurate model for high-frequency effects. 




Giacoletto (or hybrid tt) high-frequency transistor small-signal ac equivalent circuit. 

* 77 ' r O' r b' and r u 

The resistors r n , r 0 , r^, and r u are the resistances between the indicated terminals of the 
device when the device is in the active region. The resistance (using the symbol tt to agree 
with the hybrid 77 terminology) is simply (3r e as introduced for the common-emitter r e model. 
That is, 




(5.171) 



The output resistance r Q is the output resistance normally appearing across an applied 
load. Its value, which typically lies between 5 kll and 40 kll, is determined from the hybrid 
parameter h oe , the Early voltage, or the output characteristics. 

The resistance r ^ includes the base contact, base bulk, and base spreading resistance levels. 
The first is due to the actual connection to the base. The second includes the resistance from 
the external terminal to the active region of the transistor, and the last is the actual resistance 
within the active base region. It is typically a few ohms to tens of ohms. 

The resistance r u (the subscript u refers to the union it provides between collector and 
base terminals) is a very large resistance and provides a feedback path from output to 
input circuits in the equivalent model. It is typically larger than /3 r Q , which places it in the 
megohm range. 



and C„ 

All the capacitors that appear in Fig. 5.123 are stray parasitic capacitors between the vari- 
ous junctions of the device. They are all capacitive effects that really only come into play 
at high frequencies. For low to mid-frequencies their reactance is very large, and they can 
be considered open circuits. The capacitor C \ across the input terminals can range from a 
few pF to tens of pF. The capacitor C u from base to collector is usually limited to a few pF 
but is magnified at the input and output by an effect called the Miller effect, to be intro- 
duced in Chapter 9. 



pi’b or 9rn V 7T 

It is important to note in Fig. 5.123 that the controlled source can be a voltage-controlled 
current source (VCCS) or a current-controlled current source (CCCS), depending on the 
parameters employed. 

Note the following parameter equivalence in Fig. 5.123: 



1 

8m ~ 

' e 



(5.172) 




338 BJT AC ANALYSIS 



and 



1 



( 5 . 173 ) 



with 



+ r u 




( 5 . 174 ) 



Take particular note of the fact that the equivalent sources f3I l and gmV^ are both con- 
trolled current sources. One is controlled by a current at another place in the network and 
the other by a voltage at the input side of the network. The equivalence between the two 
is defined by 

fit b * 8mlbfi r e Sm^b^ir) SmYir 

r e 

For the broad range of low- to mid-frequency analysis, the effect of the stray capaci- 
tive effects can be ignored due to the very high reactance levels associated with each. The 
resistance r ^ is usually small enough with other series elements to be ignored while the 
resistance r u is usually large enough compared to parallel elements to be ignored. The result 
is an equivalent network similar to the r e model introduced and applied in this chapter. 

In Chapter 9, when high-frequency effects are considered, the hybrid i t model will be 
the model of choice. 



5-21 VARIATIONS OF TRANSISTOR PARAMETERS ^ 

A variety of curves can be drawn to show the variations of the transistor parameters with tem- 
perature, frequency, voltage, and current. The most interesting and useful at this stage of the 
development include the variations with junction temperature and collector voltage and current. 

The effect of the collector current on the r e model and hybrid equivalent model is shown 
in Fig. 5.124. Take careful note of the logarithmic scale on the vertical and horizontal axes. 
Logarithmic scales will be examined in detail in Chapter 9. The parameters have all been 
normalized (a process described in detail in Section 9.5) to unity so that the relative change 
in magnitude with collector current can easily be determined. On each set of curves, such 
as in Figs. 5.124 to 5.126, the operating point at which the parameters were determined 
is always indicated. For this particular situation, the quiescent point is at the fairly typical 
values of Vqe — 5.0 V and Iq = 1.0 mA. Because the frequency and temperature of operation 




FIG. 5.124 

Hybrid parameter variations with collector current. 



also affect the parameters, these quantities are also indicated on the curves. Figure 5.124 
shows the variation of the parameters with collector current. Note that at I c = 1 mA the 
value of all the parameters has been normalized to 1 on the vertical axis. The result is that 
the magnitude of each parameter is compared to the values at the defined operating point. 
Because manufacturers typically use the hybrid parameters for plots of this type, they are 
the curves of choice in Fig. 5.124. However, to broaden the use of the curves the r e and 
hybrid tt equivalent parameters have also been added. 

At first glance it is particularly interesting to note that: 

The parameter hf e ((3) varies the least of all the parameters of a transistor equivalent 
circuit when plotted against variations in collector current 

Figure 5. 124 clearly reveals that for the full range of collector current the parameter hf e Q3 ) 
varies from 0.5 of its g-point value to a peak of about 1.5 times that value at a current of 
about 6 mA. For a transistor with a /3 of 100, it therefore varies from about 50 to 150. This 
seems like quite a bit, but look at h oe , which jumps to almost 40 times its g-point value at 
a collector current of 50 mA. 

Figure 5.124 also shows that h oe ( 1 /r 0 ) and h ie ((3r e ) vary the most for the chosen current 
range. The parameter h ie varies from about 10 times its g-point value down to about one 
tenth the g point value at 50 mA. This variation, however, should be expected because we 
know that the value of r e is directly related to the emitter current by r e = 26 mV// £ . As 
I E (=I C ) increases, the value of r e and therefore (3r e will decrease, as shown in Fig. 5.124. 

Keep in mind as you review the curve of h oe versus current that the actual output resis- 
tance r Q is 1 /h oe . Therefore, as the curve increases with current, the value of r Q becomes 
less and less. Because r Q is a parameter that normally appears in parallel with the applied 
load, decreasing values of r Q can become a critical problem. The fact that r Q has dropped to 
almost 1/40 of its value at the g-point could spell a real reduction in gain at 50 mA. 

The parameter h re varies quite a bit, but because its g-point value is usually small enough 
to permit ignoring its effect, it is a parameter that is only of concern for collector currents 
that are much less, or quite a bit more, than the g-point level. 

This may seem like an extensive description of a set of characteristic curves. However, 
experience has revealed that graphs of this nature are too often reviewed without taking the 
time to fully appreciate the broad impact of what they are providing. These plots reveal a 
lot of information that could be extremely useful in the design process. 

Figure 5.125 shows the variation in magnitude of the parameters due to changes in 
collector-to-emitter voltage. This set of curves is normalized at the same operating point 
as the curves of Fig. 5.124 to permit comparisons between the two. In this case, however, 
the vertical scale is in percent rather than whole numbers. The 200% level defines a set of 
parameters twice that at the 100% level. A level of 1000% would reflect a 10:1 change. 
Note that hf e and h ie are relatively steady in magnitude with variations in collector-to- 
emitter voltage, whereas for changes in collector current the variation is a great deal more 



VARIATIONS OF 339 
TRANSISTOR 
PARAMETERS 




FIG. 5.125 

Hybrid parameter variations with collector-emitter potential. 



340 BJT AC ANALYSIS 



significant. In other words, if you want a parameter such as h ie (l3r e ) to remain fairly steady, 
keep the variation of Ic to a minimum while worrying less about variations in the collector- 
to-emitter voltage. The variation of h oe and h ie remains significant for the indicated range 
of collector- to-emitter voltage. 

In Fig. 5.126, the variation in parameters is plotted for changes injunction temperature. 
The normalization value is taken to be room temperature, T = 25 °C. The horizontal scale 
is now a linear scale rather than the logarithmic scale employed in the two previous figures. 
In general: 

All the parameters of a hybrid transistor equivalent circuit increase with temperature. 




FIG. 5.126 

Hybrid parameter variations with temperature. 



However, again keep in mind that the actual output resistance r Q is inversely related 
to h oe , so its value drops with an increase in h oe . The greatest change is in h ie , although 
note that the range of the vertical scale is considerably less than in the other plots. At a 
temperature of 200°C the value of h ie is almost 3 times its Q - point value, but in Fig. 5.124 
parameters jumped to almost 40 times the g-point value. 

Of the three parameters, therefore, the variation in collector current has by far the great- 
est effect on the parameters of a transistor equivalent circuit. Temperature is always a factor, 
but the effect of the collector current can be significant. 

5-24 TROUBLESHOOTING ^ 

Although the terminology troubleshooting suggests that the procedures to be described are 
designed simply to isolate a malfunction, it is important to realize that the same techniques 
can be applied to ensure that a system is operating properly. In any case, the testing, check- 
ing, and isolating procedures require an understanding of what to expect at various points 
in the network in both the dc and ac domains. In most cases, a network operating correctly 
in the dc mode will also behave properly in the ac domain. 

In general, therefore, if a system is not working properly, first disconnect the ac source 
and check the dc biasing levels. 

In Fig. 5.127 we have four transistor configurations with specific voltage levels provided 
as measured by a DMM in the dc mode. The first test of any transistor network is to simply 
measure the base-to-emitter voltage of the transistor. The fact that it is only 0.3 V in this 
case suggests that the transistor is not “on” and perhaps sitting in its saturation mode. If this 
is a switching design then the result is expected, but if in the amplifier mode there is an open 
connection preventing the base voltage from reaching an operating level. 



18 Y 



12 Y 




FIG. 5.127 

Checking the dc levels to determine if a network is properly biased. 

In Fig. 5.127b the fact that the voltage at the collector equals the supply voltage reveals 
that there is no drop across the resistor R c and the collector current is zero. The resistor R c 
is connected properly because it made the connection from the dc source to the collector. 
However, any one of the other elements may not have been connected properly, resulting 
in the absence of a base or collector current. In Fig. 5.127c the voltage drop across the 
collector-to-emitter voltage is too small compared with the applied dc voltage. Normally 
the voltage V CE is in the mid-range of perhaps 6 V to 14 V. A reading of 18 V would cause 
the same concern as the reading of 3 V. The fact that the voltage levels exist at all suggests 
that all the elements are connected but the value of one or more of the resistive elements 
may be wrong. In Fig. 5.127d we find that the voltage at the base is exactly half the supply 
voltage. We know from this chapter that the resistance R E will reflect back to the base by 
a factor of beta and appear in parallel with R 2 . The result would be a base voltage less than 
half the supply voltage. The measurement suggests that the base lead is not connected to 
the voltage divider, causing an even split of the 20- V source. 

In a typical laboratory setting, the ac response at various points in the network is checked 
with an oscilloscope as shown in Fig. 5.128. Note that the black (gnd) lead of the oscillo- 
scope is connected directly to ground and the red lead is moved from point to point in the 




FIG. 5.128 

Using the oscilloscope to measure and display various voltages of a BJT amplifier. 



341 



342 BJT AC ANALYSIS 



network, providing the patterns appearing in Fig. 5.128. The vertical channels are set in 
the ac mode to remove any dc component associated with the voltage at a particular point. 
The small ac signal applied to the base is amplified to the level appearing from collector to 
ground. Note the difference in vertical scales for the two voltages. There is no ac response 
at the emitter terminal due to the short-circuit characteristics of the capacitor at the applied 
frequency. The fact that v 0 is measured in volts and v t in millivolts suggests a sizable gain 
for the amplifier. In general, the network appears to be operating properly. If desired, the 
dc mode of the multimeter could be used to check V BE and the levels of V B , Vce* an d V E to 
review whether they lie in the expected range. Of course, the oscilloscope can also be used 
to compare dc levels simply by switching to the dc mode for each channel. 

A poor ac response can be due to a variety of reasons. In fact, there may be more than 
one problem area in the same system. Fortunately, however, with time and experience, the 
probability of malfunctions in some areas can be predicted, and an experienced person can 
isolate problem areas fairly quickly. 

In general, there is nothing mysterious about the general troubleshooting process. If you 
decide to follow the ac response, it is good procedure to start with the applied signal and 
progress through the system toward the load, checking critical points along the way. An 
unexpected response at some point suggests that the network is fine up to that area, thereby 
defining the region that must be investigated further. The waveform obtained on the oscil- 
loscope will certainly help in defining the possible problems with the system. 

If the response for the network of Fig. 5.128 is as appears in Fig. 5.129, the network has 
a malfunction that is probably in the emitter area. An ac response across the emitter is unex- 
pected, and the gain of the system as revealed by v 0 is much lower. Recall for this configuration 
that the gain is much greater if R E is bypassed. The response obtained suggests that R E is not 
bypassed by the capacitor, and the terminal connections of the capacitor and the capacitor itself 
should be checked. In this case, a checking of the dc levels will probably not isolate the problem 
area because the capacitor has an “open-circuit” equivalent for dc. In general, prior knowledge 
of what to expect, familiarity with the instrumentation, and, most important, experience are all 
factors that contribute to the development of an effective approach to the art of troubleshooting. 




5-25 PRACTICAL APPLICATIONS ^ 

Audio Mixer 

When two or more signals are to be combined into a single audio output, mixers such as 
shown in Fig. 5.130 are employed. The potentiometers at the input are the volume controls 
for each channel, with potentiometer R 3 included to provide additional balance between 



PRACTICAL 343 
APPLICATIONS 




FIG. 5.130 

Audio mixer. 

the two signals. Resistors R 4 and R 5 are there to ensure that one channel does not load 
down the other, that is, to ensure that one signal does not appear as a load to the other, 
draw power, and affect the desired balance on the mixed signal. 

The effect of resistors R 4 and R 5 is an important one that should be discussed in some 
detail. A dc analysis of the transistor configuration results in r e = 11.71 fl, which will 
establish an input impedance to the transistor of about 1.4 kfl. The parallel combination of 
* 6 II Z[ is also approximately 1.4 kft. Setting both volume controls to their maximum value 
and the balance control R 3 to its midpoint result in the equivalent network of Fig. 5.131a. 
The signal at v\ is assumed to be a low-impedance microphone with an internal resistance 
of 1 kfl. The signal at V 2 is assumed to be a guitar amplifier with a higher internal imped- 
ance of 10 kfl. Because the 470-kfl and 500-kfl resistors are in parallel for the above 
conditions, they can be combined and replaced with a single resistor of about 242 kfl. Each 
source will then have an equivalent such as shown in Fig. 5.131b for the microphone. Ap- 
plying Thevenin’s theorem shows that it is an excellent approximation to simply drop the 
242 kfl and assume that the equivalent network is as shown for each channel. The result 
is the equivalent network of Fig. 5.131c for the input section of the mixer. Applying the 
superposition theorem results in the following equation for the ac voltage at the base of the 
transistor: 

(1.4 kfl || 43 kfl)v Sl (1.4 kfl || 34 kfl)v , 2 

Vb ~ 34 kft + (1.4 kft || 43 kft) + 43 kft + (1.4 kft || 34 kft) 

= 38 X 10 _ 3 v 5l + 30 X 10 - 3 Vy 2 

Withr^ = 11.71 fl, the gain of the amplifier is —R c /r e = 3.3 kfl/1 1.71 fl = -281.8, 
and the output voltage is 

= -10.7v 5l - 8.45v 52 

which provides a pretty good balance between the two signals, even though they have a 
10:1 ratio in internal impedance. In general, the system will respond quite well. However, 
if we now remove the 33-kfl resistors from the diagram of Fig. 5.131c, the equivalent net- 
work of Fig. 5.132 results, and the following equation for is obtained using the superpo- 
sition theorem: 

(1.4 kfl || 10 kfl)v 5l (1.4 kfl || 1 kfl)v , 2 

vu = m T- m 

1 kft + 1.4 kft || 10 kft 10 kft + (1.4 kft || 1 kft) 

= 0.55v Sl + 0.055yy 2 

Using the same gain as before, we obtain the output voltage as 

v 0 = 155v^ + 15.5v i2 = 155v^ 

which indicates that the microphone will be quite loud and clear and the guitar input essen- 
tially lost. 








(b) 






(c) 



FIG. 5.131 

(a) Equivalent network with Ri, set at the midpoint and the volume controls on their maximum settings; 

(b) finding the Thevenin equivalent for channel 1; (c) substituting the Thevenin equivalent networks into Fig. 5.131a. 




FIG. 5.132 

Redrawing the network of Fig. 5.131c with the 33-kFl 
resistors removed. 



The importance of the 33-kf2 resistors is therefore defined. It makes each applied signal 
appear to have a similar impedance level so that there is good balance at the output. One 
might suggest that the larger resistor improves the balance. However, even though the bal- 
ance at the base of the transistor may be better, the strength of the signal at the base of the 
transistor will be less, and the output level reduced accordingly. In other words, the choice 
of resistors R 4 and R$ is a give-and-take situation between the input level at the base of the 
transistor and the balance of the output signal. 

To demonstrate that the capacitors are truly short-circuit equivalents in the audio range, 
substitute a very low audio frequency of 100 Hz into the reactance equation of a 56-/xF 
capacitor: 



2t TfC 2tt-( 100 Hz)(56/xF) 



28.42 12 



344 



A level of 28.42 12 compared to any of the neighboring impedances is certainly small PRACTICAL 345 

enough to be ignored. Higher frequencies will have even less effect. APPLICATIONS 

A similar mixer will be discussed in connection with the junction field effect transistor 
(JFET) in the following chapter. The major difference will be the fact that the input imped- 
ance of the JFET can be approximated by an open circuit rather than the rather low-level 
input impedance of the BJT configuration. The result will be a higher signal level at the 
input to the JFET amplifier. However, the gain of the FET is much less than that of the BJT 
transistor, resulting in output levels that are actually quite similar. 

Preamplifier 

The primary function of a preamplifier is as its name implies: an amplifier used to pick up 
the signal from its primary source and then operate on it in preparation for its passage 
into the amplifier section. Typically, a preamplifier will amplify the signal, control its vol- 
ume, perhaps change its input impedance characteristics, and if necessary determine its route 
through the stages to follow — in total, a stage of any system with a multitude of functions. 

A preamplifier such as shown in Fig. 5.133 is often used with dynamic microphones 
to bring the signal level up to levels that are suitable for further amplification or power 
amplifiers. Typically, dynamic microphones are low-impedance microphones because 
their internal resistance is determined primarily by the winding of the voice coil. The basic 
construction consists of a voice coil attached to a small diaphragm that is free to move 
within a permanent magnet. When one speaks into the microphone, the diaphragm moves 
accordingly and causes the voice coil to move in the same manner within the magnetic 
field. In accord with Faraday’s law, a voltage will be induced across the coil that will carry 
the audio signal. 




Because it is a low-impedance microphone, the input impedance of the transistor ampli- 
fier does not have to be that high to pick up most of the signal. Because the internal imped- 
ance of a dynamic microphone may be as low as 20 12 to 100 12, most of the signal would 
be picked up with an amplifier having an input impedance as low as 1 to 2 kI2. This, in 
fact, is the case for the preamplifier of Fig. 5.133. For dc biasing conditions, the collector 
dc feedback configuration was chosen because of its high stablity characteristics. 

In the ac domain, the 10 -/tF capacitor will assume a short-circuit state (on an approxi- 
mate basis), placing the 82-kI2 resistor across the input impedance of the transistor and the 
47 kI2 across the output of the transistor. A dc analysis of the transistor configuration results 
in r e = 9.64 12, giving an ac gain determined by 

(47 kI2 II 3.3 kI2) 



A v = — 



9.6412 



= - 319.7 



which is excellent for this application. Of course, the gain will drop when this pickup stage 
of the design is connected to the input of the amplifier section. That is, the input resistance 



346 BJT AC ANALYSIS 



of the next stage will appear in parallel with the 47-kft and 3. 3 -kft resistors and will drop 
the gain below the unloaded level of 319.7. 

The input impedance of the preamplifier is determined by 

Z ( = 82kft||j3r e = 82kft||(140)(9.64ft) = 82kft||l.34kft = 1.33 kil 

which is also fine for most low-impedance dynamic microphones. In fact, for a micro- 
phone with an internal impedance of 50 ft, the signal at the base would be over 98% of that 
available. This discussion is important because if the impedance of the microphone is a 
great deal more, say, 1 kft, the preamplifier would have to be designed differently to 
ensure that the input impedance was at least 10 kft or more. 

Random-Noise Generator 

There is often a need for a random-noise generator to test the response of a speaker, micro- 
phone, filter, and, in fact, any system designed to work over a wide range of frequencies. 
A random-noise generator is just as its name implies: a generator that generates sig- 
nals of random amplitude and frequency. The fact that these signals are usually totally 
unintelligible and unpredictable is the reason that they are simply referred to as noise. 
Thermal noise is noise generated due to thermal effects resulting from the interaction 
between free electrons and the vibrating ions of a material in conduction. The result is an 
uneven flow of electrons through the medium, which will result in a varying potential 
across the medium. In most cases, these randomly generated signals are in the microvolt 
range, but with sufficient amplification they can wreak havoc on a system’s response. This 
thermal noise is also called Johnson noise (named after the original researcher in the area) 
or white noise (because in optics, white light contains all frequencies). This type of noise 
has a fairly flat frequency response such as shown in Fig. 5.134a, that is, a plot of its power 
versus frequency from the very low to the very high end is fairly uniform. A second type 
of noise is called shot noise, a name derived from the fact that its noise sounds like a 
shower of lead shot hitting a solid surface or like heavy rain on a window. Its source is 
pockets of carriers passing through a medium at uneven rates. A third is pink, flicker, or 
1// noise, which is due to the variation in transit times for carriers crossing various junc- 
tions of semiconductor devices. It is called 1 //noise because its magnitude drops off with 
increase in frequency. Its effect is usually the most dramatic for frequencies below 1 
kHz, as shown in Fig. 5.134b. 




FIG. 5.134 

Typical noise frequency spectra: (a) white or Johnson; (b) pink, thermal, and shot. 

The network of Fig. 5.135 is designed to generate both a white noise and a pink noise. 
Rather than a separate source for each, first white noise is developed (level across the entire 
frequency spectrum), and then a filter is applied to remove the mid- and high-frequency 
components, leaving only the low-frequency noise response. The filter is further designed 
to modify the flat response of the white noise in the low-frequency region (to create a 1 // 
drop-off) by having sections of the filter “drop in” as the frequency increases. The white 
noise is created by leaving the collector terminal of transistor Q\ open and reverse-biasing 
the base-to-emitter junction. In essence, the transistor is being used as a diode biased in 
the Zener avalanche region. Biasing a transistor in this region creates a very unstable situ- 
ation that is conducive to the generation of random white noise. The combination of the 
avalanche region with its rapidly changing charge levels, sensitivity of the current level to 



15-30 V 




temperature, and quickly changing impedance levels contributes to the level of noise volt- 
age and current generated by the transistor. Germanium transistors are often used because 
the avalanche region is less defined and less stable than in silicon transistors. In addition, 
there are diodes and transistors designed specifically for random-noise generation. 

The source of the noise is not some specially designed generator. It is simply due to the 
fact that current flow is not an ideal phenomenon but actually varies with time at a level that 
generates unwanted variations in the terminal voltage across elements. In fact, that variation 
in flow is so broad that it can generate frequencies that extend across a wide spectrum — a 
very interesting phenomenon. 

The generated noise current of Q\ will then be the base current for Q 2 , which will be 
amplified to generate a white noise of perhaps 100 mV, which for this design would suggest 
an input noise voltage of about 170 /mV. Capacitor C\ will have a low impedance throughout 
the frequency range of interest to provide a “shorting effect” on any spurious signals in the 
air from contributing to the signal at the base of Q\. The capacitor C 2 is there to isolate the dc 
biasing of the white-noise generator from the dc levels of the filter network to follow. The 
39 kO and the input impedance of the next stage create the simple voltage-divider network 
of Fig. 5.136. If the 39 kO were not present, the parallel combination of R 2 and Z t would 
load down the first stage and reduce the gain of Q\ considerably. In the gain equation, R 2 
and Zj would appear in parallel (discussed in Chapter 9). 

Q 

R 3 

o 6 || o — 

+ 25 39 kO 

V o(Q 2 ) 




FIG. 5.136 

Input circuit for the second stage. 



The filter network is actually part of the feedback loop from collector to base appear- 
ing in the collector feedback network of Section 5.10. To describe its behavior, let us first 
consider the extremes of the frequency spectrum. For very low frequencies all the capaci- 
tors can be approximated by an open circuit, and the only resistance from collector to base 
is the 1-MO resistor. Using a beta of 100, we find that the gain of the section is about 280 
and the input impedance about 1.28 kO. At a sufficiently high frequency all the capacitors 



Pink 

-o 

Noise 



347 



348 BJT AC ANALYSIS could be replaced by short circuits, and the total resistance combination between collector 

and base would be reduced to about 14.5 kft, which would result in a very high unloaded 
gain of about 731, more than twice that just obtained with R F = 1 MCI. Because the 1 // 
filter is supposed to reduce the gain at high frequencies, it initially appears as though there 
is an error in design. However, the input impedance has dropped to about 19.33 12, which 
is a 66-fold drop from the level obtained with R F = 1 MU. This would have a significant 
impact on the input voltage appearing at the second stage when we consider the voltage- 
divider action of Fig. 5.136. In fact, when compared to the series 39-kfl resistor, the signal 
at the second stage can be assumed to be negligible or at a level where even a gain in excess 
of 700 cannot raise it to a level of any consequence. In total, therefore, the effect of dou- 
bling the gain is totally lost due to the tremendous drop in Z h and the output at very high 
frequencies can be ignored entirely. 

For the range of frequencies between the very low and the very high, the three capacitors 
of the filter will cause the gain to drop off with increase in frequency. First, capacitor C4 
will be dropped in and cause a reduction in gain (around 100 Hz). Then capacitor C5 will be 
included and will place the three branches in parallel (around 500 Hz). Finally, capacitor 
will result in four parallel branches and the minimum feedback resistance (around 6 kHz). 

The result is a network with an excellent random-noise signal for the full frequency 
spectrum (white) and the low-frequency spectrum (pink). 

Sound-Modulated Light Source 

The light from the 12-V bulb of Fig. 5.137 will vary at a frequency and an intensity that are 
sensitive to the applied signal. The applied signal may be the output of an acoustical ampli- 
fier, a musical instrument, or even a microphone. Of particular interest is the fact that the 
applied voltage is 12 V ac rather than the typical dc biasing supply. The immediate ques- 
tion, in the absence of a dc supply, is how the dc biasing levels for the transistor will be 
established. In actuality, the dc level is obtained through the use of diode D\, which recti- 
fies the ac signal, and capacitor C2, which acts as a power supply filter to generate a dc 
level across the output branch of the transistor. The peak value of a 12-V rms supply is 
about 17 V, resulting in a dc level after the capacitive filtering in the neighborhood of 16 V. 
If the potentiometer is set so that R\ is about 320 12, the voltage from base to emitter of the 
transistor will be about 0.5 V, and the transistor will be in the “off’ state. In this state the 
collector and emitter currents are essentially 0 mA, and the voltage across resistor R 3 is 
approximately 0 V. The voltage at the junction of the collector terminal and the diode is 
therefore 0 V, resulting in D 2 being in the “off’ state and 0 V at the gate terminal of the 
silicon-controlled rectifier (SCR). The SCR (see Section 17.3) is fundamentally a diode 
whose state is controlled by an applied voltage at the gate terminal. The absence of a volt- 
age at the gate means that the SCR and bulb are off. 




FIG. 5.137 

Sound-modulated light source. SCR, Silicon-controlled rectifier. 

If a signal is now applied to the gate terminal, the combination of the established bias- 
ing level and the applied signal can establish the required 0.7-V turn-on voltage, and the 
transistor will be turned on for periods of time dependent on the applied signal. When the 



SUMMARY 349 



transistor turns on, it will establish a collector current through resistor R 3 that will establish a 
voltage from collector to ground. If the voltage is more than the required 0.7 V for diode D 2 , 
a voltage will appear at the gate of the SCR that may be sufficient to turn it on and establish 
conduction from the drain to the source of the SCR. However, we must now examine one of 
the most interesting aspects of this design. Because the applied voltage across the SCR is ac, 
which will vary in magnitude with time as shown in Fig. 5.138, the conduction strength of 
the SCR will vary with time also. As shown in the figure, if the SCR is turned on when the 
sinusoidal voltage is a maximum, the resulting current through the SCR will be a maximum 
also, and the bulb will be its brightest. If the SCR should turn on when the sinusoidal voltage 
is near its minimum, the bulb may turn on, but the lower current will result in considerably 
less illumination. The result is that the lightbulb turns on in sync with when the input signal 
is peaking, but the strength of turn-on will be determined by where one is on the applied 12-V 
signal. One can imagine the interesting and varied responses of such a system. Each time one 
applies the same audio signal, the response will have a different character. 




FIG. 5.138 

Demonstrating the effect of an ac voltage on 
the operation of the SCR of Fig. 5.137. 



In the above action, the potentiometer was set below the turn-on voltage of the transis- 
tor. The potentiometer can also be adjusted so that the transistor is “just on,” resulting in a 
low-level base current. The result is a low-level collector current and insufficient voltage 
to forward-bias diode D 2 and turn on the SCR at the gate. However, when the system is 
set up in this manner, the resultant light output will be more sensitive to lower amplitude 
components of the applied signal. In the first case, the system acts more like a peak detector, 
whereas in the latter case it is sensitive to more components of the signal. 

Diode D 2 was included to be sure that there is sufficient voltage to turn on both the diode 
and the SCR, in other words, to eliminate the possibility of noise or some other low-level 
unexpected voltage on the line turning the SCR on. Capacitor C 2 can be inserted to slow 
down the response by ensuring the voltage charge across the capacitor before the gate will 
reach sufficient voltage to turn on the SCR. 

5-26 SUMMARY ^ 

Important Conclusions and Concepts 

1 . Amplification in the ac domain cannot be obtained without the application of dc 
biasing level. 

2. For most applications the BJT amplifier can be considered linear, permitting the use 
of the superposition theorem to separate the dc and ac analyses and designs. 

3. When introducing the ac model for a BJT: 

a. All dc sources are set to zero and replaced by a short-circuit connection to 
ground. 

b. All capacitors are replaced by a short-circuit equivalent. 

c. All elements in parallel with an introduced short-circuit equivalent should be 
removed from the network. 

d. The network should be redrawn as often as possible. 

4. The input impedance of an ac network cannot be measured with an ohmmeter. 



350 BJT AC ANALYSIS 



5. The output impedance of an amplifier is measured with the applied signal set to 
zero. It cannot be measured with an ohmmeter. 

6. The output impedance for the r e model can be included only if obtained from a data 
sheet or from a graphical measurement from the characteristic curves. 

7. Elements that were isolated by capacitors for the dc analysis will appear in the ac 
analysis due to the short-circuit equivalent for the capacitive elements. 

8. The amplification factor (beta, /3, or hf e ) is the least sensitive to changes in collector 
current, whereas the output impedance parameter is the most sensitive. The output 
impedance is also quite sensitive to changes in V C t t, whereas the amplification factor 
is the least sensitive. However, the output impedance is the least sensitive to 
changes in temperature, whereas the amplification factor is somewhat sensitive. 

9. The r e model for a BJT in the ac domain is sensitive to the actual dc operating con- 
ditions of the network. This parameter is normally not provided on a specification 
sheet, although h ie of the normally provided hybrid parameters is equal to (3r e , but 
only under specific operating conditions. 

10. Most specification sheets for BJTs include a list of hybrid parameters to establish 
an ac model for the transistor. One must be aware, however, that they are provided for 
a particular set of dc operating conditions. 

11. The CE fixed-bias configuration can have a significant voltage gain characteristic, 
although its input impedance can be relatively low. The approximate current gain 
is given by simply beta, and the output impedance is normally assumed to be Rq - 

12. The voltage-divider bias configuration has a higher stability than the fixed-bias 
configuration, but it has about the same voltage gain, current gain, and output 
impedance. Due to the biasing resistors, its input impedance may be lower than that 
of the fixed-bias configuration. 

13. The CE emitter-bias configuration with an unbypassed emitter resistor has a larger 
input resistance than the bypassed configuration, but it will have a much smaller 
voltage gain than the bypassed configuration. For the unbypassed or bypassed situa- 
tion, the output impedance is normally assumed to be simply R c . 

14. The emitter-follower configuration will always have an output voltage slightly less 
than the input signal. However, the input impedance can be very large, making it 
very useful for situations where a high-input first stage is needed to “pick up” as much 
of the applied signal as possible. Its output impedance is extremely low, making it 
an excellent signal source for the second stage of a multistage amplifier. 

15. The common-base configuration has a very low input impedance, but it can have a 
significant voltage gain. The current gain is just less than 1, and the output imped- 
ance is simply R c . 

16. The collector feedback configuration has an input impedance that is sensitive to 
beta and that can be quite low depending on the parameters of the configuration. 
However, the voltage gain can be significant and the current gain of some magni- 
tude if the parameters are chosen properly. The output impedance is most often 
simply the collector resistance Rq- 

17. The collector dc feedback configuration uses the dc feedback to increase its stabil- 
ity and the changing state of a capacitor from dc to ac to establish a higher voltage 
gain than obtained with a straight feedback connection. The output impedance is 
usually close to Rq and the input impedance relatively close to that obtained with the 

basic common-emitter configuration. 

18. The approximate hybrid equivalent network is very similar in composition to that 
used with the r e model. In fact, the same methods of analysis can be applied to both 
models. For the hybrid model the results will be in terms of the network parameters 
and the hybrid parameters, whereas for the r e model they will be in terms of the net- 
work parameters and /3, r e , and r 0 . 

19. The hybrid model for common-emitter, common-base, and common-collector con- 
figurations is the same. The only difference will be the magnitude of the parameters 
of the equivalent network. 

20. The total gain of a cascaded system is determined by the product of the gains of each 
stage. The gain of each stage, however, must be determined under loaded conditions. 

21. Because the total gain is the product of the individual gains of a cascaded system, the 
weakest link can have a major effect on the total gain. 



Equations 



26 mV 




Hybrid parameters: 

hie hfe /^ac’ ^ ib hfb Q: = 1 

CE fixed bias: 



A = i8r g , Z 0 = 

A v = A,- = -A,,— A = 13 

r e Rc 

Voltage-divider bias: 

Zj — ^1 11^2 ll/^g? 

Z, 

A v = --r, A f = —A v —^ = (3 

r e 

CE emitter-bias: 

Z; — Rb\\PRe> Z 0 = Rc 

A R C A 

A v = , Aj = 

Re *b + PR e 

Emitter-follower: 

Zi = Rb\(3Re, Z 0 = r e 

A v = 1 , A t = ~A V §- 

k e 



Common-base: 

Zj = ^|| 



z 0 = R c 



R< 



A v , Aj 1 



Collector feedback: 
r* 



I + Rc 

P Rf 



Rc\\Rf 



Rc 

A v = — 



A, ^ ^ 

Rc 



Collector dc feedback: 
Z ; - s R F Jj3r e , 



A„ = - 



RfJRc 



z 0 = Rc\\Rf 2 

Ai = -A v — 

Rc 



Effect of load impedance: 

_ v 0 _ r l 

VL Vi R l + R a VNV 

Effect of source impedance: 



4 . = — = 

" /, 



Zi 

— A v — 

'Ri. 



Vt = 

A = 



R,Vs 
Ri + Rs 

v* 

R s + Ri 






Ri 

Ri + R, Avnl 



Combined effect of load and source impedance: 

R l V n Ri 



A,, = — = 

v s y 



, _ ^ , 

Vi Vi R l + R a w 

A- = — = -A — A- = — = -A — ~ — 
lL h Vl Rl h Is 



R, 



s Ri + R S Rl + Ro VNL 



R, 



SUMMARY 351 



352 BJT AC ANALYSIS 



Cascode connection: 

A Vl A V2 

Darlington connection (with R E ): 

Pd — PiPh 



Zt = Rb\\(PiP 2 Re)’ 



Ai = 



Pi Pl R B 



( R B + PiP2 R e) 
1 

Darlington connection (without R E ): 



z ° p 2 + r ' 2 



A v = ^ 

v Vi 



^ill^2ll)8i(r ei + j8i j8 2 r e ) A, = 



ftfc(gi|gg) 
7?i||/? 2 + z/ 



where Z/ = (3 x (r e + for* ) 



z 0 = /? c lko 2 

Feedback pair: 

Z; — r b\\PiPi r c 



4r A v 



A = -f = 



Vi 



A/ = 



PiPi R c 

n 

~P\Pi r b 
R B + PlP2 R C 



Pi 



5.27 COMPUTER ANALYSIS 



PSpice Windows 

BJT Voltage-Divider Configuration The last few chapters have been limited to the dc anal- 
ysis of electronic networks using PSpice and Multisim. This section will consider the applica- 
tion of an ac source to a BJT network and describe how the results are obtained and interpreted. 

Most of the construction of the network of Fig. 5.139 can be accomplished using the 
procedures introduced in earlier chapters. The ac source can be found in the SOURCE 
library as VSIN. You can scroll down the list of options or simply type in YSIN at the head 
of the listing. Once this is selected and placed, a number of labels will appear that define 



O OrCAD Capture CIS - Demo Edition 



File Edit View Tools Elace Macro PSpice Accessories 
Options Window Help CSdfilKf 



SCHEMATIC1 -OiCAD 








Sfc 


x : 


-■r- 


F 


Jt- 


ji 


J 




aht 


1 


+ 


A 




i 

T 




■o 




0- 


1* 


"5 






St 








% 




$} 



FIG. 5.139 

Using PSpice Windows to analyze the network of Fig. 5.28 
( Example 5.2). 



the parameters of the source. Double-clicking the source symbol or using the sequence COMPUTER ANALYSIS 353 
Edit-Properties will result in the Property Editor dialog box, which lists all the param- 
eters appearing on the screen and more. By scrolling all the way to the left, you will find a 
listing for AC. Select the blank rectangle under the heading and enter the 1 mV value. Be 
aware that the entries can use prefixes such as m (milli) and k (kilo). Moving to the right, 
the heading FREQ will appear, in which you can enter 10 kHz. Moving again to PHASE, 
you will find the default value is 0, so it can be left alone. It represents the initial phase angle 
for the sinusoidal signal. Next you will find VAMPL, which is set at 1 mV, also followed 
by VOFF at 0 V. Now that each of the properties has been set, we have to decide what to 
display on the screen to define the source. In Fig. 5.139 the only labels are Vs and 1 mV, 
so a number of items have to be deleted and the name of the source has to be modified. For 
each quantity simply return to the heading and select it for modification. If you choose AC, 
select Display to obtain the Display Properties dialog box. Select Value Only because we 
prefer not to have the label AC appear. Leave all the other choices blank. An OK, and you 
can move to the other parameters within the Property Editor dialog box. We do not want 
the FREQ, PHASE, VAMPL and VOFF labels to appear with their values, so in each case 
select Do Not Display. To change VI to Vs, simply go to the Part Reference, and after 
selecting it, type in Vs. Then go to Display and select Value Only. Finally, to apply all the 
changes, select Apply and exit the dialog box; the source will appear as shown in Fig. 5. 139. 

The ac response for the voltage at a point in the network is obtained using the VPRINT1 
option found in the SPECIAL library. If the library does not appear, simply select Add 
Library followed by special.olb. When VPRINT1 is chosen, it will appear on the screen 
as a printer with three labels: AC, MAG, and PHASE. Each has to be set to an OK status 
to reflect the fact that you desire this type of information about the voltage level. This is 
accomplished by simply clicking on the printer symbol to obtain the dialog box and setting 
each to OK. For each entry select Display and choose Name and Label. Finally, select 
Apply and exit the dialog box. The result appears in Fig. 5.139. 

The transistor Q2N2222 can be found under the EVAL library by typing it under the 
Part heading or simply scrolling through the possibilities. The levels of I s and /3 can be 
set by first selecting the Q2N2222 transistor to make it red and then applying the sequence 
Edit-PSpice Model to obtain the PSpice Model Editor Lite dialog box and changing Is to 
2E-15A and Bf to 90. The level of Is is the result of numerous runs of the network to find 
the value that would result in V BE being closest to 0.7 V. 

Now that all the components of the network have been set, it is time to ask the computer 
to analyze the network and provide some results. If improper entries were made, the com- 
puter will quickly respond with an error listing. First select the New Simulation Profile 
key to obtain the New Simulation dialog box. Then, after entering Name as OrCAD 5-1, 
select Create and the Simulation Settings dialog box will appear. Under Analysis type, 
select AC Sweep/Noise and then under AC Sweep Type choose Linear. The Start Fre- 
quency is 10 kHz, the End Frequency is 10 kHz, and the Total Points is 1. An OK, and 
the simulation can be initiated by selecting the Run PSpice key (white arrow). A schematic 
will result with a graph that extends from 5 kHz to 15 kHz with no vertical scale. Through 
the sequence View-Output File the listing of Fig. 5.140 can be obtained. It starts with a list 
of all the elements of the network and their settings followed by all the parameters of the 
transistor. In particular, note the level of IS and BF. Next the dc levels are provided under 
the SMALL SIGNAL BIAS SOLUTION, which match those appearing on the schematic 
of Fig. 5.139. The dc levels appear on Fig. 5.139 due to the selection of the V option. Also 
note that V BE = 2.624 V - 1.924 V = 0.7 V, as stated above, due to the choice of Is. 

The next listing, OPERATING POINT INFORMATION, reveals that even though 
beta of the BJT MODEL PARAMETERS listing was set at 90, the operating conditions 
of the network resulted in a dc beta of 48.3 and an ac beta of 55. Fortunately, however, the 
voltage-divider configuration is less sensitive to changes in beta in the dc mode, and the 
dc results are excellent. However, the drop in ac beta had an effect on the resulting level 
of V 0 : 296.1 mV versus the handwritten solution (with r Q = 50 kO) of 324.3 mV — a 9% 
difference. The results are certainly close, but probably not as close as one would like. A 
closer result (within 7%) could be obtained by setting all the parameters of the device except 
I s and beta to zero. However, for the moment, the impact of the remaining parameters has 
been demonstrated, and the results will be accepted as sufficiently close to the handwritten 
levels. Later in this chapter, an ac model for the transistor will be introduced with results 



354 BJT AC ANALYSIS 



CIRCUIT DESCRIPTION 



*Analysis directives: 

.AC LIN 1 10kHz 10kHz 
.OP 

.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*)) 
.INC ".ASCHEMATICl .net" 

* source ORCAD 5-1 

Q_Q1 N00286 N00282 N003 19 Q2N2222 

R_R1 N00282 N00254 56kTC=0,0 

R_R2 0N00282 8.2kTC=0,0 

R_R3 N00286 N00254 6.8kTC=0,0 

R_R4 0N00319 1.5kTC=0,0 

V_VCC N00254 0 22Vdc 

C_C1 0N00319 20uF TC=0,0 

V_Vs N00342 0 AC lmV 

+SIN OV lmV 10kHz 0 0 0 
. PRINT AC 

+ VM ([N00286]) 

+ VP ([N00286]) 

C_C2 N00342 N00282 lOuF TC=0,0 

.END 



" * BIT MODEL PARAMETERS 



Q2N2222 

NPN 

LEVEL 1 

IS 2.000000E-15 
BF 90 
NF 1 
VAF 74.03 
IKF .2847 
ISE 14.340000E-15 
NE 1.307 
BR 6.092 
NR 1 
ISS 0 
RB 10 
RE 0 
RC 1 

CJE 22.010000E-12 
VJE .75 
MJE .377 
CJC 7.306000E-12 
VJC .75 
MJC .3416 

XCJC 1 
CJS 0 
VJS .75 
TF 411 .100000E-12 
XTF 3 
VTF 1.7 
ITF .6 
TR 46.910000E-09 
XTB 1.5 
KF 0 
AF 1 
CN 2.42 
D .87 



**** SMALL SIGNAL BIAS SOLUTION 



TEMPERATURE = 27.000 DEG C 



NODE 


VOLTAGE 


NODE 


VOLTAGE 


NODE 


VOLTAGE 


NODE 


VOLTAGE 


(N00254) 

(N00342) 


22.0000 

0.0000 


(N00282) 


2.6239 


(N00286) 


13.4530 


(N00319) 


1.9244 



VOLTAGE SOURCE CURRENTS 
NAME CURRENT 
V_VCC -1.603E-03 
V_Vs 0.000E+00 

TOTAL POWER DISSIPATION 3.53E-02 WATTS 

**** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C 



**** BIPOLAR JUNCTION TRANSISTORS 



NAME 

MODEL 

IB 

IC 

VBE 

VBC 

VCE 

BETADC 

GM 

RPI 

RX 

RO 

CBE 

CBC 

CJS 

BETAAC 

CBX/CBX2 

FT/FT2 



Q_Q1 

Q2N2222 

2.60E-05 

1.26E-03 

6.99E-01 

-1.08E+01 

1.15E+01 

4.83E+01 

4.84E-02 

1.14E+03 

1.00E+01 

6.75E+04 

5.78E-11 

2.87E-12 

0.00E+00 

5.50E+01 

0.00E+00 

1.27E+08 



**** AC ANALYSIS 



TEMPERATURE = 27.000 DEG C 



FREQ VM(N00286) VP(N00286) 
1 .000E+04 2.961E-01 -1.780E+02 



FIG. 5.140 

Output file for the network of Fig. 5.139. 



that will be an exact match with the handwritten solution. The phase angle is — 178° versus 
the ideal of — 180°, a very close match. 

A plot of the voltage at the collector of the transistor can be obtained by setting up a new 
simulation process to calculate the value of the desired voltage at a number of data points. 
The more points, the more accurate is the plot. The process is initiated by returning to the 




Simulation Settings dialog box and under Analysis type selecting Time Domain(Transient). COMPUTER ANALYSIS 355 
Time domain is chosen because the horizontal axis will be a time axis, requiring that the 
collector voltage be determined at a specified time interval to permit the plot. Because the 
period of the waveform is 1/10 kHz = 0.1 ms = 100 /as, and it would be convenient to 
display five cycles of the waveform, the Run to time(TSTOP) is set at 500 /as. The Start 
saving data after point is left at 0 s and under Transient option, the Maximum step 
size is set at 1 /as to ensure 100 data points for each cycle of the waveform. An OK, and a 
SCHEMATIC window will appear with a horizontal axis broken down in units of time 
but with no vertical axis defined. The desired waveform can then be added by first select- 
ing Trace followed by Add Trace to obtain the Add Trace dialog box. In the provided 
listing V(Ql:c) is selected as the voltage at the collector of the transistor. The instant it is 
selected it will appear as the Trace Expression at the bottom of the dialog box. Referring to 
Fig. 5.139, we find that because the capacitor C E will essentially be in the short-circuit state 
at 10 kHz, the voltage from collector to ground is the same as that across the output terminals 
of the transistor. An OK, and the simulation can be initiated by selecting the Run PSpice key. 

The result will be the waveform of Fig. 5.141 having an average value of about 13.45 V, 
which corresponds exactly with the bias level of the collector voltage in Fig. 5.139. 

The range of the vertical axis was chosen automatically by the computer. Five full 
cycles of the output voltage are displayed with 100 data points for each cycle. The data 
points appear in Fig. 5.139 because the sequence Tools-Options-Mark Data Points 
was applied. The data points appear as small dark circles on the plot curve. Using the 
scale of the graph, we see that the peak-to-peak value of the curve is approximately 
13.76 V - 13.16 V = 0.6 V = 600 mV, resulting in a peak value of 300 mV. Because a 
1-mV signal was applied, the gain is 300, or very close to the calculator solution of 296.1. 




FIG. 5.141 

Voltage v c for the network Fig. 5.139. 



If a comparison is to be made between the input and output voltages on the same screen, 
the Add Y-Axis option under Plot can be used. After you select it, choose the Add Trace 
icon and select V(Vs:+) from the provided list. The result is that both waveforms will ap- 
pear on the same screen as shown in Fig. 5.142, each with its own vertical scale. 

If two separate graphs are preferred, we can start by selecting Plot followed by Add Plot 
to Window after the graph of Fig. 5.141 is in place. The result will be a second set of axes 
waiting for a decision about which curve to plot. Using Trace- Add Trace-V(Vs:+) will 
result in the graphs of Fig. 5.143. The SEL (from SELECT) appearing next to one of 
the plots defines the “active” plot. 




356 BJT AC ANALYSIS 




FIG. 5.142 

The voltages v c and v s for the network of Fig. 5.139. 



g SCHEMATIC! OrCAD 5 1 PSpice A/D Demo [OrCAD 5 1 (active)] 



S File £dit View Simulation Jrace Plot Tfiols Window Help 



cadence' 



• SCHFMATlCl-OfCAD . 



^ H vi m a x >■, ~ ^ k. lal. iM.MM-M.MMjal.MJi 



it 

a 

a 

® 




U U(Us :♦) 



SEL» 
13 . OU 





----- 


— a — 4 — -a- — » — 




| s > — * — 


— * S* — i 




— ; — i-.-l 










' : /’■v 


x 










JL 1 ' 








tf- Y -i 


7 c \ . f yY 






























































Api... 


i— r- 




















*’ vT"! ! [ 




f ] 








r*' 





























Os 10 

o U ( Q 1 : i; ) 



200 us 300 us 

Tine 



iiOOus SOOus 



lC\ECETll ORCAD\Ofcad 5-1-PSpiceFi 



Time= 500.0E-06 100% i 



FIG. 5.143 

Two separate plots ofvc and v s in Fig. 5.139. 



The last operation to be introduced in this coverage of graph displays is the use of 
the cursor option. The result of the sequence Trace- Cursor-Display is a line at the dc 
level of the graph of Fig. 5.144 intersecting with a vertical line. The level and time both 
appear in the small dialog box in the bottom right corner of the screen. The first number 
for Cursor 1 is the time intersection and the second is the voltage level at that instant. A 
left-click of the mouse will provide control of the intersecting vertical and horizontal lines 
at this level. Clicking on the vertical line and holding down on the clicker will allow you to 
move the intersection horizontally along the curve, simultaneously displaying the time and 



COMPUTER ANALYSIS 357 



voltage level in the data box at the bottom right of the screen. If it is moved to the first peak 
of the waveform, the time appears as 75.194 jul s with a voltage level of 13.753 V, as shown 
in Fig. 5.144. On right-clicking of the mouse, a second intersection, defined by Cursor 2, 
will appear, which can be moved in the same way with its time and voltage appearing in the 
same dialog box. Note that if Cursor 2 is placed close to the negative peak, the difference 
in time is 49.61 /ms (as displayed in the same box), which is very close to one-half the period 
of the waveform. The difference in magnitude is 591 mV, which is very close to the 600 mV 
obtained earlier. 




FIG. 5.144 

Demonstrating the use of cursors to read specific points on a plot. 



Voltage-Divider Configuration-Controlled Source Substitution The results obtained 
for any analysis using the transistors provided in the PSpice listing will always be some- 
what different from those obtained with an equivalent model that only includes the effect 
of beta and r e . This was clearly demonstrated for the network of Fig. 5.139. If a solution is 
desired that is limited to the approximate model used in the hand calculations, then the 
transistor must be represented by a model such as appearing in Fig. 5.145. 






E 

FIG. 5.145 

Using a controlled source to represent the transistor of Fig. 5.139. 





358 BJT AC ANALYSIS 



For Example 5.2, /3 is 90, with f3r e = 1.66 kll. The current-controlled current source 
(CCCS) is found in the ANALOG library as part F. After selection, an OK, and the graphi- 
cal symbol for the CCCS will appear on the screen as shown in Fig. 5.146. Because it does 
not appear within the basic structure of the CCCS, it must be added in series with the 
controlling current that appears as an arrow in the symbol. Note the added 1.66-kI2 resis- 
tor, labeled beta-re in Fig. 5.146. Double-clicking on the CCCS symbol will result in the 
Property Editor dialog box, in which the GAIN can be set to 90. It is the only change to 
be made in the listing. Then select Display followed by Name and Value and exit (x) the 
dialog box. The result is the GAIN = 90 label appearing in Fig. 5.146. 




FIG. 5.146 

Substituting the controlled source of Fig. 5.145 for the transistor 
of Fig. 5.139. 



A simulation and the dc levels of Fig. 5.146 will appear. The dc levels do not match 
the earlier results because the network is a mix of dc and ac parameters. The equivalent 
model substituted in Fig. 5.146 is a representation of the transistor under ac conditions, 
not dc biasing conditions. When the software package analyzes the network from an ac 
viewpoint it will work with an ac equivalent of Fig. 5.146, which will not include the dc 
parameters. The Output File will reveal that the output collector voltage is 368.3 mV, or 
a gain of 368.3, essentially an exact match with the handwritten solution of 368.76. The 
effects of r Q could be included by simply placing a resistor in parallel with the controlled 
source. 

Darlington Configuration Although PSpice does have two Darlington pairs in the 
library, individual transistors are employed in Fig. 5.147 to test the solution to Exam- 
ple 5.17. The details of setting up the network have been covered in the preceding sec- 
tions and chapters. For each transistor I s is set to 100E-18 and [3 to 89.4. The applied 
frequency is 10 kHz. A simulation of the network results in the dc levels appearing in 
Fig. 5.147a and the Output File in Fig. 5.147b. In particular, note that the voltage drop 
between base and emitter for both transistors is 10.52 V — 9.148 V = 1.37 V com- 
pared to the 1.6 V assumed in the example. Recall that the drop across Darlington pairs 
is typically about 1.6 V and not simply twice that of a single transistor, or 
2(0.7 V) = 1.4 V. The output voltage of 99.36 mV is very close to the 99.80 mV 
obtained in Section 5.17. 





**** 


BJT MODEL PARAMETERS 














Q2N3904 

NPN 












LEVEL 


1 












IS 


100.000000E-18 












BF 


89.4 












NF 


1 












BR 


1 












NR 


I 












CN 


2.42 












D 


.87 










**** 


SMALL SIGNAL BIAS SOLUTION 


TEMPERATURE = 


27 .000 DEG C 




NODE 


VOLTAGE 


NODE VOLTAGE 


NODE 


VOLTAGE 


NODE 


VOLTAGE 


N00218) 


0.0000 


(N00225) 18.0000 


(N00243) 


8.9155 


(N00250) 


9.6513 


(N00291) 


0.0000 


(N02131) 8.0632 










**** AC ANALYSIS 


TEMPERATURE = 


27.000 DEG C 








FREQ 


VM(N00291) 










1.000E+04 


9.936E-02 











(a) 



(b) 



FIG. 5.147 

(a) Design Center schematic of Darlington network; (b) output listing for circuit of part (a) (edited). 



Multisim 

Collector Feedback Configuration Because the collector feedback configuration gen- 
erated the most complex equations for the various parameters of a B JT network, it seems 
appropriate that Multisim be used to verify the conclusions of Example 5.9. The net- 
work appears as shown in Fig. 5.148 using the “virtual” transistor from the Transistor 
family toolbar. Recall from the previous chapter that transistors are obtained by first 
selecting the Transistor keypad appearing as the fourth option over on the component 




FIG. 5.148 

Network of Example 5.9 redrawn using Multisim. 



359 






360 BJT AC ANALYSIS 



toolbar. Once chosen, the Select a Component dialog box will appear; under the Fam- 
ily heading, select TRANSISTORS_VIRTUAL followed by BJT_NPN_VIRTUAL. 
Following an OK the symbols and labels will appear as shown in Fig. 5.148. We 
must now check that the beta value is 200 to match the example under investigation. 
This can be accomplished using one of two paths. In Chapter 4 we used the EDIT- 
PROPERTIES sequence, but here we will simply double-click on the symbol to obtain 
the TRANSISTORSJVIRTUAL dialog box. Under Value, select Edit Model to obtain 
the Edit Model dialog box (the dialog box has a different appearance from that obtained 
with the other route and requires a different sequence to change its parameters). The 
value of BF appears as 100, which must be changed to 200. First select the BF line to 
make it blue all the way across. Then place the cursor directly over the 100 value and 
select it to isolate it as the quantity to be changed. After deleting the 100, type in the 
desired 200 value. Then click the BF line directly under the Name heading and the 
entire line will be blue again, but now with the 200 value. Then choose Change Part 
Model at the bottom left of the dialog box and the TRANSISTORS-VIRTUAL dialog 
box will appear again. Select OK and /3 = 200 will be set for the virtual transistor. Note 
the asterisk next to the BJT label to indicate the parameters of the device have been 
changed from the default values. The label Bf = 100 was set using Place-Text as 
described in the previous chapter. 

This will be the first opportunity to set up an ac source. First, it is important to real- 
ize that there are two types of ac sources available, one whose value is in rms units, the 
other with its peak value displayed. The option under Power Sources uses rms values, 
whereas the ac source under Signal Sources uses peak values. Because meters display 
rms values, the Power Sources option will be used here. Once Source is selected, the 
Select a Component dialog box will appear. Under the Family listing select POWER_ 
SOURCES and then select AC_POWER under the Component listing. An OK, and 
the source will appear on the screen with four pieces of information. The label VI can 
be deleted by first double-clicking on the source symbol to obtain the AC_POWER 
dialog box. Select Display and disengage Use Schematic Global Settings. To remove 
the label VI, disengage the Show RefDes option. An OK, and the VI will disappear 
from the screen. Next the value has to be set at 1 mV, a process initiated by selecting 
Value in the AC_POWER dialog box and then changing the Voltage (RMS) to 1 mV. 
The units of mV can be set using the scroll keys to the right of the magnitude of the 
source. After you change the Voltage to 1 mV, an OK will place this new value on the 
screen. The frequency of 1000 Hz can be set in the same way. The 0-degree phase shift 
happens to be the default value. 

The label Bf = 200 is set in the same way as described in Chapter 4. The two multi- 
meters are obtained using the first option at the top of the right vertical toolbar. The meter 
faces appearing in Fig. 5.148 were obtained by simply double-clicking on the multimeter 
symbols on the schematic. Both were set to read voltages, the magnitudes of which will be 
in rms units. 

After simulation the results of Fig. 5. 148 appear. Note that the meter XMM1 is not read- 
ing the 1 mV expected. This is due to the small drop in voltage across the input capacitor 
at 1 kHz. Certainly, however, it is very close to 1 mV. The output of 245.166 mV quickly 
reveals that the gain of the transistor configuration is about 245.2, which is a very close 
match with the 240 obtained in Example 5.9. 



Darlington Configuration Applying Multisim to the network of Fig. 5.147 with a pack- 
aged Darlington amplifier results in the printout of Fig. 5.149. For each transistor the 
parameters were changed to Is = 100E-18 A and Bf = 89.4 using the technique described 
earlier. For practice purposes the ac signal source was employed rather than the power 
source. The peak value of the applied signal is set at 100 mV, but note that the multimeter 
reads the effective or rms value of 99.991 mV. The indicators reveal that the base voltage 
of Q\ is 7.736 V, and the emitter voltage of Q 2 is 6.193 V. The rms value of the output 
voltage is 99.163 mV, resulting in a gain of 0.99 as expected for the emitter follower con- 
figuration. The collector current is 16 mA with a base current of 1.952 mA, resulting in a 
(3 d of about 8200. 




FIG. 5.149 

Network of Example 5.9 redrawn using Multisim. 



PROBLEMS 



*Note: Asterisks indicate more difficult problems. 



5.2 Amplification in the AC Domain 

1. a. What is the expected amplification of a BJT transistor amplifier if the dc supply is set to 

zero volts? 

b. What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on 
the waveform. 

c. What is the conversion efficiency of an amplifier in which the effective value of the current 
through a 2.2-kfl load is 5 mA and the drain on the 18-V dc supply is 3.8 mA? 

2. Can you think of an analogy that would explain the importance of the dc level on the resulting 
ac gain? 

3. If a transistor amplifier has more than one dc source, can the superposition theorem be applied 
to obtain the response of each dc source and algebraically add the results? 

5.3 BJT Transistor Modeling 

4. What is the reactance of a 10-^F capacitor at a frequency of 1 kHz? For networks in which the 
resistor levels are typically in the kilohm range, is it a good assumption to use the short-circuit 
equivalence for the conditions just described? How about at 100 kHz? 

5. Given the common-base configuration of Fig. 5.150, sketch the ac equivalent using the nota- 
tion for the transistor model appearing in Fig. 5.7. 





FIG. 5.150 

Problem 5. 



5.4 The r e Transistor Model 

6. a. Given an Early voltage of = 100 V, determine r Q if V C e q — 8 V and I c = 4 mA. 
b. Using the results of part (a), find the change in I c for a change in V C e of 6 V at the same 
g-point as part (a). 










BJT AC ANALYSIS 






7. For the common-base configuration of Fig. 5.18, an ac signal of 10 mV is applied, resulting in 
an ac emitter current of 0.5 mA. If a = 0.980, determine: 



8. Using the model of Fig. 5.16, determine the following for a common-emitter amplifier if 
f 3 = 80, I E { dc) = 2 mA, and r Q = 40 kfl. 



b. I b . 

c. Aj = I„/I, = I L /I b ifR L = 1.2 kn. 

d. A v ifR L = 1.2 kn. 

9. The input impedance to a common-emitter transistor amplifier is 1.2 kll with [3 = 140, 
r a = 50 kft, and Ri = 2.7 kli. Determine: 



b. 4 if Vi = 30 mV. 

c. 4. 

d. Aj = ijii = 4 / 4 . 

e. A v = VjVi. 

10. For the common-base configuration of Fig. 5.18, the dc emitter current is 3.2 mA and a is 0.99. 
Determine the following if the applied voltage is 48 mV and the load is 2.2 k D. 



5.5 Common-Emitter Fixed-Bias Configuration 

11. For the network of Fig. 5.151: 

a. Determine and Z 0 . 

b. FindA v . 

c. Repeat parts (a) and (b) with r Q = 20 kll. 

12. For the network of Fig. 5.152, determine V C c for a voltage gain of A v = - 160. 



*13. For the network of Fig. 5.153: 

a. Calculate I B , I c , and r e . 

b. Determine Z* and Z Q . 

c. Calculate A v . 

d. Determine the effect of r Q = 30 kD on A v . 

14. For the network of Fig. 5.153, what value of R c will cut the voltage gain to half the value 
obtained in problem 13? 



b. V 0 if R l = 1.2 k D. 

c. A v = VjVi. 

d. Z 0 with r a = °° fl. 

e. A; = I 0 /Ii. 

f. I b . 




12 V 




FIG. 5.151 
Problem 11. 



FIG. 5.152 

Problem 12. 



12 V 




FIG. 5.153 

Problem 13. 



5.6 Voltage-Divider Bias 

15 . For the network of Fig. 5. 154: 

a. Determine r e . 

b. Calculate Z t and Z Q . 

c. Find A v . 

d. Repeat parts (b) and (c) with r Q — 25 kfl. 




Problem 15. 

16 . Determine V cc for the network of Fig. 5.155 if A v = —160 and r 0 = 100 kfl. 



17 . For the network of Fig. 5.156: 

a. Determine r e . 

b. Calculate V B and V c . 

c. Determine Z t and A v = VjVi. 




FIG. 5.155 
Problem 16. 



Vcc = 20 V 





BJT AC ANALYSIS 



18 . For the network of Fig. 5.157: 

a. Determine r e . 

b. Find the dc voltages V B , V CB » and V C e • 

c. Determine Z z and Z 0 . 

d. Calculate A v = V 0 /V t . 




FIG. 5.157 
Problem 18. 



5.7 CE Emitter-Bias Configuration 

19 . For the network of Fig. 5.158: 

a. Determine r e . 

b. Find Z z and Z Q . 

c. Calculate A v . 

d. Repeat parts (b) and (c) with r 0 = 20 kfl. 

20 . Repeat Problem 19 with R E bypassed. Compare results. 

21 . For the network of Fig. 5.159, determine R E and R B if A v = — 10andr e = 3.8 D. Assume that 

Z b = P^E- 



20 Y 





FIG. 5.158 FIG. 5.159 

Problems 19 and 20. Problem 21. 

*22. For the network of Fig. 5. 160: 

a. Determine r e . 

b. Find Z z and A v . 

23. For the network of Fig. 5.161: 

a. Determine r e . 

b. Calculate V B , V CE , and V CB . 

c. Determine Z z and Z 0 . 

d. Calculate A v = V 0 /V[. 

e. Determine A t = 7 0 // z . 





o22 V 



PROBLEMS 



» 5.6 kQ 



* 330 kQ 1 | 7 « 



U °^o 



v.o- 



/3 = 80 
r„ = 40 kQ 



' 1.2 kQ 



0.47 kQ , 



FIG. 5.160 

Problem 22. 



16V 




FIG. 5.161 

Problem 23. 



5.8 Emitter-Follower Configuration 

24 . For the network of Fig. 5. 162: 

a. Determine r e and f3r e . 

b. Find Z z and Z 0 . 

c. Calculate A v . 



* 25 . For the network of Fig. 5. 163: 

a. Determine Z z and Z a . 

b. FindA v . 

c. Calculate V 0 if V z = 1 mV. 

* 26 . For the network of Fig. 5. 164: 

a. Calculate I B and I C - 

b. Determine r e . 

c. Determine Z z and Z a . 

d. FindA v . 



12 V 




16 V 




FIG. 5.162 
Problem 24. 



V C c - 20 V 




FIG. 5.164 

Problem 26. 



BJT AC ANALYSIS 



5.9 Common-Base Configuration 

27. For the common-base configuration of Fig. 5.165: 

a. Determine r e . 

b. Find Z t and Z Q . 

c. Calculate A v . 

*28. For the network of Fig. 5. 166, determine A v . 



8 V 




+6 V -10 V 




FIG. 5.165 FIG. 5.166 

Problem 27. Problem 28. 

5.1 0 Collector Feedback Configuration 

29. For the collector feedback configuration of Fig. 5. 167: 

a. Determine r e . 

b. Find Z t and Z Q . 

c. Calculate A v . 

*30. Given r e = 10 D, /3 = 200, A v = -160, and A t = 19 for the network of Fig. 5.168, deter- 
mine R c , Rf, and V C c- 

*31. For the network of Fig. 5.49: 

a. Derive the approximate equation for A v . 

b. Derive the approximate equations for Z t and Z a . 

c. Given R c = 2.2 kO, R F = 120 kO, R E = 1.2 kH, p = 90, and V cc = 10 V, calculate 
the magnitudes of A v , Z b and Z Q using the equations of parts (a) and (b). 



12 V 




FIG. 5.167 

Problem 29. 



5.1 1 Collector DC Feedback Configuration 

32. For the network of Fig. 5. 169: 

a. Determine Z t and Z a . 

b. FindA v . 



^cc 




FIG. 5.168 
Problem 30. 




PROBLEMS 



9 V 




FIG. 5.169 
Problems 32 and 33. 



33. Repeat problem 32 with the addition of an emitter resistor R E = 0.68 kfl. 

5.1 2-5.1 5 Effect of R l and R s and Two-Port Systems Approach 

*34. For the fixed-bias configuration of Fig. 5.170: 

a. Determine A Vnl , Z h and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place. 

c. Calculate the gain A Vl = V 0 /V[. 

d. Determine the current gain A ih = Ijl^ 




FIG. 5.170 

Problems 34 and 35. 



35. a. Determine the voltage gain A Vl for the network of Fig. 5. 170 for R L = 4.7 kfl, 2.2 k Pi, and 
0.5 k fl. What is the effect of decreasing levels of R L on the voltage gain? 
b. How will Z h Z 0 , and A Vnl change with decreasing values of R L 1 

*36. For the network of Fig. 5.171: 

a. Determine A Vnl , Z h and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place. 

c. Determine A v = V 0 /V[. 

d. Determine A Vs = V 0 /V s . 

e. Change R s to 1 k D and determine A v . How does A v change with the level of Rp 

f. Change R s to 1 kfl and determine A v/ How does A Vs change with the level of Rp 

g. Change R s to 1 kfl and determine A Vnl , Z b and Z Q . How do they change with the change in Rp. 

h. For the original network of Fig. 5.171 calculate A t = Ijli. 




BJT AC ANALYSIS 



12 V 



+ 









FIG. 5.171 

Problem 36. 



*37. For the network of Fig. 5. 172: 

a. Determine A Vnl , Z b and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in 
place. 

c. Determine A Vl and A v . 

d. Calculate A iv 

e. Change R L to 5.6 kD and calculate A v . What is the effect of increasing levels of R L on the 
gain? 

f. Change R s to 0.5 k D (with R L at 2.7 kD) and comment on the effect of reducing R s on 
A Vj . 

g. Change R L to 5.6 kfl and R s to 0.5 k D and determine the new levels of Z t and Z Q . How are 
the impedance parameters affected by changing levels of R L and R S 1 




FIG. 5.172 

Problem 37. 



38. For the voltage-divider configuration of Fig. 5. 1 73 : 

a. Determine A Vnl , Z b and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in 
place. 

c. Calculate the gain A vr 

d. Determine the current gain A iv 

e. Determine A vv A iv and Z Q using the r e model and compare solutions. 

39. a. Determine the voltage gain A Vl for the network of Fig. 5.173 with R L = 4.7 kft, 2.2 k fl, 

and 0.5 kd. What is the effect of decreasing levels of R L on the voltage gain? 
b. How will Z h Z OJ and A Vnl change with decreasing levels of R L 1 



16 V 



PROBLEMS 




FIG. 5.173 

Problems 38 and 39. 



40 . For the emitter- stabilized network of Fig. 5. 174: 

a. Determine A Vnl , Z z , and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a). 

c. Determine A Vl and A Vs . 

d. Change R s to 1 kD. What is the effect on A Vnl , Z z , and Z 0 ? 

e. Change R s to 1 kfl and determine A Vl and A v . What is the effect of increasing levels of R s 
on A Vl and A V 1 

f. Determine A z = Ijli. 



18 V 




FIG. 5.174 

Problem 40. 



* 41 . For the network of Fig. 5.175: 

a. Determine A Vnl , Z z , and Z Q . 

b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a). 

c. Determine A Vl and A v 

d. Change R s to 1 kfl and determine A Vl and A Vg . What is the effect of increasing levels of R s 
on the voltage gains? 

e. Change R s to 1 kfl and determine A Vnl , Z z , and Z Q . What is the effect of increasing levels of 
R s on the parameters? 

f. Change R L to 5.6 k D and determine A Vl and A Vj . What is the effect of increasing levels of 
R l on the voltage gains? Maintain R s at its original level of 0.6 kD. 

I 0 

g. Determine A z = — with R L = 2.7 k D and R s = 0.6 k D. 

I i 



BJT AC ANALYSIS 



20 V 




FIG. 5.175 

Problem 41. 



*42. For the common-base network of Fig. 5.176: 

a. Determine Z b Z Q , and A Vnl . 

b. Sketch the two-port model of Fig. 5.63 with the parameters of part (a) in place. 

c. Determine A Vl and A Vg . 

d. Determine A Vl and A Vs using the r e model and compare with the results of part (c). 

e. Change R s to 0.5 kfl and R L to 2.2 k D and calculate A Vl and A v . What is the effect of 
changing levels of R s and R L on the voltage gains? 

f. Determine Z Q if R s changed to 0.5 kfl with all other parameters as appearing in Fig. 5.176. 
How is Z Q affected by changing levels of R S 1 

g. Determine Z t if R L is reduced to 2.2 kfl. What is the effect of changing levels of R L on the 
input impedance? 

h. For the original network of Fig. 5.176 determine A t = Ijli. 



6 V -22 V 




FIG. 5.176 
Problem 42. 



5.1 6 Cascaded Systems 

*43. For the cascaded system of Fig. 5.177 with two identical stages, determine: 

a. The loaded voltage gain of each stage. 

b. The total gain of the system, A v and A v . 

c. The loaded current gain of each stage. 

d. The total current gain of the system A ih = I Q / I t . 

e. How Z t is affected by the second stage and R L . 

f. How Z Q is affected by the first stage and R s . 

g. The phase relationship between V 0 and V t . 




FIG. 5.177 

Problem 43. 



*44. For the cascaded system of Fig. 5.178, determine: 

a. The loaded voltage gain of each stage. 

b. The total gain of the system, A Vl and A v . 

c. The loaded current gain of each stage. 

d. The total current gain of the system. 

e. How Z t is affected by the second stage and R L . 

f. How Z 0 is affected by the first stage and R s . 

g. The phase relationship between V 0 and V t . 




FIG. 5.178 

Problem 44. 



45. For the B JT cascade amplifier of Fig. 5. 179, calculate the dc bias voltages and collector current 
for each stage. 

46. a. Calculate the voltage gain of each stage and the overall ac voltage gain for the BJT cascade 

amplifier circuit of Fig. 5.179. 
b. Find A ir = /„//,■. 



+15 V 




FIG. 5.179 
Problems 45 and 46. 




BJT AC ANALYSIS 



47 . For the cascode amplifier circuit of Fig. 5.180, calculate the dc bias voltages V Bl , V Bl , and V Cr 
* 48 . For the cascode amplifier circuit of Fig. 5.180, calculate the voltage gain A v and output voltage V 0 . 

49 . Calculate the ac voltage across a 10-kH load connected at the output of the circuit in Fig. 5. 180. 

+20 V 




FIG. 5.180 
Problems 47 and 49. 

5.1 7 Darlington Connection 

50 . For the Darlington network of Fig. 5.181: 

a. Determine the dc levels of V Bl , V Cl , V El , V CBl , and V CEr 

b. Find the currents I Bl , I Bl , and I Er 

c. Calculate Z t and Z Q . 

d. Determine the voltage gain A v = VJV t and current gain A t = I 0 /I im 



+16 V 




FIG. 5.181 

Problems 50 through 53. 

51. Repeat problem 50 with a load resistor of 1 .2 kfl. 

52 . Determine A v = V 0 /V s for the network of Fig. 5.181 if the source has an internal resistance of 
1.2 k 12 and the applied load is 10 k D. 

53 . A resistor R c = 470 D is added to the network of Fig. 5.181 along with a bypass capacitor 
C E = 5 /jlF across the emitter resistor. If /3 D = 4000, V BEj — 1.6 V, and r Ql = r Ql = 40 k D 
for a packaged Darlington amplifier: 

a. Find the dc levels of V Bl , V Ev and V CEr 

b. Determine Z t and Z a . 

c. Determine the voltage gain A v = VjVi if the output voltage V 0 is taken off the collector 
terminal via a coupling capacitor of 10 ^iF. 




Feedback Pair 



PROBLEMS 



54. For the feedback pair of Fig. 5. 182: 

a. Calculate the dc voltages V Bx , V Bl , V Cl , Vq 2 , V El , and V Er 

b. Determine the dc currents I Bl , I Ci ,Ib 2 Jc 2 , and I Er 

c. Calculate the impedances Z { and Z a . 

d. Find the voltage gain A v = VjVi. 

e. Determine the current gain A t = I Q /Ii. 



+16 V 




FIG. 5.182 

Problems 54 and 55. 



55. Repeat problem 54 if a 22-12 resistor is added between V El and ground. 

56. Repeat problem 54 if a load resistance of 1.2 k 12 is introduced. 



5.19 The Hybrid Equivalent Model 



57. Given I E ( dc) =1.2 mA, (3 = 120, and r Q = 40 k!2, sketch the following: 

a. Common-emitter hybrid equivalent model. 

b. Common-emitter r e equivalent model. 

c. Common-base hybrid equivalent model. 

d. Common-base r e equivalent model. 

58. Given h ie = 2.4 k!2, hf e = 100, h re = 4 X 10~ 4 , and h oe = 25 /rS, sketch the following: 

a. Common-emitter hybrid equivalent model. 

b. Common-emitter r e equivalent model. 

c. Common-base hybrid equivalent model. 

d. Common-base r e equivalent model. 

59. Redraw the common-emitter network of Fig. 5.3 for the ac response with the approximate 
hybrid equivalent model substituted between the appropriate terminals. 

60. Redraw the network of Fig. 5.183 for the ac response with the r e model inserted between the 
appropriate terminals. Include r Q . 



61. Redraw the network of Fig. 5.184 for the ac response with the r e model inserted between the 
appropriate terminals. Include r Q . 

62. Given the typical values of h ie = 1 k!2, h re = 2 X 1(T 4 , and A v = -160 for the input con- 
figuration of Fig. 5.185: 

a. Determine V 0 in terms of V*. 

b. Calculate I b in terms of V f . 

c. Calculate 1 ^ if h re V Q is ignored. 

d. Determine the percentage difference in I b using the following equation: 



m ,-rr ■ r 4(with 0 Ut h re ) ~ /,/Wlth h re ) 

% difference in I b = X 100% 

4( without h re ) 

e. Is it a valid approach to ignore the effects of h re V 0 for the typical values employed in this 
example? 




v cc 




FIG. 5.183 
Problem 60. 



V EE “ V CC 




FIG. 5.184 

Problem 61. 




o WV 

1 kft + 

f>reK % 2xl0 4 V„ 



FIG. 5.185 
Problems 62 and 64. 



63. Given the typical values of R L = 2.2 k Pi and h oe = 20 /jl S, is it a good approximation to 
ignore the effects of 1 /h oe on the total load impedance? What is the percentage difference in 
total loading on the transistor using the following equation? 

R l - R l H l/hoe) 

% difference in total load = — X 100% 

Rl 

64. Repeat Problem 62 using the average values of the parameters of Fig. 5.92 with A v = — 180. 

65. Repeat Problem 63 for R L = 3.3 k Pi and the average value of h oe in Fig. 5.92. 

5.20 Approximate Hybrid Equivalent Circuit 

66. a. Given (3 = 120, r e = 4.5 ft, and r 0 = 40kft, sketch the approximate hybrid equivalent 

circuit. 

b. Given h ie = 1 kft, h re = 2 X 10 -4 , hf e = 90, and h oe = 20 /jlS, sketch the r e model. 

67. For the network of Problem 1 1 : 

a. Determine r e . 

b. Find hf e and h ie . 

c. Find Z z and Z Q using the hybrid parameters. 

d. Calculate A v and A z using the hybrid parameters. 

e. Determine Z z and Z 0 if h oe = 50 /jlS. 

f. Determine A v and A t if h oe = 50 /jlS. 

g. Compare the solutions above with those of Problem 9. (Note: The solutions are available in 
Appendix E if Problem 1 1 was not performed.) 

68. For the network of Fig. 5.186: 

a. Determine Z z and Z 0 . 

b. Calculate A v and A t . 

c. Determine r e and compare (3r e to h ie . 



PROBLEMS 



18 V 




FIG. 5.186 
Problem 68. 










*69. For the common-base network of Fig. 5.187: 

a. Determine Z, and Z a . 

b. Calculate A v and A t . 

c. Determine a , /3 , r e , and r 0 . 



hfl, = -0.992 
ho, = 9.45 Q 
^o6 =1 b A/v 




5.21 Complete Hybrid Equivalent Model 

*70. Repeat parts (a) and (b) of Problem 68 with h re = 2 X 10 -4 and compare results. 

*71. For the network of Fig. 5.188, determine: 

a. Z. 

b. A v . 

A Z lo/lv 

d. Z 0 . 

*72. For the common-base amplifier of Fig. 5.189, determine: 

a. Z. 

b. A*, 

c. A v . 

d. Z 0 . 





BJT AC ANALYSIS 



20 V 




FIG. 5.188 

Problem 71. 

h ib = 9.45 Q 



hfl, = -0.997 
h ob = 0.5 pA/V 




FIG. 5.189 

Problem 72. 



5.22 Hybrid 77 Model 

73. a. Sketch the Giacoletto (hybrid 77) model for a common-emitter transistor if = 4 11, 
= 5 pF, C u = 1.5 pF, /z oe = 18 p,S, /3 = 120, and r e = 14. 
b. If the applied load is 1.2 kfl and the source resistance is 250 D, draw the approximate 
hybrid 77 model for the low- and mid-frequency range. 



5.23 Variations of Transistor Parameters 



For Problems 74 through 80, use Figs. 5.124 through 5.126. 

74. a. Using Fig. 5. 124, determine the magnitude of the percentage change in hf e for an I c change 
from 0.2 mA to 1 mA using the equation 

hf e ( 0.2 mA) - hf e ( 1mA) 



% change = 



hf e ( 0.2 mA) 

b. Repeat part (a) for an I c change from 1 mA to 5 mA. 

75. Repeat Problem 74 for h ie (same changes in I c ). 



X 100% 



76. a. If h oe = 20 ^tS at I c = 1 mA on Fig. 5.124, what is the approximate value of h oe at 

I c = 0.2 mA? 

b. Determine its resistive value at 0.2 mA and compare to a resistive load of 6.8 kD. Is it a 
good approximation to ignore the effects of 1 /h oe in this case? 

77. a. If h oe = 20 /jlS at I c = 1 mA of Fig. 5.124, what is the approximate value of h oe at 

I c = 10 mA? 

b. Determine its resistive value at 10 mA and compare to a resistive load of 6.8 k D. Is it a 
good approximation to ignore the effects of 1 /h oe in this case? 

78. a. If h re = 2 X 10~ 4 at I c = 1 mA on Fig. 5.124, determine the approximate value of h re at 

0.1 mA. 

b. For the value of h re determined in part (a), can h re be ignored as a good approximation if 
A v = 210? 





79. a. Based on a review of the characteristics of Fig. 5.124, which parameter changed the least 

for the full range of collector current? 

b. Which parameter changed the most? 

c. What are the maximum and minimum values of 1 /h oe l Is the approximation 1 /h oe ||/? L = R L 
more appropriate at high or low levels of collector current? 

d. In which region of current spectrum is the approximation h re V ce = 0 the most appropriate? 

80. a. Based on a review of the characteristics of Fig. 5.126, which parameter changed the most 

with increase in temperature? 

b. Which changed the least? 

c. What are the maximum and minimum values of hjP. Is the change in magnitude signifi- 
cant? Was it expected? 

d. How does r e vary with increase in temperature? Simply calculate its level at three or four 
points and compare their magnitudes. 

e. In which temperature range do the parameters change the least? 

5.24 Troubleshooting 

*81. Given the network of Fig. 5. 190: 

a. Is the network properly biased? 

b. What problem in the network construction could cause V B to be 6.22 V and obtain the given 
waveform of Fig. 5.190? 





FIG. 5.190 
Problem 81. 



5.27 Computer Analysis 

82. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.25. Display the 
input and output waveforms. 

83. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.32. Display the 
input and output waveforms. 

84. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.44. Display the 
input and output waveforms. 

85. Using Multisim, determine the voltage gain for the network of Fig. 5.28. 

86. Using Multisim, determine the voltage gain for the network of Fig. 5.39. 

87. Using PSpice Windows, determine the level of V 0 for V t = 1 mV for the network of Fig. 5.69. 
For the capacitive elements assume a frequency of 1 kHz. 

88. Repeat Problem 87 for the network of Fig. 5.71. 

89. Repeat Problem 87 for the network of Fig. 5.82. 

90. Repeat Problem 87 using Multisim. 

91. Repeat Problem 87 using Multisim. 






Field-Effect Transistors 




CHAPTER OBJECTIVES ^ 

Become familiar with the construction and operating characteristics of Junction Field 
Effect (JFET), Metal-Oxide Semiconductor FET (MOSFET), and Metal- Semiconductor 
FET (MESFET) transistors. 

Be able to sketch the transfer characteristics from the drain characteristics of a JFET, 
MOSFET, and MESFET transistor. 

Understand the vast amount of information provided on the specification sheet for each 
type of FET. 

Be aware of the differences between the dc analysis of the various types of FETs. 

6-1 INTRODUCTION ^ 

The field-effect transistor (FET) is a three-terminal device used for a variety of applications 
that match, to a large extent, those of the BJT transistor described in Chapters 3 through 5. 
Although there are important differences between the two types of devices, there are also 
many similarities, which will be pointed out in the sections to follow. 

The primary difference between the two types of transistors is the fact that: 

The BJT transistor is a current-controlled device as depicted in Fig. 6.1a , whereas the 
JFET transistor is a voltage-controlled device as shown in Fig. 6.1b. 

In other words, the current Iq in Fig. 6.1a is a direct function of the level of I B . For the FET 
the current I D will be a function of the voltage Vqs applied to the input circuit as shown in 
Fig. 6.1b. In each case the current of the output circuit is controlled by a parameter of the 
input circuit — in one case a current level and in the other an applied voltage. 

Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field- 
effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar 
device — the prefix hi indicates that the conduction level is a function of two charge carriers, 
electrons and holes. The FET is a unipolar device depending solely on either electron ( n - 
channel) or hole (p-channel) conduction. 

The term field effect in the name deserves some explanation. We are all familiar with 
the ability of a permanent magnet to draw metal filings to itself without the need for actual 
contact. The magnetic field of the permanent magnet envelopes the filings and attracts them 
to the magnet along the shortest path provided by the magnetic flux lines. For the FET an 
electric field is established by the charges present, which controls the conduction path of 
the output circuit without the need for direct contact between the controlling and controlled 
quantities. 




378 





(a) (b) 

FIG. 6.1 

(a) Current-controlled and (b) voltage-controlled amplifiers. 



There is a natural tendency when introducing a device with a range of applications 
similar to one already introduced to compare some of the general characteristics of one to 
those of the other: 

One of the most important characteristics of the FET is its high input impedance. 

At a level of 1 Mil to several hundred megohms it far exceeds the typical input resistance 
levels of the B JT transistor configurations — a very important characteristic in the design of 
linear ac amplifier systems. On the other hand, the BJT transistor has a much higher sensi- 
tivity to changes in the applied signal. In other words, the variation in output current is typi- 
cally a great deal more for BJTs than for FETs for the same change in the applied voltage. 
For this reason: 

Typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. 
However, 

FETs are more temperature stable than BJTs y and FETs are usually smaller than 
BJTs , making them particularly useful in integrated-circuit (IC) chips. 

The construction characteristics of some FETs, however, can make them more sensitive to 
handling than BJTs. 

Three types of FETs are introduced in this chapter: the junction field- effect transistor 
(JFET), the metal-oxide-semiconductor field- effect transistor (MOSFET), and the metal- 
semiconductor field-effect transistor (MESFET). The MOSFET category is further broken 
down into depletion and enhancement types, which are both described. The MOSFET 
transistor has become one of the most important devices used in the design and construc- 
tion of integrated circuits for digital computers. Its thermal stability and other general 
characteristics make it extremely popular in computer circuit design. However, as a discrete 
element in a typical top-hat container, it must be handled with care (to be discussed in a 
later section). The MESFET is a more recent development and takes full advantage of the 
high-speed characteristics of GaAs as the base semiconductor material. Although currently 
the more expensive option, the cost issue is often outweighed by the need for higher speeds 
in RF and computer designs. 

Once the FET construction and characteristics have been introduced, the biasing ar- 
rangements will be covered in Chapter 7. The analysis performed in Chapter 4 using BJT 
transistors will prove helpful in the derivation of the important equations and understanding 
the results obtained for FET circuits. 

Ian Munro Ross and G. C. Dacey (Fig. 6.2) were instrumental in the early stages of 
development of the field-effect transistor. Take particular note of the equipment used in 
1955 for their research. 



CONSTRUCTION AND 379 
CHARACTERISTICS 
OF JFETs 




Drs. Ian Munro Ross (front) and 
G. C. Dacey jointly developed an 
experimental procedure for measur- 
ing the characteristics of a field- 
effect transistor in 1955. 

Dr. Ross Bom: Southport, England; 

PhD, Gonville and Caius 
College, Cambridge Uni- 
versity; President Emeri- 
tus, AT&T Bell Labs; 
Fellow, IEEE; Member, 
the National Science 
Board; Chairman, 
National Advisory Com- 
mittee on Semiconductors 
Dr. Dacey Born: Chicago, Illinois; 

PhD, California Insti- 
tute of Technology; 
Director of Solid-State 
Electronics Research, 
Bell Labs; Vice Presi- 
dent, Research, Sandia 
Corporation; Member 
IRE, Tau Beta Pi, Eta 
Kappa Nu 

FIG. 6.2 

Early development of the field- effect 
transistor. 

(Courtesy of AT&T Archives and 
History Center.) 



6.2 CONSTRUCTION AND CHARACTERISTICS OF JFETs 



As indicated earlier, the JFET is a three-terminal device with one terminal capable of con- 
trolling the current between the other two. In our discussion of the BJT transistor the npn 
transistor was employed through the major part of the analysis and design sections, with a 




380 FIELD-EFFECT 
TRANSISTORS 



Source 




Drain 

FIG. 6.4 



Water analogy for the JFET control 
mechanism. 



section devoted to the effect of using a pnp transistor. For the JFET transistor the zz-channel 
device will be the prominent device, with paragraphs and sections devoted to the effect of 
using a ^-channel JFET. 

The basic construction of the n - channel JFET is shown in Fig. 6.3. Note that the major 
part of the structure is the zz-type material, which forms the channel between the embed- 
ded layers of p - type material. The top of the zz-type channel is connected through an ohmic 
contact to a terminal referred to as the drain (D), whereas the lower end of the same material 
is connected through an ohmic contact to a terminal referred to as the source (S). The two 
p - type materials are connected together and to the gate (G) terminal. In essence, therefore, 
the drain and the source are connected to the ends of the zz-type channel and the gate to the 
two layers of p - type material. In the absence of any applied potentials the JFET has two 
p-n junctions under no-bias conditions. The result is a depletion region at each junction, 
as shown in Fig. 6.3, that resembles the same region of a diode under no-bias conditions. 
Recall also that a depletion region is void of free carriers and is therefore unable to support 
conduction. 



o Drain ( D ) 



Ohmic 

contacts 



^-channel 



Gate (G ) 



y " Et 



Depletion 

region 



Depletion 

region 



o Source (S ) 

FIG. 6.3 

Junction field-effect transistor (JFET). 



Analogies are seldom perfect and at times can be misleading, but the water analogy of 
Fig. 6.4 does provide a sense for the JFET control at the gate terminal and the appropriate- 
ness of the terminology applied to the terminals of the device. The source of water pressure 
can be likened to the applied voltage from drain to source, which establishes a flow of 
water (electrons) from the spigot (source). The “gate,” through an applied signal (potential), 
controls the flow of water (charge) to the “drain.” The drain and source terminals are at 
opposite ends of the zz-channel as introduced in Fig. 6.3 because the terminology is defined 
for electron flow. 

V C s = 0 V, V DS Some Positive Value 

In Fig. 6.5, a positive voltage V DS is applied across the channel and the gate is connected 
directly to the source to establish the condition V GS = 0 V. The result is a gate and a source 
terminal at the same potential and a depletion region in the low end of each /^-material 
similar to the distribution of the no-bias conditions of Fig. 6.3. The instant the voltage 
V DD ( = Vds ) i s applied, the electrons are drawn to the drain terminal, establishing the con- 
ventional current I D with the defined direction of Fig. 6.5. The path of charge flow clearly 
reveals that the drain and source currents are equivalent (I D = I s ). Under the conditions in 
Fig. 6.5, the flow of charge is relatively uninhibited and is limited solely by the resistance 
of the zz- channel between drain and source. 

It is important to note that the depletion region is wider near the top of both p - type 
materials. The reason for the change in width of the region is best described through the 
help of Fig. 6.6. Assuming a uniform resistance in the zz- channel, we can break down 




CONSTRUCTION AND 381 
CHARACTERISTICS 
OF JFETs 




FIG. 6.5 

JFETat V GS = 0 Vand V DS > 0 V. 




Varying reverse-bias potentials across 
the p-n junction of an n-channel JFET. 



the resistance of the channel into the divisions appearing in Fig. 6.6. The current 
will establish the voltage levels through the channel as indicated on the same figure. 
The result is that the upper region of the /7-type material will be reverse-biased by about 
1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the discussion of 
the diode operation that the greater the applied reverse bias, the wider is the depletion 
region — hence the distribution of the depletion region as shown in Fig. 6.6. The fact that 
the p-n junction is reverse-biased for the length of the channel results in a gate current 
of zero amperes, as shown in the same figure. The fact that I G = 0 A is an important 
characteristic of the JFET. 

As the voltage V DS is increased from 0 V to a few volts, the current will increase as 
determined by Ohm’s law and the plot of I D versus V DS will appear as shown in Fig. 6.7. 
The relative straightness of the plot reveals that for the region of low values of V DS , the 
resistance is essentially constant. As V DS increases and approaches a level referred to as 
V P in Fig. 6.7, the depletion regions of Fig. 6.5 will widen, causing a noticeable reduction 
in the channel width. The reduced path of conduction causes the resistance to increase and 
the curve in the graph of Fig. 6.7 to occur. The more horizontal the curve, the higher the 
resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal 
region. If V DS is increased to a level where it appears that the two depletion regions would 




FIG. 6.7 

I D versus V DS for V GS = 0V. 





382 FIELD-EFFECT “touch” as shown in Fig. 6.8, a condition referred to as pinch- off will result. The level of 

TRANSISTORS y DS establishes this condition is referred to as the pinch-off voltage and is denoted by 

V P , as shown in Fig. 6.7. In actuality, the term pinch-off is a misnomer in that it suggests 
the current I D is pinched off and drops to 0 A. As shown in Fig. 6.7, however, this is hardly 
the case — Id maintains a saturation level defined as I DSS in Fig. 6.7. In reality a very small 
channel still exists, with a current of very high density. The fact that I D does not drop off at 
pinch-off and maintains the saturation level indicated in Fig. 6.7 is verified by the follow- 
ing fact: The absence of a drain current would remove the possibility of different potential 
levels through the n-channel material to establish the varying levels of reverse bias along 
the p-n junction. The result would be a loss of the depletion region distribution that caused 
pinch-off in the first place. 



G 

o- 

+ 



V G S - 0 V 



<?D 



+ 







?s 



FIG. 6.8 

Pinch-off (V GS = 0V, V DS = V P ). 




o 



Load 



-o 



FIG. 6.9 

Current source equivalent for 
V G s = 0V, V ds >V p . 



As V[)s is increased beyond V P , the region of close encounter between the two depletion 
regions increases in length along the channel, but the level of I D remains essentially the 
same. In essence, therefore, once V DS > V P the JFET has the characteristics of a current 
source. As shown in Fig. 6.9, the current is fixed at I D = I DSS , but the voltage V D s (for 
levels > V P ) is determined by the applied load. 

The choice of notation I DSS is derived from the fact that it is the drain-to-source current 
with a short-circuit connection from gate to source. As we continue to investigate the char- 
acteristics of the device we will find that: 

I D ss * s the maximum drain current for a JFET and is defined by the conditions 
V GS = 0 V and V DS > \V P \. 

Note in Fig. 6.7 that V GS = 0 V for the entire length of the curve. The next few paragraphs 
will describe how the characteristics of Fig. 6.7 are affected by changes in the level of V GS . 



v cs <ov 

The voltage from gate to source, denoted V GS , is the controlling voltage of the JFET. Just 
as various curves for I c versus V G e were established for different levels of I B for the BJT 
transistor, curves of I D versus V DS for various levels of V G $ can be developed for the JFET. 
For the n-channel device the controlling voltage V GS is made more and more negative from 
its V GS = 0 V level. In other words, the gate terminal will be set at lower and lower poten- 
tial levels as compared to the source. 






CONSTRUCTION AND 383 
CHARACTERISTICS 
OF JFETs 



FIG. 6.10 

Application of a negative voltage to the gate of a JFET. 



In Fig. 6.10 a negative voltage of — 1 V is applied between the gate and source terminals 
for a low level of V DS . The effect of the applied negative-bias V GS is to establish depletion 
regions similar to those obtained with V G $ = 0 V, but at lower levels of V D g. Therefore, the 
result of applying a negative bias to the gate is to reach the saturation level at a lower level 
of V DS , as shown in Fig. 6. 1 1 for V GS = -IV. The resulting saturation level for I D has been 
reduced and in fact will continue to decrease as V GS is made more and more negative. Note 
also in Fig. 6.11 how the pinch-off voltage continues to drop in a parabolic manner as V GS 
becomes more and more negative. Eventually, V GS when V G $ = —Vp will be sufficiently 
negative to establish a saturation level that is essentially 0 mA, and for all practical purposes 
the device has been “turned off.” In summary: 

The level of V GS that results in I D = 0 mA is defined by V GS = Vp, with V P being a 
negative voltage for n-channel devices and a positive voltage for p-channel JFETs. 




FIG. 6.11 

n-Channel JFET characteristics with Ipss = 8 mA and Vp = —4 V. 




384 FI ELD- EFFECT On most specification sheets the pinch-off voltage is specified as V G $( 0 ff) rather than V P . 

TRANSISTORS A specification sheet will be reviewed later in the chapter when the majority of the control- 

ling elements have been introduced. The region to the right of the pinch-off locus of Fig. 
6. 1 1 is the region typically employed in linear amplifiers (amplifiers with minimum distor- 
tion of the applied signal) and is commonly referred to as the constant-current, saturation, 
or linear amplification region. 

Voltage-Controlled Resistor 

The region to the left of the pinch-off locus of Fig. 6.11 is referred to as the ohmic or 
voltage-controlled resistance region. In this region the JFET can actually be employed as 
a variable resistor (possibly for an automatic gain control system) whose resistance is con- 
trolled by the applied gate-to- source voltage. Note in Fig. 6.1 1 that the slope of each curve 
and therefore the resistance of the device between drain and source for V DS < Vp are a 
function of the applied voltage Vq $ . As V GS becomes more and more negative, the slope of 
each curve becomes more and more horizontal, corresponding to an increasing resistance 
level. The following equation provides a good first approximation to the resistance level in 
terms of the applied voltage V GS : 



= r ° 

(1 - V GS /Vp) 2 



where r Q is the resistance with V GS = 0 V and r d is the resistance at a particular level of V GS . 

For an ^-channel JFET with r 0 = 10 kfl ( V GS = 0 V, V P = — 6 V), Eq. (6.1) results in 
40 kn at V G s = -3 V. 

^-Channel Devices 

The p-channel JFET is constructed in exactly the same manner as the ^-channel device of 
Fig. 6.3 but with a reversal of the p- and n- type materials as shown in Fig. 6.12. The 
defined current directions are reversed, as are the actual polarities for the voltages V G $ and 
V DS . For the /^-channel device, the channel will be constricted by increasing positive volt- 
ages from gate to source and the double- subscript notation for V DS will result in negative 
voltages for V DS on the characteristics of Fig. 6.13, which has an I DSS of 6 mA and a pinch- 
off voltage of V G s = +6 V. Do not let the minus signs for V DS confuse you. They simply 
indicate that the source is at a higher potential than the drain. 




FIG. 6.12 

p- Channel JFET. 




I D (mA) 



CONSTRUCTION AND 385 
CHARACTERISTICS 
OF JFETs 




FIG. 6.13 

p-Channel JFET characteristics with I DSS = 6 mA and V P = +6 V. 

Note at high levels of V D $ that the curves suddenly rise to levels that seem unbounded. 
The vertical rise is an indication that breakdown has occurred and the current through the 
channel (in the same direction as normally encountered) is now limited solely by the exter- 
nal circuit. Although not appearing in Fig. 6.1 1 for the ^-channel device, they do occur for 
the ^-channel device if sufficient voltage is applied. This region can be avoided if the level 
of V DSmax is noted on the specification sheet and the design is such that the actual level of 
V D s is less than this value for all values of V GS . 

Symbols 

The graphic symbols for the n - channel and /7-channel JFETs are provided in Fig. 6.14. Note 
that the arrow is pointing in for the n - channel device of Fig. 6.14a to represent the direction 
in which I G would flow if the p—n junction were forward-biased. For the /7-channel device 
(Fig. 6.14b) the only difference in the symbol is the direction of the arrow in the symbol. 

D D 



9 9 




— 6 — 6 

S S 

(a) (b) 



FIG. 6.14 

JFET symbols: (a) n-channel; (b) p-channel. 



Summary 

A number of important parameters and relationships were introduced in this section. A few 
that will surface frequently in the analysis to follow in this chapter and the next for n - channel 
JFETs include the following: 

The maximum current is defined as I D ss and occurs when V GS = 0 V and V DS > \Vp\, 
as shown in Fig. 6.15a. 

For gate -to -source voltages V G $ is less than (more negative than ) the pinch-off level, 
the drain current is 0 A (I D = 0 A), as in Fig. 6.15b . 

For all levels of V G $ between 0 V and the pinch-off level, the current I D will range 
between I D $s and 0 A, respectively, as in Fig. 6.15c. 

A similar list can be developed for p-channel JFETs. 



386 FIELD-EFFECT 
TRANSISTORS 




(a) 




(b) 




(c) 

FIG. 6.15 

(a) V GS = 0 V,I d = I dss ; ( b) cutoff (I D = 0 A) V GS less than the pinch- off level; (c) I D is between 0 A and 
1 Dssf° r Vgs — OV and greater than the pinch- off level 




William Bradford Shockley (191 0— 
1989), co-inventor of the first 
transistor and formulator of the 
“field-effect” theory employed in 
the development of the transistor 
and the FET. 

Shockley Bom: London, England; 
PhD, Harvard, 1936; 
Head, Transistor Physics 
Department, Bell 
Laboratories; President, 
Shockley Transistor 
Corp.; Poniatoff Professor 
of Engineering Science, 
Stanford University; 
Nobel Prize in physics in 
1956 with Walter Brattain 
and John Bardeen 

FIG. 6.16 

Dr. William Bradford Shockley. 
(Courtesy of AT&T Archives and 
History Center.) 



6-5 TRANSFER CHARACTERISTICS ^ 

Derivation 

For the BJT transistor the output current Iq and the input controlling current I B are 
related by beta, which was considered constant for the analysis to be performed. In equa- 
tion form, 

control variable 



Ic=Nb) = P h 

f 

constant 

In Eq. (6.2) a linear relationship exists between I c and I B . Double the level of I B and I c will 
increase by a factor of two also. 

Unfortunately, this linear relationship does not exist between the output and input quan- 
tities of a JFET. The relationship between Id and Vqs is defined by Shockley ’s equation 
(see Fig. 6.16): 

control variable 



( 6 . 3 ) 



constants 

The squared term in the equation results in a nonlinear relationship between I D and Vqs , 
producing a curve that grows exponentially with decreasing magnitude of Vqs. 

For the dc analysis to be performed in Chapter 7, a graphical rather than a mathematical 
approach will in general be more direct and easier to apply. The graphical approach, how- 
ever, will require a plot of Eq. (6.3) to represent the device and a plot of the network equa- 
tion relating the same variables. The solution is defined by the point of intersection of the 
two curves. It is important to keep in mind when applying the graphical approach that the 
device characteristics will be unaffected by the network in which the device is employed. 




( 6 . 2 ) 




The network equation may change along with the intersection between the two curves, but TRAN S FE R 387 

the transfer curve defined by Eq. (6.3) is unaffected. In general, therefore: CHARACTERISTICS 

The transfer characteristics defined by Shockley’s equation are unaffected by 
the network in which the device is employed. 

The transfer curve can be obtained using Shockley’s equation or from the output char- 
acteristics of Fig. 6.11. In Fig. 6.17 two graphs are provided, with the vertical scaling in 
milliamperes for each graph. One is a plot of I D versus Vps , whereas the other is I D versus 
Vgs- Using the drain characteristics on the right of the “y” axis, we can draw a horizontal 
line from the saturation region of the curve denoted Vqs = 0 V to the I D axis. The resulting 
current level for both graphs is loss- The point of intersection on the I D versus Vqs curve 
will be as shown since the vertical axis is defined as Vgs = 0 V. 




FIG. 6.17 

Obtaining the transfer curve from the drain characteristics. 



In review: 



When V GS — 0 V, I D — I DSS 



( 6 . 4 ) 



When V G s — V P = —■ 4 V, the drain current is 0 mA, defining another point on the 
transfer curve. That is: 



When = V P , I D = OmA 



( 6 . 5 ) 



Before continuing, it is important to realize that the drain characteristics relate one output 
(or drain) quantity to another output (or drain) quantity — both axes are defined by variables 
in the same region of the device characteristics. The transfer characteristics are a plot of 
an output (or drain) current versus an input-controlling quantity. There is therefore a direct 
“transfer” from input to output variables when employing the curve to the left of Fig. 6. 17. If 
the relationship were linear, the plot of I D versus V G s would result in a straight line between 
I D ss an d V P . However, a parabolic curve will result because the vertical spacing between 
steps of V G s on the drain characteristics of Fig. 6.17 decreases noticeably as Vqs becomes 
more and more negative. Compare the spacing between Vqs = 0 V and V G s — — 1 V to 
that between V G s — — 3 V and pinch-off. The change in V G s is the same, but the resulting 
change in I D is quite different. 

If a horizontal line is drawn from the Vqs — — 1 V curve to the I D axis and then extended 
to the other axis, another point on the transfer curve can be located. Note that V G s — -IV 
on the bottom axis of the transfer curve with I D = 4.5 mA. Note in the definition of I D at 
Vgs = 0 V and —IV that the saturation levels of I D are employed and the ohmic region 
ignored. Continuing with V G s — — 2 V and —3 V, we can complete the transfer curve. It is 



the transfer curve of I D versus V GS that will receive extended use in the analysis of Chapter 
7 and not the drain characteristics of Fig. 6.17. The next few paragraphs will introduce a 
quick, efficient method of plotting I D versus V GS given only the levels of I DSS and V P and 
Shockley’s equation. 

Applying Shockley's Equation 

The transfer curve of Fig. 6.17 can also be obtained directly from Shockley’s equation (6.3) 
given simply the values of I DSS and V P . The levels of I DSS and V P define the limits of the 
curve on both axes and leave only the necessity of finding a few intermediate plot points. 
The validity of Eq. (6.3) as a source of the transfer curve of Fig. 6.17 is best demonstrated 
by examining a few specific levels of one variable and finding the resulting level of the 
other as follows: 

Substituting V G $ = 0 V gives 

Eq. (6.3): I D = / DSS (l - 

= hiss I - = Idss( 1 - 0) 2 

and 



388 FIELD-EFFECT 
TRANSISTORS 



Id ~ bss I v GS =ow 



( 6 . 6 ) 



Substituting V GS = V P yields 



L D 



loss 

= Idss( 1 



1_V, 

V P 



l) 2 = « 0) 



I D - 0A| v GS =v P 



( 6 . 7 ) 



For the drain characteristics of Fig. 6.17, if we substitute V G $ = -IV, 




= 8mA^l =8inA^l8jJ =8mA(0.75) 2 

= 8 mA (0.5625) 

= 4.5 mA 

as shown in Fig. 6.17. Note the care taken with the negative signs for V GS and V P in the 
calculations above. The loss of one sign would result in a totally erroneous result. 

It should be obvious from the above that given I DSS and V P (as is normally provided on 
specification sheets), the level of I D can be found for any level of V GS . Conversely, by using 
basic algebra we can obtain [from Eq. (6.3)] an equation for the resulting level of V GS for a 
given level of I D . The derivation is quite straightforward and results in 



V GS = M 1 - 




( 6 . 8 ) 



Let us test Eq. (6.8) by finding the level of V G s that will result in a drain current of 4.5 mA 
for the device with the characteristics of Fig. 6.17. We find 

4.5 mA 



Vgs = “4 V 1 - 



8 mA 



= —4 V(1 - VO. 5625) = —4 V(1 - 0.75) 
= -4 V(0.25) 

= -IV 



as substituted in the above calculation and verified by Fig. 6.17. 



Shorthand Method transfer 389 

CHARACTERISTICS 

Since the transfer curve must be plotted so frequently, it would be quite advantageous to 
have a shorthand method for plotting the curve in the quickest, most efficient manner while 
maintaining an acceptable degree of accuracy. The format of Eq. (6.3) is such that specific 
levels of Vqs will result in levels of I D that can be memorized to provide the plot points 
needed to sketch the transfer curve. If we specify Vqs to be one-half the pinch-off value V P , 
the resulting level of I D will be the following, as determined by Shockley’s equation: 

Id = Idss( 1 - ^rf) 

= w ( ' ~^ /2 ) 2 = w ( 1 - = W 0 - 5) 2 

— bssb-25) 



and 



InSS i 

b = — I V GS = Vp/2 



( 6 . 9 ) 



Now it is important to realize that Eq. (6.9) is not for a particular level of Vp. It is a general 
equation for any level of V P as long as Vqs = V P /2. The result specifies that the drain cur- 
rent will always be one-fourth the saturation level I D $s as long as the gate-to- source voltage 
is one-half the pinch-off value. Note the level of I D for V GS = V P /2 = -4 V/2 = -2 V 
in Fig. 6.17. 

If we choose b = loss / 2 and substitute into Eq. (6.8), we find that 



and 





( 6 . 10 ) 



Additional points can be determined, but the transfer curve can be sketched to a satisfactory 
level of accuracy simply using the four plot points defined above and reviewed in Table 6.1. In 
fact, in the analysis of Chapter 7, a maximum of four plot points are used to sketch the transfer 
curves. On most occasions using just the plot point defined by V GS = V P /2 and the axis 
intersections at I D ss and V P will provide a curve accurate enough for most calculations. 



TABLE 6.1 

Vqs versus I D Using Shockley’s 
Equation 



V GS 


Id 


0 


bss 


0.3Vp 


bss / 2 


0.5Vp 


bss / 4 


Vp 


0 mA 



EXAMPLE 6.1 Sketch the transfer curve defined by I P ss — 12 mA and V P = —6 V. 
Solution: Two plot points are defined by 

bss — 12 mA and Vqs — 0 V 
and I D = 0 mA and Vqs — V P 

At Vqs = y P /2 = ~6 V/2 = — 3 V the drain current is determined by I D = loss/ 4 — 
12mA/4 = 3 mA. At I D = loss/ 2 — 12mA/2 = 6 mA the gate-to-source voltage is 
determined by V GS = 0.3 Vp = 0.3(— 6 V) = — 1.8 V. All four plot points are well defined 
on Fig. 6.18 with the complete transfer curve. 



390 FIELD-EFFECT 
TRANSISTORS 



/ D (mA) 




= 12 mA 



For /^-channel devices Shockley’s equation (6.3) can still be applied exactly as it appears. 
In this case, both V P and Vqs will be positive and the curve will be the mirror image of the 
transfer curve obtained with an ^-channel and the same limiting values. 



EXAMPLE 6.2 Sketch the transfer curve for a p-channel device with I DSS = 4 mA and 
V P = 3 V. 

Solution: At V GiS = V P /2 = 3 V/2 = 1.5V,/ D = I DSS / 4 = 4mA/4 = 1mA. At 
Id = bss / 2 = 4 mA/2 = 2 mA, V GS = 03V P = 0.3(3 V) = 0.9 V. Both plot points 
appear in Fig. 6.19 along with the points defined by I DS s and V P . 



I D (mA) 




FIG. 6.19 

Transfer curve for the p-channel device of Example 6.2. 



6-4 SPECIFICATION SHEETS (JFETs) ^ 

As with any electronic device it is important to be able to understand the data provided on 
a specification sheet. Often times the notation used is different than we normally apply so a 
measure of translation may have to be applied. In general, however, the headings for the data 
are uniform and include Maximum Ratings, Thermal Characteristics, Electrical Charac- 
teristics, and sets of Typical Characteristics. In Fig. 6.20 the specification sheets for a 
Fairchild Semiconductor 2N5457 ^-channel JFET appears with two types of packaging tech- 
niques. The TO-92 package is for a higher power device than the surface mount SOT-23 unit. 



FAIRCHILD 



SPECIFICATION SHEETS 391 
(JFETs) 



ABSOLUTE MAXIMUM RATINGS 



Symbol 


Parameter 


Value 


Units 


^DS 


Drain-Source Voltage 


25 


V 


v DG 


Drain-Gate Voltage 


25 


V 


v GS 


Gate-Source Voltage 


-25 


V 


Igf 


Forward Gate Current 


10 


mA 


T T 

J’ stg 


Operating and Storage Junction 
Temperature Range 


-55 to +150 


°C 



SEMICONDUCTOR tm 



2N5457 MMBF5457 




NOTE: Source & Drain 
are interchangeable 



N- Channel General Purpose Amplifier 

This device is a low-level audio amplifier and 
switching transistor, and can be used for 
analog switching applications. 



THERMAL CHARACTERISTICS 



Symbol 


Characteristic 


Max 


Units 


2N5457 


*MMBF5457 




Total Device Dissipation 


625 


350 


mW 


r D 


Derate above 25 °C 


5.0 


2.8 


mW/°C 


R ejc 


Thermal Resistance, Junction to Case 


125 




°C/W 


R 6JA 


Thermal Resistance, Junction to Ambient 


357 


556 


°C/W 



ELECTRICAL CHARACTERISTICS T A = 25°C unless otherwise noted 



Symbol 


Parameter 


Test Conditions 


Min 


Typ 


Max 


Units 



OFF CHARACTERISTICS 



V (BR)GSS 


Gate-Source Breakdown Voltage 


I G - 10 pA, V DS - 0 


-25 






V 


^GSS 


Gate Reverse Current 


V GS = -15 V, V DS = 0 

V GS = -15 V, V DS = 0, T a = 100°C 






-1.0 

-200 


nA 

nA 


^GS(off) 


Gate-Source Cutoff Voltage 


V DS = 15 V,I D = lOnA 5457 


-0.5 




-6.0 


V 


V GS 


Gate-Source Voltage 


V DS = 15V,I d = 100 |xA 5457 




-2.5 




V 



ON CHARACTERISTICS 



^dss 


Zero- Gate Voltage Drain Current 


V DS = 15 V, V GS = 0 5457 


1.0 


3.0 


5.0 


mA 


SMALL SIGNAL CHARACTERISTICS 


§fs 


Forward Transfer Conductance 


V DS = 15 V, V GS = 0, f = 1 .0 kHz 5457 


1000 




5000 


mhos 


g 0 S 


Output Conductance 


V DS = 15 V, V GS = 0, f = 1.0 MHz 




10 


50 


jumhos 


Ciss 


Input Capacitance 


V DS = 15 V, V GS = 0, f = 1.0 MHz 




4.5 


7.0 


pF 


C r SS 


Reverse Transfer Capacitance 


V DS = 15 V, V GS = 0, f = 1.0 MHz 




1.5 


3.0 


pF 


NF 


Noise Figure 


V DS = 15 V, V GS = 0, f = 1.0 kHz, 
R G = 1.0 megohm, B W = 1 .0 Hz 






3.0 


dB 



(a) 



Common drain-source 




(b) 



Power dissipation vs. ambient temperature 




FIG. 6.20 

n-channel 2N5457 JFET Characteristic k. 






392 FIELD-EFFECT 
TRANSISTORS 



10 



Capacitance vs. voltage 



Channel resistance vs. temperature 




V G s - Gate-source voltage (V) 
(d) 




-75 -25 25 75 125 175 

T A - Ambient temperature (°C) 

(e) 



Transconductance vs. drain current 




0.01 0.1 1 10 



I D - Drain current (mA) 



Output conductance vs. drain current 




ffi 



(g) 



FIG. 6.20 

Continued 



Maximum Ratings 

The maximum rating list usually appears at the beginning of the specification sheet, with 
the maximum voltages between specific terminals, maximum current levels, and the maxi- 
mum power dissipation level of the device. The specified maximum levels for V DS , V DG 
and V GS must not be exceeded at any point in the design operation of the device. Any good 
design will try to avoid these levels by a good margin of safety. Although normally 
designed to operate with I G = 0 mA, if forced to accept a gate current, it could withstand 
10 mA (I G f) before damage would occur. 



Thermal Characteristics 

The total device dissipation at 25 °C (room temperature) is the maximum power the device 
can dissipate under normal operating conditions and is defined by 



Pd ~ Vds^d 



( 6 . 11 ) 



Note the similarity in format with the maximum power dissipation equation for the BJT 
transistor. 

The derating factor is discussed in detail in Chapter 3, but for the moment recognize that 
the 5 mW/°C rating reveals that the dissipation rating decreases by 5 mW for each increase 
in temperature of 1°C above 25°C. 



Electrical Characteristics 



SPECIFICATION SHEETS 393 
(JFETs) 



The electrical characteristics include the level of V P in the “off’ characteristics and I D gs in 
the “on” characteristics. In this case V P = Vgs( off) has a range from —0.5 V to —6.0 V and 
loss from 1 mA to 5 mA. The fact that both will vary from device to device with the same 
nameplate identification must be considered in the design process. The small- signal char- 
acteristics will become important when we examine ac networks in Chapter 8. 



Typical Characteristics 

The Typical Characteristics listing will include a variety of curves demonstrating how 
important parameters vary with voltage, current, temperature, and frequency. 

First note in Fig. 6.20a that the plot includes the negative region of Vqs on the normally 
positive side of the horizontal axis. Notice also that the plot is for a pinch-off voltage of 
—2.6 V, which is about halfway between the range of possible pinch-off voltages. If this 
is the only plot provided it acts like an average value between limits. The Common-Drain 
characteristics are provided in Fig. 6.20b for a pinch-off voltage of —1.8 V. Note how the 
drain current drops to 0 ampere when this pinch-off voltage is applied. Also note that the 
Idss l eve l is only about 3.75 mA for this pinch-off voltage, whereas it was about 9.5 mA for 
a pinch-off of —2.6 V in Fig. 6.20a. The Power Dissipation versus Ambient temperature is 
plotted in Fig. 6.20c, clearly showing the dramatic drop in power handling capability with 
temperature. At the boiling point of water (100°C) it is only 250 mW compared with 650 mW 
at room temperature. Capacitive effects in Fig. 6.20d will become very important at high 
frequencies because of the resulting reactance and the effect on speed of operation. It is 
interesting to note that the more negative the gate-to-source voltage, the less the capacitive 
effects at a frequency of 1 MHz. The Channel Resistance plot of Fig. 6.20e demonstrates 
how the channel resistance changes with temperature at various levels of Vgs(OFF)- At first 
glance the change may not appear that dramatic, but take note of the fact that the vertical 
axis is a log scale extending from 10 12 to 1 kll. The plots of Transconductance (Fig. 6.20f) 
and Output Conductance (Fig. 6.20g) will become important when we consider JFET ac net- 
works. They define the two parameters of the ac equivalent circuit. Each is certainly affected 
by the level of drain current with lesser sensitivity to the pinch-off voltage. 



Operating Region 

The specification sheet and the curve defined by the pinch-off levels at each level of Vqs 
define the region of operation for linear amplification on the drain characteristics as shown 
in Fig. 6.21. The ohmic region defines the minimum permissible values of Vpg at each 
level of Vgs> and Vi)s nvdx specifies the maximum value for this parameter. The saturation 




FIG. 6.21 

Normal operating region for linear amplifier design. 



394 FIELD-EFFECT 
TRANSISTORS 



current I D ss is the maximum drain current, and the maximum power dissipation level 
defines the curve drawn in the same manner as described for BJT transistors. The resulting 
shaded region is the normal operating region for amplifier design. 



6-5 INSTRUMENTATION ^ 

Recall from Chapter 3 that hand-held instruments are available to measure the level of /3^ c 
for the BJT transistor. Similar instrumentation is not available to measure the levels of I D ss 
and Vp. However, the curve tracer introduced for the BJT transistor can also display the 
drain characteristics of the JFET transistor through a proper setting of the various controls. 
The vertical scale (in milliamperes) and the horizontal scale (in volts) have been set to 
provide a full display of the characteristics, as shown in Fig. 6.22. For the JFET of Fig. 
6.22, each vertical division (in centimeters) reflects a 1-mA change in Id, whereas each 
horizontal division has a value of 1 V. The step voltage is 500 mV/step (0.5 V/step), 
revealing that the top curve is defined by Vqs = 0 V and the next curve down is —0.5 V for 
the ^-channel device. Using the same step voltage, we see the next curve is —1 V, then 
—1.5 V, and finally —2 V. By drawing a line from the top curve over to the I D axis, we can 
estimate the level of I D ss to be about 9 mA. The level of Vp can be estimated by noting the 
Vqs value of the bottom curve and taking into account the shrinking distance between 
curves as Vqs becomes more and more negative. In this case, V P is certainly more negative 
than —2 V, and perhaps V P is close to —2.5 V. However, keep in mind that the Vqs curves 
contract very quickly as they approach the cutoff condition, and perhaps Vp = — 3 V is a 
better choice. It should also be noted that the step control is set for a five-step display, 
limiting the displayed curves to Vqs — 0, —0.5, —1, —1.5, and —2 V. If the step control 
had been increased to 10, the voltage per step could be reduced to 250 mV = 0.25 V and 
the curve for Vqs = —2.25 V would have been included as well as an additional curve 
between each step of Fig. 6.22. The Vqs — —2.25 V curve would reveal how quickly the 
curves are closing in on each other for the same step voltage. Fortunately, the level of Vp 
can be estimated to a reasonable degree of accuracy simply by applying a condition appearing 




FIG. 6.22 

Drain characteristics for a 2N4416 JFET transistor as displayed on a curve tracer. 



IMPORTANT 395 
RELATIONSHIPS 



in Table 6.1. That is, when Id = loss/ 2, then V GS = 0.3Vp. For the characteristics of 
Fig. 6.22, I D = I D ss / 2 = 9 mA/2 = 4.5 mA, and, as visible from Fig. 6.22, the corre- 
sponding level of Vqs is about —0.9 V. Using this information, we find that 
V P = Vqs/ 0.3 = -0.9 V/0.3 = -3 V, which will be our choice for this device. Using 
this value, we find that at Vqs — — 2 V, 



Id 



— Idss 




2 



= 9mA 



1 



—2 V 
-3 V 



2 



= 1mA 



as supported by Fig. 6.22. 

At Vqs = -2.5 V, Shockley’s equation results in I D = 0.25 mA, with V P = -3 V, 
clearly revealing how quickly the curves contract near V P . The importance of the parameter 
g m and how it is determined from the characteristics of Fig. 6.22 are described in Chapter 8 
when small- signal ac conditions are examined. 



6-6 IMPORTANT RELATIONSHIPS ^ 

A number of important equations and operating characteristics for the JFET have been 
introduced that are of particular importance for the analysis of dc and ac configurations 
that will follow. To isolate and emphasize their importance, they are repeated in Table 6.2 
next to corresponding equations for the B JT transistor. The JFET equations are defined for 
the configuration of Fig. 6.23a, whereas the BJT equations relate to Fig. 6.23b. 

TABLE 6.2 




( 6 . 12 ) 



JFET 

D 



BJT 

C 



I r = 0A 



Go- 



\ lD 

Id = Idss ( 1- ~0 

\ IS 

S 

(a) 









B O 1 I c - ftI B 

\ IE 



+ 

V BE = 0J\ 



(b) 



FIG. 6.23 

(a) JFET versus (b) BJT. 

A clear understanding of the effect of each of the equations above is sufficient back- 
ground to approach the most complex of dc configurations. Recall that V BE = 0.7 V was 
often the key to initiating an analysis of a BJT configuration. Similarly, the condition 
Iq = 0 A is often the starting point for the analysis of a JFET configuration. For the BJT 
configuration, I B is normally the first parameter to be determined. For the JFET, it is nor- 
mally Vqs . The number of similarities between the analysis of BJT and JFET dc configura- 
tions will become quite apparent in Chapter 7. 





396 FIELD-EFFECT 
TRANSISTORS 



6.7 DEPLETION-TYPE MOSFET 



As noted in the introduction, there are three types of FETs: JFETs, MOSFETs, and MESFETs. 
MOSFETs are further broken down into depletion type and enhancement type. The terms 
depletion and enhancement define their basic mode of operation; the name MOSFET stands 
for raetal-tfxide-semiconductor/ield- effect /ransistor. Since there are differences in the 
characteristics and operation of different types of MOSFET, they are covered in separate 
sections. In this section we examine the depletion-type MOSFET, which has characteristics 
similar to those of a JFET between cutoff and saturation at I D $s , and also has the added 
feature of characteristics that extend into the region of opposite polarity for Vqs- 

Basic Construction 

The basic construction of the ^-channel depletion-type MOSFET is provided in Fig. 6.24. 
A slab of /7-type material is formed from a silicon base and is referred to as the substrate. 
It is the foundation on which the device is constructed. In some cases the substrate is inter- 
nally connected to the source terminal. However, many discrete devices provide an addi- 
tional terminal labeled SS, resulting in a four-terminal device, such as that in Fig. 6.24. The 
source and drain terminals are connected through metallic contacts to n - doped regions 
linked by an ^-channel as shown in the figure. The gate is also connected to a metal contact 
surface but remains insulated from the n - channel by a very thin silicon dioxide (SiC^) 
layer. SiC >2 is a type of insulator referred to as a dielectric , which sets up opposing (as 
indicated by the prefix di~) electric fields within the dielectric when exposed to an exter- 
nally applied field. The fact that the SiC >2 layer is an insulating layer means that: 

There is no direct electrical connection between the gate terminal and the channel of 
a MOSFET 



(Drain) 




FIG. 6.24 

n-Channel depletion-type MOSFET. 



In addition: 

It is the insulating layer of SiO 2 in the MOSFET construction that accounts for the 
very desirable high input impedance of the device. 

In fact, the input resistance of a MOSFET is usually more than that of a typical JFET, 
even though the input impedance of most JFETs is sufficiently high for most applications. 
Because of the very high input impedance, the gate current I G is essentially 0 A for dc- 
biased configurations. 

The reason for the label metal-oxide-semiconductor FET is now fairly obvious: metal 
for the drain, source, and gate connections; oxide for the silicon dioxide insulating layer; and 




semiconductor for the basic structure on which the n- and p - type regions are diffused. The DEPLETION -TYPE 397 

insulating layer between the gate and the channel has resulted in another name for the device : M 0 S F ET 

insulated- gate FET , or IGFET , although this label is used less and less in the literature. 

Basic Operation and Characteristics 

In Fig. 6.25 the gate-to- source voltage is set to 0 V by the direct connection from one ter- 
minal to the other, and a voltage V DD is applied across the drain-to- source terminals. The 
result is an attraction of the free electrons of the ^-channel for the positive voltage at the 
drain. The result is a current similar to that flowing in the channel of the JFET. In fact, the 
resulting current with Vqs = 0 V continues to be labeled I DSS , as shown in Fig. 6.26. 



fe=ov 




FIG. 6.25 

n- Channel depletion-type MOSFET with V GS = 0V and applied voltage V DD • 




Drain and transfer characteristics for an n-channel depletion-type MOSFET. 



In Fig. 6.27, V GS is set at a negative voltage such as —1 V. The negative potential at the gate 
will tend to pressure electrons toward the p-type substrate (like charges repel) and attract holes 
from the /7-type substrate (opposite charges attract) as shown in Fig. 6.27. Depending on the 




398 FIELD-EFFECT 
TRANSISTORS 



^-channel 



G o 




Metal 

contact 



Recombination 

process 



/^-material 

substrate 



Holes attracted 
to negative 
potential at gate 



Electrons repelled 
by negative 
potential at gate 



FIG. 6.27 

Reduction in free carriers in a channel due to a 
negative potential at the gate terminal. 



magnitude of the negative bias established by V GS , a level of recombination between electrons 
and holes will occur that will reduce the number of free electrons in the ^-channel available for 
conduction. The more negative the bias, the higher is the rate of recombination. The resulting 
level of drain current is therefore reduced with increasing negative bias for V GS , as shown in 
Fig. 6.26 for V GS = — 1 V, —2 V, and so on, to the pinch-off level of —6 V. The resulting levels 
of drain current and the plotting of the transfer curve proceed exactly as described for the JFET. 

For positive values of V G $, the positive gate will draw additional electrons (free carri- 
ers) from the /7-type substrate due to the reverse leakage current and establish new carriers 
through the collisions resulting between accelerating particles. As the gate-to-source volt- 
age continues to increase in the positive direction, Fig. 6.26 reveals that the drain current 
will increase at a rapid rate for the reasons listed above. The vertical spacing between the 
V G s — 0 V and V G $ = +1 V curves of Fig. 6.26 is a clear indication of how much the cur- 
rent has increased for the 1-V change in V GS . Due to the rapid rise, the user must be aware 
of the maximum drain current rating since it could be exceeded with a positive gate voltage. 
That is, for the device of Fig. 6.26, the application of a voltage V GS = +4 V would result 
in a drain current of 22.2 mA, which could possibly exceed the maximum rating (current or 
power) for the device. As revealed above, the application of a positive gate-to-source volt- 
age has “enhanced” the level of free carriers in the channel compared to that encountered 
with Vqs = 0 V. For this reason the region of positive gate voltages on the drain or transfer 
characteristics is often referred to as the enhancement region , with the region between 
cutoff and the saturation level of I DSS referred to as the depletion region. 

It is particularly interesting and helpful that Shockley’s equation will continue to be ap- 
plicable for the depletion-type MOSFET characteristics in both the depletion and enhance- 
ment regions. For both regions, it is simply necessary that the proper sign be included with 
V GS in the equation and the sign be carefully monitored in the mathematical operations. 



EXAMPLE 6.3 Sketch the transfer characteristics for an ^-channel depletion-type MOSFET 
with I DSS = 10 mA and V P = -4 V. 

Solution: 

At V G s — 0 V, I D — I dss = 10 111 A 

y GS = y p = — 4 V, I D = 0mA 

Vp —4 V Idss 10 mA 

Vos = f = — = ~ 2 V, b = ^ = 



4 



= 2.5 mA 



DEPLETION-TYPE 399 
MOSFET 



A . T I DSS 
and at I D = — , 

V GS = 0.3 V P = 0.3(— 4 V) = -1.2V 
all of which appear in Fig. 6.28. 




Transfer characteristics for an n-channel depletion-type 
MOSFET with I D ss = 10 mA and V P = —4 V. 



Before plotting the positive region of V GS , keep in mind that I D increases very rapidly 
with increasing positive values of Vqs . In other words, be conservative with the choice of 
values to be substituted into Shockley’s equation. In this case, we try + 1 V as follows: 



1 “ T7 



= (10 mA) 1 - 



+ 1 V 
-4 V 



= (10 mA) (1 + 0.25) 2 = (10 mA) (1.5625) 



= 15.63 mA 

which is sufficiently high to finish the plot. 



p-Channel Depletion-Type MOSFET 

The construction of a /7-channel depletion-type MOSFET is exactly the reverse of that 
appearing in Fig. 6.24. That is, there is now an n-type substrate and a /7-type channel, as 
shown in Fig. 6.29a. The terminals remain as identified, but all the voltage polarities and 
the current directions are reversed, as shown in the same figure. The drain characteristics 
would appear exactly as in Fig. 6.26, but with V D s having negative values, I D having posi- 
tive values as indicated (since the defined direction is now reversed), and Vqs having the 
opposite polarities as shown in Fig. 6.29c. The reversal in Vqs will result in a mirror image 
(about the I D axis) for the transfer characteristics as shown in Fig. 6.29b. In other words, 



C] o— 1 I 1 o Co 




FIG. 6.29 

p-Channel depletion- type MOSFET with I^ss = 6 m A and Vp = +6 V. 



the drain current will increase from cutoff at Vqs = Vp in the positive Vqs region to I D ss 
and then continue to increase for increasingly negative values of Vqs- Shockley’s equation 
is still applicable and requires simply placing the correct sign for both V GS and Vp in the 
equation. 

Symbols, Specification Sheets, and Case Construction 

The graphic symbols for an n- and /^-channel depletion-type MOSFET are provided in Fig. 
6.30. Note how the symbols chosen try to reflect the actual construction of the device. The 
lack of a direct connection (due to the gate insulation) between the gate and the channel is 
represented by a space between the gate and the other terminals of the symbol. The vertical 
line representing the channel is connected between the drain and the source and is “sup- 
ported” by the substrate. Two symbols are provided for each type of channel to reflect the 
fact that in some cases the substrate is externally available, whereas in others it is not. For 
most of the analysis to follow in Chapter 7, the substrate and the source will be connected 
and the lower symbols will be employed. 



n-channel 




^-channel 




e>S 




(a) (b) 

FIG. 6.30 

Graphic symbols for: (a) n-channel depletion-type 
MOSFETs and (b) p-channel depletion-type 
MOSFETs. 



400 




The device appearing in Fig. 6.31 has three terminals, with the terminal identification DEPLETION-TYPE 401 

appearing in the same figure. The specification sheet for a depletion-type MOSFET is simi- MOS FET 

lar to that of a JFET. The levels of V P and I DSS are provided along with a list of maximum 
values and typical “on” and “off’ characteristics. In addition, however, since I D can extend 
beyond the I DSS level, another point is normally provided that reflects a typical value of I D 
for some positive voltage (for an ^-channel device). For the unit of Fig. 6.31, I D is specified 
as //)( on ) = 9 mA dc, with V DS = 10 V and V GS = 3.5 V. 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Drain-Source Voltage 

2N3797 


v DS 


20 


Vdc 


Gate-Source Voltage 


v GS 


±10 


Vdc 


Drain Current 




20 


mAdc 


Total Device Dissipation @ T A = 25°C 
Derate above 25 °C 


Pd 


200 

1.14 


mW 

mW/'C 


Junction Temperature Range 


Tj 


+ 175 


°C 


Storage Channel Temperature Range 


Tt g 


-65 to +200 


°c 




ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted) 



Characteristic 


Symbol 


Min 


Typ 


Max 


Unit 


OFF CHARACTERISTICS 


Drain Source Breakdown Voltage 

(V GS = -7.0 V, I D = 5.0 //A) 2N3797 


V(BR)DSX 


20 


25 


- 


Vdc 


Gate Reverse Current ( 1 ) 

(V GS = -10V,V DS =0) 

(V GS =-10V,V DS = 0, T a = 150°C) 


^ss 


- 


- 


1.0 

200 


pAdc 


Gate Source Cutoff Voltage 

(I D = 2.0 M, V DS = 10 V) 2N3797 


V OS(off) 


- 


-5.0 


-7.0 


Vdc 


Drain-Gate Reverse Current (1) 
(V DG =10V t I s = 0) 


1 DGO 


_ 


— 


1.0 


pAdc 



ON CHARACTERISTICS 



Zero-Gate-Voltage Drain Current 




!dss 








mAdc 


(V DS = 10V, V GS = 0) 


2N3797 




2.0 


2.9 


6.0 




On-State Drain Current 




iD(on) 








mAdc 


(V DS = 10V, V GS = +3.5 V) 


2N3797 




9.0 


14 


18 





SMALL-SIGNAL CHARACTERISTICS 



Forward Transfer Admittance 

(V DS = 10 V, V GS =0,f = 1.0 kHz) 


2N3797 


lYfsl 


1500 


2300 


3000 


^tmhos 


(V DS = 10 V, V GS = 0, f = 1.0 MHz) 


2N3797 




1500 




_ 




Output Admittance 

(I DS = 10V,V GS =0,f=1.0 kHz) 


2N3797 


Dost 




27 


60 


jtmhos 


Input Capacitance 

(V DS - 10V,V GS =0,f= 1.0 MHz) 


2N3797 


c, ss 


_ 


6.0 


8.0 


pF 


Reverse Transfer Capacitance 

(V DS = 10 V, V GS = 0,f = 1.0 MHz) 


c„ s 




0.5 


0.8 


pF 



FUNCTIONAL CHARACTERISTICS 



Noise Figure 


NF 


- 


3.8 


- 


dB 


( v ds = 10 V, V GS = 0, f = 1.0 kHz, R s = 3 megohms) 













(1) This value of current includes both the FET leakage current as well as the leakage current associated with the test socket and fixture 



when measured under best attainable conditions. 



FIG. 6.31 

2N3797 Motorola n-channel depletion-type MOSFET. 





402 FIELD-EFFECT 
TRANSISTORS 



6.8 ENHANCEMENT-TYPE MOSFET 



Although there are some similarities in construction and mode of operation between depletion- 
type and enhancement- type MOSFETs, the characteristics of the enhancement- type 
MOSFET are quite different from anything obtained thus far. The transfer curve is not 
defined by Shockley’s equation, and the drain current is now cut off until the gate-to- 
source voltage reaches a specific magnitude. In particular, current control in an ^-channel 
device is now effected by a positive gate-to- source voltage rather than the range of nega- 
tive voltages encountered for n - channel JFETs and ^-channel depletion- type MOSFETs. 

Basic Construction 

The basic construction of the n - channel enhancement-type MOSFET is provided in Fig. 6.32. 
A slab of p-type material is formed from a silicon base and is again referred to as the 
substrate. As with the depletion-type MOSFET, the substrate is sometimes internally con- 
nected to the source terminal, whereas in other cases a fourth lead (labeled SS) is made 
available for external control of its potential level. The source and drain terminals are again 
connected through metallic contacts to zz-doped regions, but note in Fig. 6.32 the absence of 
a channel between the two zz-doped regions. This is the primary difference between the 
construction of depletion-type and enhancement- type MOSFETs — the absence of a channel 
as a constructed component of the device. The Si02 layer is still present to isolate the gate 
metallic platform from the region between the drain and source, but now it is simply sepa- 
rated from a section of the p - type material. In summary, therefore, the construction of an 
enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except 
for the absence of a channel between the drain and source terminals. 



Si0 2 



n -doped 
region 




«-doped 

region 



no-channel 



Substrate 



OSS 



FIG. 6.32 

n- Channel enhancement-type MOSFET. 



Basic Operation and Characteristics 

If V GS is set at 0 V and a voltage applied between the drain and the source of the device of 
Fig. 6.32, the absence of an zz-channel (with its generous number of free carriers) will result 
in a current of effectively 0 A — quite different from the depletion-type MOSFET and JFET, 
where I D = I DSS . It is not sufficient to have a large accumulation of carriers (electrons) at 
the drain and the source (due to the n - doped regions) if a path fails to exist between the two. 
With V DS some positive voltage, V GS at 0 V, and terminal SS directly connected to the 
source, there are in fact two reverse-biased p-n junctions between the n - doped regions and 
the p- substrate to oppose any significant flow between drain and source. 

In Fig. 6.33, both V DS and V GS have been set at some positive voltage greater than 
0 V, establishing the drain and the gate at a positive potential with respect to the source. 



Electrons attracted to positive gate ENHANCEME N T-T Y P E 403 

(induced n-channel) M 0 S FET 




FIG. 6.33 

Channel formation in the n-channel enhancement-type 
MOSFET. 



The positive potential at the gate will pressure the holes (since like charges repel) in the 
/7-substrate along the edge of the Si0 2 layer to leave the area and enter deeper regions of 
the /7-substrate, as shown in the figure. The result is a depletion region near the Si0 2 insu- 
lating layer void of holes. However, the electrons in the /7-substrate (the minority carriers 
of the material) will be attracted to the positive gate and accumulate in the region near 
the surface of the Si0 2 layer. The Si0 2 layer and its insulating qualities will prevent the 
negative carriers from being absorbed at the gate terminal. As Vqs increases in magnitude, 
the concentration of electrons near the Si0 2 surface increases until eventually the induced 
7z-type region can support a measurable flow between drain and source. The level of V GS 
that results in the significant increase in drain current is called the threshold voltage and is 
given the symbol V T . On specification sheets it is referred to as VGS(Th> although V T is less 
unwieldy and will be used in the analysis to follow. Since the channel is nonexistent with 
Vqs = 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type 
of MOSFET is called an enhancement-type MOSFET. Both depletion- and enhancement- 
type MOSFETs have enhancement-type regions, but the label was applied to the latter since 
it is its only mode of operation. 

As V GS is increased beyond the threshold level, the density of free carriers in the induced 
channel will increase, resulting in an increased level of drain current. However, if we hold 
Vqs constant and increase the level of V DS , the drain current will eventually reach a satura- 
tion level as occurred for the JFET and depletion-type MOSFET. The leveling off of b 
is due to a pinching-off process depicted by the narrower channel at the drain end of the 
induced channel as shown in Fig. 6.34. Applying Kirchhoff s voltage law to the terminal 
voltages of the MOSFET of Fig. 6.34, we find that 



V dg — V DS Vqs 



( 6 . 13 ) 



If Vqs is held fixed at some value such as 8 V and V DS is increased from 2 V to 5 V, the 
voltage V DG [by Eq. (6.13)] will increase from —6 V to —3 V and the gate will become less 
and less positive with respect to the drain. This reduction in gate-to-drain voltage will in 
turn reduce the attractive forces for free carriers (electrons) in this region of the induced 
channel, causing a reduction in the effective channel width. Eventually, the channel will be 
reduced to the point of pinch-off and a saturation condition will be established as described 




FIG. 6.34 

Change in channel and depletion region with increasing 
level ofVpsfor a fixed value o/Vqs. 



earlier for the JFET and depletion-type MOSFET. In other words, any further increase 
in Vps at the fixed value of Vos will n °t affect the saturation level of I D until breakdown 
conditions are encountered. 

The drain characteristics of Fig. 6.35 reveal that for the device of Fig. 6.34 with 
Vgs — 8 V, saturation occurs at a level of Vg>s = 6 V. In fact, the saturation level for Vpg 
is related to the level of applied Vqs by 



Vds s&{ ~ Vgs ~ V T 



( 6 . 14 ) 



Obviously, therefore, for a fixed value of V T , the higher the level of Vqs, the greater is the 
saturation level for Vp>s , as shown in Fig. 6.34 by the locus of saturation levels. 




FIG. 6.35 

Drain characteristics of an n-channel enhancement-type MOSFET with 
V T = 2 V and k = 0.278 X 10~ 3 A/V 2 . 



For the characteristics of Fig. 6.34, the level of V T is 2 V, as revealed by the fact that the 
drain current has dropped to 0 mA. In general, therefore: 

For values ofV G $ less than the threshold level , the drain current of an enhancement- 
type MOSFET is 0 mA. 

Figure 6.35 clearly reveals that as the level of V GS increases from V T to 8 V, the resulting 
saturation level for I D also increases from a level of 0 mA to 10 mA. In addition, it is quite 
noticeable that the spacing between the levels of V GS increases as the magnitude of V GS 
increases, resulting in ever-increasing increments in drain current. 

For levels of V G $ > V T , the drain current is related to the applied gate-to- source voltage 
by the following nonlinear relationship: 



Id = k(V GS ~ V T f 



( 6 . 15 ) 



Again, it is the squared term that results in the nonlinear (curved) relationship between I D and 
Vqs- The k term is a constant that is a function of the construction of the device. The value 
of k can be determined from the following equation [derived from Eq. (6.15)], where Id (on) 
and Vgs(oii) are the values for each at a particular point on the characteristics of the device. 



(on) 

(V G5 (on) - V T ) 2 



( 6 . 16 ) 



ENHANCEMENT-TYPE 405 
MOSFET 



Substituting Id (on) = It) mA when Vgs (on) — 8 V from the characteristics of Fig. 6.35 
yields 



_ 10 mA _ 10mA _ 10mA 

_ (8 V - 2 V) 2 (6 V) 2 36 V 2 

= 0.278 X 10“ 3 A/ V 2 

and a general equation for I D for the characteristics of Fig. 6.35 results in 

l D = 0.278 X 10“ 3 (V G5 - 2 V) 2 



Substituting V G s = 4 V, we find that 

I D = 0.278 X 10“ 3 (4 V - 2 V) 2 = 0.278 X 10“ 3 (2) 2 
= 0.278 X 10" 3 (4) = 1.11 mA 



as verified by Fig. 6.35. At V G s = Vp, the squared term is 0, and I D — 0 mA. 

For the dc analysis of enhancement-type MOSFETs to appear in Chapter 7, the transfer 
characteristics will again be the characteristics to be employed in the graphical solution. In 
Fig. 6.36, the drain and transfer characteristics have been set side by side to describe the 




FIG. 6.36 

Sketching the transfer characteristics for an n-channel enhancement-type MOSFET from the drain characteristics. 



406 FI ELD- EFFECT transfer process from one to the other. Essentially, it proceeds as introduced earlier for the 

TRAN S I STO RS JFET and depletion-type MOSFETs. In this case, however, it must be remembered that the 

drain current is 0 mA for V GS < V T . As V GS is increased beyond V T , the drain current b 
will begin to flow at an increasing rate in accordance with Eq. (6.15). Note that in defining 
the points on the transfer characteristics from the drain characteristics, only the saturation 
levels are employed, thereby limiting the region of operation to levels of V D g greater than 
the saturation levels as defined by Eq. (6.14). 

The transfer curve of Fig. 6.36 is certainly quite different from those obtained earlier. 
For an ^-channel (induced) device, it is now totally in the positive V GS region and does not 
rise until V GS = V T . The question now surfaces as to how to plot the transfer characteristics 
given the levels of k and V T as included below for a particular MOSFET : 

I D = 0.5 X 10- 3 (V G5 - 4 V) 2 

First, a horizontal line is drawn at Id = 0 mA from V GS = 0 V to V GS = 4 V as shown 
in Fig. 6.37a. Next, a level of V G $ greater than V T such as 5 V is chosen and substituted into 
Eq. (6.15) to determine the resulting level of I D as follows: 

I D = 0.5 X 1(T 3 (V G5 - 4 V) 2 

= 0.5 X 10 -3 (5 V - 4 V) 2 = 0.5 X 10“ 3 (1) 2 

= 0.5 mA 

and a point on the plot is obtained as shown in Fig. 6.37b. Finally, additional levels of V GS 
are chosen and the resulting levels of I D obtained. In particular, at V GS = 6,1, and 8 V, the 
level of Ij) is 2, 4.5, and 8 mA, respectively, as shown on the resulting plot of Fig. 6.37c. 





FIG. 6.37 

Plotting the transfer characteristics of an n-channel enhancement-type MOSFET with k = 0.5 X 10~ 3 A/ V 2 and V T = 4 V. 



p-Channel Enhancement-Type MOSFETs 

The construction of a /^-channel enhancement-type MOSFET is exactly the reverse of that 
appearing in Fig. 6.32, as shown in Fig. 6.38a. That is, there is now an rc-type substrate and 
p - doped regions under the drain and source connections. The terminals remain as identi- 
fied, but all the voltage polarities and the current directions are reversed. The drain charac- 
teristics will appear as shown in Fig. 6.38c, with increasing levels of current resulting from 
increasingly negative values of V GS . The transfer characteristics of Fig. 6.38b will be the 
mirror image (about the I D axis) of the transfer curve of Fig. 6.36, with I D increasing with 
increasingly negative values of V G $ beyond V T , as shown in Fig. 6.38c. Equations (6.13) 
through (6.16) are equally applicable to /^-channel devices. 

Symbols, Specification Sheets, and Case Construction 

The graphic symbols for the n- and ^-channel enhancement- type MOSFETs are pro- 
vided as Fig. 6.39. Again note how the symbols try to reflect the actual construction of 





FIG. 6.38 

p-Channel enhancement-type MOSFET with V T = 2 V and k = 0.5 X 10~ 3 A/V 2 . 



^-channel /^-channel 






(a) 



(b) 



FIG. 6.39 

Symbols for: (a) n-channel enhancement-type 
MOSFETs and (b) p-channel enhancement- 
type MOSFETs. 



the device. The dashed line between drain and source is chosen to reflect the fact that 
a channel does not exist between the two under no-bias conditions. It is, in fact, the 
only difference between the symbols for the depletion-type and enhancement-type 
MOSFETs. 

The specification sheet for a Motorola ^-channel enhancement-type MOSFET is pro- 
vided as Fig. 6.40. The case construction and the terminal identification are provided next 
to the maximum ratings, which now include a maximum drain current of 30 mA dc. The 
specification sheet provides the level of Ipss under “off’ conditions, which is now simply 
10 nA dc (at Vps — 10 V and Vqs = 0 V), compared to the milliampere range for the JFET 
and the depletion-type MOSFET. The threshold voltage is specified as VgsctIi) an( l has a 
range of 1 to 5 V dc, depending on the device employed. Rather than provide a range of k 
in Eq. (6.15), a typical level of Id (on) 0 mA in this case) is specified at a particular level of 
Vgs( on) (10 V for the specified Ip level). In other words, when Vqs = 10 V, Id = 3 mA. 
The given levels of VGS(Th> Id( on> and ^GSCon) permit a determination of k from Eq. (6.16) 
and a writing of the general equation for the transfer characteristics. The handling require- 
ments of MOSFETs are reviewed in Section 6.9. 



407 



MAXIMUM RATINGS 



Rating 


Symbol 


Value 


Unit 


Drain-Source Voltage 


V DS 


25 


Vdc 


Drain-Gate Voltage 


^DG 


30 


Vdc 


Gate-Source Voltage* 


V C.S 


30 


Vdc 


Drain Current 


U 


30 


mAdc 


Total Device Dissipation @ T A = 25°C 


Pd 


300 


mW 


Derate above 25 °C 




1.7 


mW/“C 


Junction Temperature Range 


t j 


175 


°C 


Storage Temperature Range 


U, g 


-65 to +175 


°C 



* Transient potentials of ± 75 Volt will not cause gate-oxide failure. 




ELECTRICAL CHARACTERISTICS (T A = 25 B C unless otherwise noted.) 



Characteristic 


Symbol 


Min 


Max 


Unit 


OFF CHARACTERISTICS 


Drain-Source Breakdown Voltage 


V(BR)DSX 


25 


- 


Vdc 


(I D - 10 ^A, V GS = 0) 










Zero-Gate -Voltage Drain Current 


f DSS 








(V D s - iO V, V GS = 0) T a = 25°C 




- 


10 


nAdc 


T a = 150°C 




- 


10 


jiAdc 


Gate Reverse Current 


*GSS 




± 10 


pAdc 


(V GS = ± 15 Vdc. V DS = 0) 











ON CHARACTERISTICS 



Gate Threshold Voltage 

(V DS = 10 V, I D = lOjiA) 


V GS(Th) 


1.0 


5 


Vdc 


Drain -Source On- Voltage 
(I D = 2.0 mA t V GS = 10V) 


V DS(on) 


- 


1.0 


V 


On-State Drain Current 

<V GS = 10 V, V DS - 10 V) 


^D(on) 


3.0 


- 


mAdc 



SMALL-SIGNAL CHARACTERISTICS 



Forward T ransfer Admittance 

(V DS = 10 V, I D = 2.0 mA, f = 1.0 kHz) 




1000 


- 


/rmho 


Input Capacitance 

(V DS = 10V,V GS =0,f =140 kHz) 


C iss 


- 


5.0 


pF 


Reverse Transfer Capacitance 

(V DS = 0, V GS = 0, f = 140 kHz) 


C rss 




1.3 


pF 


Drain-Substrate Capacitance 

(V D (sub) =10V,f = 140 kHz) 


Cd(sub) 


- 


5.0 


pF 


Drain-Source Resistance 

(V GS = 10V,I D -0,f= 1.0 kHz) 


fds(on) 


- 


300 


ohms 



SWITCHING CHARACTERISTICS 



Tum-On Delay (Fig. 5) 


I D = 2.0 mAdc, V DS = 10 Vdc, 

(V GS - 10 Vdc) 

(See Figure 9; Times Circuit Determined) 


tdi 


- 


45 


ns 


Rise Time (Fig. 6) 


t r 


- 


65 


ns 


Turn-Off Delay (Fig. 7) 


Id 2 


- 


60 


ns 


Fall Time (Fig. 8) 


tf 


- 


100 


ns 



FIG. 6.40 

2N4351 Motorola n-channel enhancement-type MOSFET. 



EXAMPLE 6.4 Using the data provided on the specification sheet of Fig. 6.40 and an 
average threshold voltage of VGS(Th) — 3 V, determine: 

a. The resulting value of k for the MOSFET. 

b. The transfer characteristics. 

Solution: 

r, 7 lD (° n ) 

a. Eq. (6.16): k = w 

(^GS(on) ~~ VGS( Th)) 

3 mA 3 mA 3 X 1CT 3 . 9 

= 9 = 9 = A/V 2 

(10 V — 3 V) 2 (7 V) 2 49 

= 0.061 X 10“ 3 A/V 2 



408 





b. Eq. (6.15): 



MOSFET HANDLING 409 



Id = k(V GS ~ V T ) 2 

= 0.061 X 10“ 3 (V G5 - 3 V) 2 

For V GS = 5 V, 

l D = 0.061 X 10 _3 (5 V - 3 V) 2 = 0.061 X 10“ 3 (2) 2 
= 0.061 X 10“ 3 (4) = 0.244 mA 

For V GS = 8, 10, 12, and 14 V, I D will be 1.525, 3 (as defined), 4.94, and 7.38 mA, 
respectively. The transfer characteristics are sketched in Fig. 6.41. 




6-9 MOSFET HANDLING ^ 

The thin Si0 2 layer between the gate and the channel of MOSFETs has the positive effect 
of providing a high-input-impedance characteristic for the device, but because of its 
extremely thin layer, it introduces a concern for its handling that was not present for the 
BJT or JFET transistors. There is often sufficient accumulation of static charge (picked up 
from the surroundings) to establish a potential difference across the thin layer that can 
break down the layer and establish conduction through it. It is therefore imperative to leave 
the shorting (or conduction) shipping foil (or ring) connecting the leads of the device 
together until the device is to be inserted in the system. The shorting ring prevents the pos- 
sibility of applying a potential across any two terminals of the device. With the ring, the 
potential difference between any two terminals is maintained at 0 V. At the very least 
always touch ground to permit discharge of the accumulated static charge before handling 
the device, and always pick up the transistor by the casing. 

There are often transients (sharp changes in voltage or current) in a network when ele- 
ments are removed or inserted if the power is on. The transient levels can often be more 
than the device can handle, and therefore the power should always be off when network 
changes are made. 

The maximum gate-to- source voltage is normally provided in the list of maximum rat- 
ings of the device. One method of ensuring that this voltage is not exceeded (perhaps by 
transient effects) for either polarity is to introduce two Zener diodes, as shown in Fig. 6.42. 
The Zeners are back to back to ensure protection for either polarity. If both are 30-V 
Zeners and a positive transient of 40 V appears, the lower Zener will “fire” at 30 V and the 
upper will turn on with a 0-V drop (ideally — for the positive “on” region of a semiconduc- 
tor diode) across the other diode. The result is a maximum of 30 V for the gate-to-source 
voltage. One disadvantage introduced by the Zener protection is that the off resistance of 
a Zener diode is less than the input impedance established by the Si0 2 layer. The result is 
a reduction in input resistance, but even so, it is still high enough for most applications. 
So many of the discrete devices now have the Zener protection that some of the concerns 
listed above are not as troublesome. However, it is still best to be somewhat cautious when 
handling discrete MOSFET devices. 



?D 




FIG. 6.42 

Zener-protected MOSFET. 



Co 0 



410 FIELD-EFFECT 
TRANSISTORS 



6.10 VMOS AND UMOS POWER MOSFETs 



One of the disadvantages of the typical planar MOSFET is the reduced power handling 
(typically less than 1 W) and current levels compared with the broad range of bipolar tran- 
sistors. However, through a vertical design such as shown for the VMOS MOSFET in Fig. 
6.43a and the UMOS MOSFET in Fig. 6.43b, power and current levels have been increased 
along with higher switching speeds and reduced operating dissipation. All the elements of 
the planar MOSFET are present in the VMOS or UMOS MOSFETs — the metallic surface 
connection to the terminals of the device, the Si 02 layer between the gate, and the p-type 
region between the drain and the source for the growth of the induced /i-channel (enhance- 
ment-mode operation). The term vertical is due primarily to the fact that the channel is 
now formed in the vertical direction resulting in a vertical current direction rather than the 
horizontal direction for the planar device. However, the channel of Fig. 6.43a also has the 
appearance of a “V” cut in the semiconductor base, which often stands out as the reason 
for the name for the device. The construction of Fig. 6.43a is somewhat simplistic in 
nature, leaving out some of the transition levels of doping, but it does permit a description 
of the most important facets of its operation. 




FIG. 6.43 

(a) VMOS MOSFET; (b) UMOS MOSFET. 

The application of a positive voltage to the drain and a negative voltage to the source 
with the gate at 0 V or some typical positive “on” level as shown in Fig. 6.43a results in 
the induced ^-channel in the narrow p-type region of the device. The length of the chan- 
nel is now defined by the vertical height of the p-region, which can be made significantly 
less than that of a channel using planar construction. On a horizontal plane the length of 
the channel is limited to 1 /jl m to 2 /xm (1 ptm = 10 -6 m). Diffusion layers (such as the p- 
region of Fig. 6.43) can be controlled to small fractions of a micrometer. Since decreasing 
channel lengths result in reduced resistance levels, the power dissipation level of the device 
(power lost in the form of heat) at operating current levels will be reduced. In addition, the 
contact area between the channel and the n + region is greatly increased by the vertical mode 
construction, contributing to a further decrease in the resistance level and an increased area 
for current between the doping layers. There is also the existence of two conduction paths 
between drain and source, as shown in Fig. 6.43, to further contribute to a higher current 
rating. The net result is a device with drain currents that can reach the ampere levels with 
power levels exceeding 10 W. 

The VMOS MOSFET was the first in line of vertical MOSFETs designed primarily to 
be used as power switches to control the operation of power supplies, low- voltage motor 
controllers, DC- to DC-con vertors, flat-panel displays, and a host of applications in today’s 
automobiles. Fundamentally, a good power switch should work at relatively low voltages 
(less than 200 V), has excellent high-speed characteristics, and low levels of “on” resistance 
to ensure minimum power losses during operation. Over time, a variety of other vertical 
designs began to surface to improve on the “V” construction of Fig. 6.43a. The delicate 



etching required to establish the V groove resulted in difficulties establishing a consistent CMOS 411 

threshold voltage, and the sharp tip at the end of the channel created high electric fields, 

which affected the breakdown voltage of the MOSFET. The breakdown voltage is important 

because it is directly related to the “on” resistance. Increase the breakdown voltage and the 

“on” resistance begins to increase. 

One improvement over the “V” design is the “U” groove or channel as appearing in 
Fig. 6.43b. The operation of this UMOS MOSFET (also called Trench MOSFET) is very 
similar to that of the VMOS MOSFET but with improved characteristics. First the fabrica- 
tion process is preferred because the trench-etching process developed for memory cells 
in DRAMs can be utilized. The result is reduced widths in the neighborhood of 2-10 gm 
compared with the VMOS construction with widths in the 20-30 gm range. The channel 
width itself may be only 1 /mm with a height of 2 jam. The “on” resistance is less using the 
trench approach because the channel length is decreased and the width of the current path is 
increased near the bottom of the trench. However, due to the large surface area required for 
the heavy current flow, there are capacitive effects that must be considered at frequencies 
beyond 100 kHz. The three that have to be considered are Cgs . C GD , and C D s (respectively 
referred to as Q vv , C rss , and C oss on specification sheets). For the UMOS MOSFET the gate- 
to-source capacitance at the input is the largest and typically thousands of pF. 

The Toshiba line of UMOS-V MOSFETs has a drain current running from 1 1 A to 45 A 
with “on” resistances as low as 3.1-1 1 .5 mil at 10 V. The maximum drain-to- source voltage 
for the units is 30 V, and the gate-to- source capacitance ranges from 1400 pF to 4600 pF. 

They are primarily used in flat-panel displays, desktop and mobile computers, and other 
portable electronic devices. 

In general, therefore 

Power MOSFETs have reduced “on” resistance levels and higher current and power 
ratings than planar MOSFETs. 

An additional important characteristic of the vertical construction is: 

Power MOSFETs have a positive temperature coefficient , which combats the possibility 
of thermal runaway . 

If the temperature of a device should increase due to the surrounding medium or currents 
of the device, the resistance levels will increase, causing a reduction in drain current rather 
than an increase as encountered for a conventional device. Negative temperature coeffi- 
cients result in decreased levels of resistance with increases in temperature, which fuel the 
growing current levels and result in further temperature instability and thermal runaway. 

Another positive characteristic of the vertical configuration is: 

The reduced charge storage levels result in faster switching times for vertical construc- 
tion compared to those for conventional planar construction. 

In fact, VMOS and UMOS devices typically have switching times less than one-half that 
encountered for the typical B JT transistor. 



6-11 CMOS ^ 

A very effective logic circuit can be established by constructing a /7-channel and an ^-channel 
MOSFET on the same substrate as shown in Fig. 6.44. Note the induced /7-channel on the 
left and the induced ^-channel on the right for the p- and ^-channel devices, respectively. 
The configuration is referred to as a complementary MOSFET arrangement (CMOS); it 
has extensive applications in computer logic design. The relatively high input impedance, 
fast switching speeds, and lower operating power levels of the CMOS configuration have 
resulted in a whole new discipline referred to as CMOS logic design. 

One very effective use of the complementary arrangement is as an inverter, as shown in 
Fig. 6.45. As introduced for switching transistors, an inverter is a logic element that “inverts” 
the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5 V (1 -state), 
an input level of 0 V will result in an output level of 5 V, and vice versa. Note in Fig. 6.45 
that both gates are connected to the applied signal and both drain to the output V 0 . The 
source of the /7-channel MOSFET ( Q 2 ) is connected directly to the applied voltage V ss , 
whereas the source of the 7z-channel MOSFET ( Qi ) is connected to ground. For the logic 
levels defined above, the application of 5 V at the input should result in approximately 0 V 



412 FIELD-EFFECT 
TRANSISTORS 



V t 




FIG. 6.44 

CMOS with the connections indicated in Fig. 6.45. 



at the output. With 5 V at V* (with respect to ground), Vqs 1 = Vu and Qi is “on,” resulting 
in a relatively low resistance between drain and source as shown in Fig. 6.46. Since V/ and 
Vgs are at 5 V, Vqs 2 — 0 V, which is less than the required V T for the device, resulting in 
an “off” state. The resulting resistance level between drain and source is quite high for Q 2 , 
as shown in Fig. 6.46. A simple application of the voltage-divider rule will reveal that V 0 is 
very close to 0 V, or the 0-state, establishing the desired inversion process. For an applied 
voltage Vi of 0 V (0-state), Vqs 1 — 0 V, and Q\ will be “off” with V S s 2 — _ 5 V, turning 
on the p-channel MOSFET. The result is that Q 2 will present a small resistance level, <2i 
a high resistance, and V 0 = Vgs — 5 V (the 1 -state). Since the drain current that flows for 
either case is limited by the “off” transistor to the leakage value, the power dissipated by 
the device in either state is very low. Additional comment on the application of CMOS logic 
is presented in Chapter 13. 



v i 



o- 

+ 



5 V 

(1-state) 



,U,o = 5V 



v gs 2 



lP 



p-channel 

MOSFET 



e 2 



V ss ? 5V 



■o^sOV 

(0-state) & off 



,/i 



Jh 



^-channel 

MOSFET 

Qi 



Q\ on 



V GS, 



leakage 



R 2 (high) 



— o V n 



RjVss 

R-i + R 2 



= 0 V (0-state) 



(low) 



FIG. 6.45 

CMOS inverter. 



FIG. 6.46 

Relative resistance levels for V t = 5 V 
(1 -state). 



6-12 MESFETs ^ 

As noted in earlier discussions, the use of GaAs in the construction of semiconductor 
devices has been around for quite a few decades. Unfortunately, however, the manufactur- 
ing costs, lower resulting density in ICs, and production problems have kept it from prom- 
inence in the industry until the last few years. The need for high-speed devices and 
improved production methods in recent years have established a strong demand for large- 
scale integrated circuits using GaAs. 





MESFETs 413 



Although the Si MOSFETs just described can be made using GaAs instead, it is a more 
difficult manufacturing process due to diffusion problems. However, the production of FETs 
using a Schottky barrier (discussed in detail in Chapter 16) at the gate can be done quite 
efficiently: 

Schottky barriers are barriers established by depositing a metal such as tungsten on an 
n-type channel. 

The use of a Schottky barrier at the gate is the major difference from the depletion- and 
enhancement-type MOSFETs, which employ an insulating barrier between the metal con- 
tact and the n - type channel. The absence of an insulating layer reduces the distance between 
the metal contact surface of the gate and the semiconductor layer, resulting in a lower level 
of stray capacitance between the two surfaces (recall the effect of distance between the 
plates of a capacitor and its terminal capacitance). The result of the lower capacitance level 
is a reduced sensitivity to high frequencies (forming a shorting effect), which further sup- 
ports the high mobility of carriers in the GaAs material. 

The presence of a metal-semiconductor junction is the reason such FETs are called 
metal-semiconductor field-effect transistors (MESFETs). The basic construction of a 
MESFET is provided in Fig. 6.47. Note in Fig. 6.47 that the gate terminal is connected 
directly to a metallic conductor lying directly against the ^-channel between the source and 
drain terminals. The only difference from the depletion-type MOSFET construction is the 
absence of the insulator at the gate. When a negative voltage is applied to the gate, it will 
attract free negative carriers (electrons) in the channel to the metal surface, reducing the 
number of carriers in the channel. The result is a reduced drain current, as shown in Fig. 6.48, 
for increasing values of negative voltage at the gate terminal. For positive voltages at the 
gate, additional electrons will be attracted into the channel and the current will rise as shown 
by the drain characteristics of Fig. 6.48. The fact that the drain and transfer characteristics of 
the depletion-type MESFET are so similar to those of the depletion-type MOSFET results 
in analysis techniques similar to those applied to depletion-type MOSFETs. The defined 
polarities and current directions for the MESFET are provided in Fig. 6.49 along with the 
symbol for the device. 



Heavily doped 
72-type region 



Lightly doped 
n-type region 



Metal 

(tungsten) 




FIG. 6.47 

Basic construction of an n-channel MESFET. 




Characteristics of an n-channel MESFET. 




FIG. 6.49 

Symbol and basic biasing arrangement for an 
n-channel MESFET. 




414 FI ELD-EFFECT There are also enhancement-type MESFETs with a construction the same as in Fig. 6.47 

TRAN S I STO RS but w ithout the initial channel, as shown in Fig. 6.50 along with its graphic symbol. The re- 

sponse and characteristics are essentially the same as for the enhancement-type MOSFET. 
However, due to the Schottky barrier at the gate, the positive threshold voltage is limited 
to 0 V to about 0.4 V because the “turn-on” voltage for a Schottky barrier diode is about 

0.7 V. Again, the analysis techniques applied to enhancement-type MESFETs are similar 
to those employed for enhancement-type MOSFETs. 



Heavily doped 
ft-type region 



Metal 





(a) (b) 

FIG. 6.50 

Enhancement-type MESFET: (a) construction; (b) symbol 



It is important to realize, however, that the channel must be an n-type material in a MESFET. 
The mobility of holes in GaAs is relatively low compared to that of the negatively charged car- 
riers, losing the advantage of using GaAs for high-speed applications. The result is: 

Depletion-type and enhancement-type MESFETs are made with an n-channel between 
the drain and the source, and therefore only n-type MESFETs are commercially available. 

For both types of MESFETs the channel length (identified in Figs. 6.47 and 6.50) should 
be made as short as possible for high-speed applications. The length is typically between 
0.1 /im and 1 jam. 

6-15 SUMMARY TABLE ^ 

Since the transfer curves and some important characteristics vary from one type of FET to 
another, Table 6.3 was developed to clearly display the differences from one device to the 
next. A clear understanding of all the curves and parameters of the table will provide a suf- 
ficient background for the dc and ac analyses to follow. Take a moment to ensure that each 
curve is recognizable and its derivation understood, and then establish a basis for compari- 
son of the levels of the important parameters of R t and Q for each device. 

6.14 SUMMARY ^ 

Important Conclusions and Concepts 

1. A current-controlled device is one in which a current defines the operating condi- 
tions of the device, whereas a voltage-controlled device is one in which a particular 
voltage defines the operating conditions. 

2. The JFET can actually be used as a voltage-controlled resistor because of a unique 
sensitivity of the drain-to- source impedance to the gate-to- source voltage. 

3. The maximum current for any JFET is labeled I DSS and occurs when Vqs = 0 V. 

4. The minimum current for a JFET occurs at pinch-off defined by Vqs — Vp. 

5. The relationship between the drain current and the gate-to- source voltage of a JFET is 
a nonlinear one defined by Shockley’s equation. As the current level approaches 
loss ’ ^e sensitivity of I D to changes in Vqs increases significantly. 



TABLE 6.3 

Field Effect Transistors 



Symbol and Input Resistance 

Type Basic Relationships Transfer Curve and Capacitance 




416 FIELD-EFFECT 
TRANSISTORS 



6. The transfer characteristics ( J D versus V GS ) are characteristics of the device itself and 
are not sensitive to the network in which the JFET is employed. 

7. When V GS = Vp/2, I D = 7 D ^/4; and at a point where I D = 7 D ^/2, V GS = 0.3 V. 

8. Maximum operating conditions are determined by the product of the drain- to- source 
voltage and the drain current. 

9. MOSFETs are available in one of two types: depletion and enhancement. 

10. The depletion-type MOSFET has the same transfer characteristics as a JFET for drain 
currents up to the I DSS level. At this point the characteristics of a depletion-type MOSFET 
continue to levels above I DSS , whereas those of the JFET will end. 

1 1 . The arrow in the symbol of ^-channel JFETs or MOSFETs will always point in to the 
center of the symbol, whereas those of a ^-channel device will always point out of 
the center of the symbol. 

12. The transfer characteristics of an enhancement-type MOSFET are not defined by 
Shockley’s equation but rather by a nonlinear equation controlled by the gate-to-source 
voltage, the threshold voltage, and a constant k defined by the device employed. The 
resulting plot of I D versus V GS rises exponentially with incrseasing values of V GS . 

13. Always handle MOSFETs with additional care due to the static electricity that exists 
in places we might least suspect. Do not remove any shorting mechanism between the 
leads of the device until it is installed. 

14. A CMOS (complementary MOSFET) device employs a unique combination of a p- 
channel and an n -channel MOSFET with a single set of external leads. It has the 
advantages of a very high input impedance, fast switching speeds, and low operating 
power levels, all of which make it very useful in logic circuits. 

15. A depletion-type MESFET includes a metal-semiconductor junction, resulting in char- 
acteristics that match those of an n -channel depletion-type JFET. Enhancement- 
type MESFETs have the same characteristics as enhancement- type MOSFETs. The 
result of this similarity is that the same type of dc and ac analysis techniques can be 
applied to MESFETs as was applied to JFETs. 



Equations 

JFET: 

j _ j A _ v® V 

In - Inis I 1 Vp J 



In = h 



D i DSS\V gs = 0V’ l D 



=ov> Id ~ 0mA|y G5= y p , Id — 



wss 



V GS =Vp/2 



V GS = 0.3Vp|/ D = W 2 



Vgs 
p d “ VdsId 
rd 



M i - Jt 2 - 



[ DSS 



(1 - V GS /Vp) 2 
MOSFET (enhancement): 



k(V GS - V T ) 2 



k = 



/, 



D( on) 



(v G5 (on) - v T y 



6.15 COMPUTER ANALYSIS ^ 

PSpice Windows 

The characteristics of an ^-channel JFET can be displayed using the same procedure 
employed for the transistor in Section 3.13. The series of curves across the characteristics 
plotted against various values of voltage requires a nested sweep within the sweep for the 
drain-to- source voltage. The required configuration of Fig. 6.51 is constructed using pro- 
cedures described in the previous chapters. In particular, note the complete absence of 
resistors since the input impedance is assumed to be infinite, resulting in a gate current of 0 A. 



COMPUTER ANALYSIS 417 



The JFET is found under Part in the Place Part dialog box. It can be called up by simply 
typing in JFET in the provided space under the Part heading. Once in place, a single click 
on the symbol followed by Edit-PSpice Model will result in the PSpice Model Editor 
Demo dialog box. Note that Beta is equal to 1.304 mA/V 2 and Vto is —3 V. For the junc- 
tion field effect transistor Beta is defined by 



(A/v 2 ) ( 6 . 17 ) 



Beta = 



wss 

V P 2 



The parameter Vto defines Vqs — Vp — —3 V as the pinch-off voltage. Using Eq. (6.17), 
one can solve for I DS s and find that it is about 1 1 .37 mA. Once the plots are obtained one can 
check whether both of these parameters are accurately defined by the characteristics. With 
the network established, select a New Simulation to obtain the New Simulation dialog box. 
Using OrCAD 6-1 as the name followed by Create results in the Simulation Settings dialog 
box, in which DC Sweep is selected under the Analysis type heading. The Sweep variable 
is set as a Voltage source with the Name VDD. The Start Value is 0 V, the End Value is 
10 V, and the Increment is 0.01 V. Now select Secondary Sweep and apply the Name VGG 
with a Start Value of 0 V, an End Value of -5 V, and an Increment of -1 V. Finally, the 
Secondary Sweep must be enabled by ensuring the check appears in the box to the left of the 
listing, followed by an OK to leave the dialog box. A Simulation, and the SCHEMATIC 
screen will appear with a horizontal axis labeled VDD extending from 0 V to 10 V. Continue 
with the sequence Trace- Add Trace to obtain the Add Traces dialog box, and select ID(J1) 
to obtain the characteristics of Fig. 6.52. Note in particular that I D $s is very close to 1 1.7 mA 
as predicted based on the value of Beta. Also note that cutoff does occur at Vqs = Vp = — 3 V. 



FH OrCAD Capture OS - Demo Edition - (/ - (SC 



|ite £dil ^iew loots £lace yacro P£pice 
Accessories Options Window Help cadence 



SLItt MA i IU1 -U rLAl) w 




it ft 




r / 


: 


± X 


+ 


1 r 


+ 1 




1 


& 1* 






St j 


^ ‘ft 




“a 





FIG. 6.51 

Network used to obtain the characteristics of 
the n- channel J2N3819 JFET. 



SCHEMATICI-OjCAD 6-1 - PSpice A/D Dhtiu - [OrCAD 6-1 (active)] 




FIG. 6.52 

Drain characteristics for the n-channel J2N3819 JFET of Fig. 6.51. 



The transfer characteristics can be obtained by setting up a New Simulation that has a 
single sweep since there is only one curve to plot. Once DC Sweep is again selected, the 
Name is VGG with a Start Value of -3 V, an End Value of 0 V, and an Increment of 
0.01 V. Since there is no need for a secondary nested sweep, select OK, and the simula- 
tion is performed. When the graph appears, select Trace- Add Trace-ID(Jl) to obtain the 
transfer characteristics of Fig. 6.53. Note how the axis is set with the —3 V to the far left and 
the 0 V to the far right. Again, I DSS is very close to the predicted 1 1.7 mA and Vp = —3 V. 




FIELD-EFFECT 

TRANSISTORS 




FIG. 6.53 

Transfer characteristics for the n-channel J2N3819 JFET of Fig. 6.51. 



PROBLEMS ^ 

*Note: Asterisks indicate more difficult problems. 

6.2 Construction and Characteristics of IFETs 

1. a. Draw the basic construction of a p-channel JFET. 

b. Apply the proper biasing between drain and source and sketch the depletion region for 
Vgs = 0 V. 

2. Using the characteristics of Fig. 6.11, determine Id for the following levels of V G s (with 
Vds > V P ): 

a. T G5 = 0V. 

b. V GS = -1 V. 

c. Vqs = —1.5 V. 

d. V G5 = -1.8 V. 

e. V G5 =-4V. 

f. Vqs = —6 V. 

3. Using the results of problem 2 plot the transfer characteristics of I D vs. V GS . 

4. a. Determine V DS for V GS = 0 V and I D = 6 mA using the characteristics of Fig. 6. 1 1. 

b. Using the results of part (a), calculate the resistance of the JFET for the region I D = 0 to 
6 mA for V GS = 0 V. 

c. Determine V DS for V GS = - 1 V and I D = 3 mA. 

d. Using the results of part (c), calculate the resistance of the JFET for the region I D = 0 to 
3 mA for V G s = -IV. 

e. Determine V DS for V GS = — 2 V and I D = 1.5 mA. 

f. Using the results of part (e), calculate the resistance of the JFET for the region I D = 0 to 
1.5 mA for V GS = -2 V. 

g. Defining the result of part (b) as r 0 , determine the resistance for V GS = — 1 V using 
Eq. (6.1) and compare with the results of part (d). 

h. Repeat part (g) for V GS = —2 V using the same equation, and compare the results with part (f). 

i. Based on the results of parts (g) and (h), does Eq. (6.1) appear to be a valid approximation? 

5. Using the characteristics of Fig. 6. 1 1 : 

a. Determine the difference in drain current (for V DS > V P ) between V GS = 0 V and V GS = -1 V. 

b. Repeat part (a) between V GS = — 1 and —2 V. 

c. Repeat part (a) between V GS = —2 and —3 V. 

d. Repeat part (a) between V GS = —3 and —4 V. 

e. Is there a marked change in the difference in current levels as V GS becomes increasingly 
negative? 




6 . 



7 . 



8 . 



9 . 



6.3 



10 . 



11 . 



12 . 



13 . 



14 . 



15 . 



16 . 



f. Is the relationship between the change in V GS and the resulting change in I D linear or non- 
linear? Explain. 

What are the major differences between the collector characteristics of a BJT transistor and the 
drain characteristics of a JFET transistor? Compare the units of each axis and the controlling vari- 
able. How does I c react to increasing levels of I B versus changes in I D to increasingly negative 
values of V GS 1 How does the spacing between steps of I B compare to the spacing between steps 
of V GS 1 Compare V Gsat to V P in defining the nonlinear region at low levels of output voltage. 

a. Describe in your own words why I G is effectively 0 A for a JFET transistor. 

b. Why is the input impedance to a JFET so high? 

c. Why is the terminology field effect appropriate for this important three-terminal device? 

Given I DSS =12 mA and | V P \ = 6 V, sketch a probable distribution of characteristic curves 
for the JFET (similar to Fig. 6.1 1). 

In general, comment on the polarity of the various voltages and direction of the currents for an 
n-channel JFET versus a ^-channel JFET. 

Transfer Characteristics 

Given the characteristics of Fig. 6.54: 

a. Sketch the transfer characteristics directly from the drain characteristics. 

b. Using Fig. 6.54 to establish the values of I DS s and V P , sketch the transfer characteristics 
using Shockley’s equation. 

c. Compare the characteristics of parts (a) and (b). Are there any major differences? 



i D (mA) 



Vgs = 0V 















p: 


















































































































































































































































































































































- 1 V 
t 










i 




























































/ 




/ 


























































/ 
























































1 




























































ii- 


















































2 V 






L 


























































L_ 


























































7 


























































.. 






















































-3V 




' 






















































n 


























































4 V - 


J 






















































■ J 






















































— f — 

-5 V 
























































*-■111111111 t i i i i i i i i i i i 






- J j— 1 



10 



15 



20 



25 



Vi*CV) 



FIG. 6.54 

Problems 10 and 20. 



a. Given I DSS =12 mA and V P = —4 V, sketch the transfer characteristics for the JFET 
transistor. 

b. Sketch the drain characteristics for the device of part (a). 

Given I DSS = 9 mA and V P = —4 V, determine I D when: 

a. V G s = 0 V. 

b. V G s = — 2 V. 

c. k G5 = -4V. 

d. V G5 = -6V. 

Given I DSS =16 mA and V P = —5 V, sketch the transfer characteristics using the data points 
of Table 6.1. Determine the value of I D at V GS = -3 V from the curve, and compare it to the 
value determined using Shockley’s equation. Repeat the above for V GS = -1 V. 

For a particular JFET if I D = 4 mA when V GS = — 3 V, determine V P if I DSS =12 mA. 

Given I D ss — 6 mA and V P = —4.5 V: 

a. Determine I D at V GS = — 2 and —3.6 V. 

b. Determine V GS at I D = 3 and 5.5 mA. 

Given a Q-point of I D = 3 mA and V GS = — 3 V, determine I DS s if V P = —6 V. 




17. A p-channel JFET has device parameters of I DS s — 7.5 mA and V P = 4 V. Sketch the transfer 
characteristics. 

Specification Sheets (IFETs) 

18. Define the region of operation for the 2N5457 JFET of Fig. 6.20 using the range of I DSS and V P 
provided. That is, sketch the transfer curve defined by the maximum I DSS and V P and the transfer 
curve for the minimum I DSS and V P . Then, shade in the resulting area between the two curves. 

19. For the 2N5457 JFET of Fig. 6.20, what is the power rating at a typical operating temperature 
of 45°C using the 5.0 mW/°C derating factor. 

20. Define the region of operation for the JFET of Fig. 6.54 if V D s max = 30 V and Po maLX = 100 mW. 

6.5 Instrumentation 

21. Using the characteristics of Fig. 6.22, determine I D at V GS = -0.7 V and V DS = 10 V. 

22. Referring to Fig. 6.22, is the locus of pinch-off values defined by the region ofV DS < \V P \ = 3 V? 

23. Determine V P for the characteristics of Fig. 6.22 using I DSS and I D at some value of V GS . That 
is, simply substitute into Shockley’s equation and solve for V P . Compare the result to the 
assumed value of —3 V from the characteristics. 

24. Using I DSS = 9 mA and V P = — 3 V for the characteristics of Fig. 6.22, calculate I D at V GS = 
— 1 V using Shockley’s equation and compare to the level in Fig. 6.22. 

25. a. Calculate the resistance associated with the JFET of Fig. 6.22 for V GS = 0 V from 

I D = 0 mA to 4 mA. 

b. Repeat part (a) for V GS = -0.5 V from I D = 0 to 3 mA. 

c. Assigning the label r Q to the result of part (a) and r d to that of part (b), use Eq. (6.1) to 
determine r d and compare to the result of part (b). 

6.7 Depletion-Type IVIOSFET 

26. a. Sketch the basic construction of a ^-channel depletion-type MOSFET. 

b. Apply the proper drain-to-source voltage and sketch the flow of electrons for V GS = 0 V. 

27. In what ways is the construction of a depletion-type MOSFET similar to that of a JFET? In 
what ways is it different? 

28. Explain in your own words why the application of a positive voltage to the gate of an ^-channel 
depletion-type MOSFET will result in a drain current exceeding I DSS . 

29. Given a depletion-type MOSFET with I DSS = 6 mA and V P = —3 V, determine the drain cur- 
rent at V G s = —1, 0, 1, and 2 V. Compare the difference in current levels between —IV and 
0 V with the difference between 1 V and 2 V. In the positive V G $ region, does the drain current 
increase at a significantly higher rate than for negative values? Does the I D curve become more 
and more vertical with increasing positive values of V GS 1 Is there a linear or a nonlinear rela- 
tionship between I D and V GS 7 Explain. 

30. Sketch the transfer and drain characteristics of an ^-channel depletion-type MOSFET with 
loss — 12 mA and V P = —8 V for a range of V GS = ~V P to V GS = 1 V. 

31. Given I D = 14 mA and V GS = 1 V, determine V P if I DSS = 9.5 mA for a depletion-type 
MOSFET. 

32. Given I D = 4 mA at V GS = — 2 V, determine I DSS if Up = -5 V. 

33. Using an average value of 2.9 mA for the I DSS of the 2N3797 MOSFET of Fig. 6.31, determine 
the level of V GS that will result in a maximum drain current of 20 mA if V P = —5 V. 

34. If the drain current for the 2N3797 MOSFET of Fig. 6.3 1 is 8 mA, what is the maximum per- 
missible value of V DS utilizing the maximum power rating? 

6.8 Enhancement-Type IVIOSFET 

35. a. What is the significant difference between the construction of an enhancement-type MOSFET 

and a depletion-type MOSFET? 

b. Sketch a ^-channel enhancement-type MOSFET with the proper biasing applied 
(V DS > 0 V, V GS > V T ) and indicate the channel, the direction of electron flow, and the 
resulting depletion region. 

c. In your own words, briefly describe the basic operation of an enhancement-type MOSFET. 

36. a. Sketch the transfer and drain characteristics of an ^-channel enhancement-type MOSFET if 

Vj = 3.5 V and k = 0.4 X 10“ 3 A/V 2 . 

b. Repeat part (a) for the transfer characteristics if V T is maintained at 3.5 V but k is increased 
by 100% to 0.8 X 10“ 3 A/V 2 . 



37. a. Given UGS(Th) — 4 V and I Dion) = 4 mA at Vcsion) = 6 V, determine k and write the gen- 

eral expression for I D in the format of Eq. (6.15). 

b. Sketch the transfer characteristics for the device of part (a). 

c. Determine I D for the device of part (a) at V GS = 2, 5, and 10 V. 

38. Given the transfer characteristics of Fig. 6.55, determine V T and k and write the general equa- 
tion for I D . 




39. Given k — 0.4 X 10 3 A/V 2 and Io(on) = 3 mA with Vgs(oii) — 4 V, determine V T . 

40. The maximum drain current for the 2N4351 ^-channel enhancement-type MOSFET is 
30 mA. Determine V GS at this current level if k = 0.06 X 1CT 3 A/V 2 and V T is the maxi- 
mum value. 

41. Does the current of an enhancement-type MOSFET increase at about the same rate as a depletion- 
type MOSFET for the conduction region? Carefully review the general format of the equa- 
tions, and if your mathematics background includes differential calculus, calculate dI D /dV GS 
and compare its magnitude. 

42. Sketch the transfer characteristics of a p-channel enhancement-type MOSFET if V T = — 5 V 
and k = 0.45 X 10“ 3 A/V 2 . 

43. Sketch the curve of I D = 0.5 X 10 _3 ( k/vs) and I D = 0.5 X 10 3 (VV;;s — 4) 2 for V GS from 0 V 

to 10 V. Does V T = 4 V have a significant effect on the level of I D for this region? 

6.1 0 VMOS and UMOS Power MOSFETs 

44. a. Describe in your own words why the VMOS FET can withstand a higher current and power 

rating than devices constructed with standard techniques. 

b. Why do VMOS FETs have reduced channel resistance levels? 

c. Why is a positive temperature coefficient desirable? 

45. What are the relative advantages of the UMOS technology over the VMOS technology? 

6.11 CMOS 

*46. a. Describe in your own words the operation of the network of Fig. 6.45 with V t = 0 V. 

b. If the “on” MOSFET of Fig. 6.45 (with V) = 0 V) has a drain current of 4 mA with 

Vds = 0.1 V, what is the approximate resistance level of the device? If I D = 0.5 /jl A for 
the “off” transistor, what is the approximate resistance of the device? Do the resulting 
resistance levels suggest that the desired output voltage level will result? 

47. Research CMOS logic at your local or college library, and describe the range of applications 
and basic advantages of the approach. 



m3 



FET Biasing 




CHAPTER OBJECTIVES ^ 

Be able to perform a dc analysis of JFET, MOSFET, and MESFET networks. 
Become proficient in the use of load-line analysis to examine FET networks. 
Develop confidence in the dc analysis of networks with both FETs and BJTs. 
Understand how to use the Universal JFET Bias Curve to analyze the various FET 
configurations. 



7,1 INTRODUCTION ^ 

In Chapter 4 we found that the biasing levels for a silicon transistor configuration can be 
obtained using the approximate characteristic equations V BE = 0.7 V, I E — fiI B , and 
Iq = I E . The link between input and output variables is provided by /3, which is assumed 
to be fixed in magnitude for the analysis to be performed. The fact that beta is a constant 
establishes a linear relationship between I c and I B . Doubling the value of I B will double 
the level of I E , and so on. 

For the field-effect transistor, the relationship between input and output quantities is 
nonlinear due to the squared term in Shockley’s equation. Linear relationships result in 
straight lines when plotted on a graph of one variable versus the other, whereas nonlinear 
functions result in curves as obtained for the transfer characteristics of a JFET. The nonlin- 
ear relationship between Id and Vqs can complicate the mathematical approach to the dc 
analysis of FET configurations. A graphical approach may limit solutions to tenths-place 
accuracy, but it is a quicker method for most FET amplifiers. Since the graphical approach 
is in general the most popular, the analysis of this chapter will have graphical solutions 
rather than mathematical solutions. 

Another distinct difference between the analysis of B JT and FET transistors is that: 

The controlling variable for a BJT transistor is a current level , whereas for the FET a 
voltage is the controlling variable. 

In both cases, however, the controlled variable on the output side is a current level that also 
defines the important voltage levels of the output circuit. 




The general relationships that can be applied to the dc analysis of all FET amplifiers are 



FIXED-BIAS 423 
CONFIGURATION 




( 7 . 1 ) 



and 




( 7 . 2 ) 



For JFETs and depletion- type MOSFETs and MESFETs, Shockley’ s equation is applied 
to relate the input and output quantities: 



Id ~ Idss\ 1 



VgA 

VpJ 



2 



( 7 . 3 ) 



For enhancement-type MOSFETs and MESFETs, the following equation is applicable: 



Id = KVcs ~ V T r 



( 7 . 4 ) 



It is particularly important to realize that all of the equations above are for the field- 
effect transistor only\ They do not change with each network configuration so long as the 
device is in the active region. The network simply defines the level of current and voltage 
associated with the operating point through its own set of equations. In reality, the dc solu- 
tion of B JT and FET networks is the solution of simultaneous equations established by the 
device and the network. The solution can be determined using a mathematical or graphical 
approach — a fact to be demonstrated by the first few networks to be analyzed. However, as 
noted earlier, the graphical approach is the most popular for FET networks and is employed 
in this book. 

The first few sections of this chapter are limited to JFETs and the graphical approach 
to analysis. The depletion-type MOSFET will then be examined with its increased range 
of operating points, followed by the enhancement-type MOSFET. Finally, problems of a 
design nature are investigated to fully test the concepts and procedures introduced in the 
chapter. 



7.2 FIXED-BIAS CONFIGURATION ^ 

The simplest of biasing arrangements for the ^-channel JFET appears in Fig. 7.1. Referred 
to as the fixed-bias configuration, it is one of the few FET configurations that can be 
solved just as directly using either a mathematical or a graphical approach. Both methods 
are included in this section to demonstrate the difference between the two methods and 
also to establish the fact that the same solution can be obtained using either approach. 



Vdd 




FIG. 7.1 

Fixed-bias configuration. 



424 FET BIASING 



Vdd 




The configuration of Fig. 7.1 includes the ac levels V t and V Q and the coupling capacitors 
(Ci and C 2 ). Recall that the coupling capacitors are “open circuits” for the dc analysis and 
low impedances (essentially short circuits) for the ac analysis. The resistor R G is present 
to ensure that V t appears at the input to the FET amplifier for the ac analysis (Chapter 8). 
For the dc analysis, 

h = OA 

and V R(} = I g R g = (0 A )R G = 0 V 

The zero- volt drop across R G permits replacing R G by a short-circuit equivalent, as appear- 
ing in the network of Fig. 7.2, specifically redrawn for the dc analysis. 

The fact that the negative terminal of the battery is connected directly to the defined 
positive potential of V GS clearly reveals that the polarity of V GS is directly opposite to that 
of V G q. Applying Kirchhoff ’ s voltage law in the clockwise direction of the indicated loop 
of Fig. 7.2 results in 

-V GG - V GS = 0 



and 



Vgs ~ ~Vgg 



( 7 . 5 ) 



Since V GG is a fixed dc supply, the voltage Vqs is fixed in magnitude, resulting in the des- 
ignation “fixed-bias configuration.” 

The resulting level of drain current I D is now controlled by Shockley’s equation: 

v 2 

I v rzv 

Id ~ Idss\ 



■ -JSaY 

Vp) 



Since V G $ is a fixed quantity for this configuration, its magnitude and sign can simply be 
substituted into Shockley’ s equation and the resulting level of I D calculated. This is one of 
the few instances in which a mathematical solution to a FET configuration is quite direct. 

A graphical analysis would require a plot of Shockley’s equation as shown in Fig. 7.3. 
Recall that choosing V GS = V P /2 will result in a drain current of loss / 4 when plotting 
the equation. For the analysis of this chapter, the three points defined by I DSS , V P , and the 
intersection just described will be sufficient for plotting the curve. 




FIG. 7.3 

Plotting Shockley’s equation. 




FIG. 7.4 

Finding the solution for the fixed-bias 
configuration. 



In Fig. 7.4, the fixed level of V^has been superimposed as a vertical line at V G $ — — Vgg- 
At any point on the vertical line, the level of V G s is ~V GG — the level of I D must simply be 
determined on this vertical line. The point where the two curves intersect is the common 
solution to the configuration — commonly referred to as the quiescent or operating point. 
The subscript Q will be applied to the drain current and gate-to- source voltage to identify 
their levels at the Q-point. Note in Fig. 7.4 that the quiescent level of I D is determined by 
drawing a horizontal line from the Q-pomi to the vertical I D axis. It is important to realize 



that once the network of Fig. 7.1 is constructed and operating, the dc levels of I D and V GS 
that will be measured by the meters of Fig. 7.5 are the quiescent values defined by Fig. 7.4. 



FIXED-BIAS 425 
CONFIGURATION 



Id q 




Ammeter 



Voltmeter 



Measuring the quiescent values ofI D and V GS . 



The drain-to-source voltage of the output section can be determined by applying 
Kirchhoff s voltage law as follows: 



+ V DS + Id^d ~ Vdd — 0 



and 



Vds ~ Vdd Id^d 



( 7 . 6 ) 



Recall that single-subscript voltages refer to the voltage at a point with respect to ground. 
For the configuration of Fig. 7.2, 



Vc = OV 



( 7 . 7 ) 



Using double-subscript notation, we have 



or 



V D s = V d -V s 
V D = V DS +V S = V DS + OV 



and 



V D = V DS 



( 7 . 8 ) 



In addition, 
or 



Vgs = - V* 

V G = y G5 + y 5 = y GS + o V 



and 



Vg = Vos 



( 7 . 9 ) 



The fact that V D = V DS and V G = V GS is fairly obvious from the fact that V$ — 0 V, 
but the derivations above were included to emphasize the relationship that exists between 
double- subscript and single-subscript notation. Since the configuration requires two dc sup- 
plies, its use is limited and will not be included in the forthcoming list of the most common 
FET configurations. 




426 FET BIASING 



EXAMPLE 7,1 Determine the following for the network of Fig. 7.6: 



a - VgSq- 

b- b Q - 
c - Vds- 

d. V D . 

e. V G . 

f. v s . 




Solution: 

Mathematical Approach 

a- Vgs q = ~V GG = -2V 

b - , “« = ^ 1 -^) 2 = 10 mA ( 1 -^ l ) 2 

= 10 mA(l - 0.25) 2 = 10 mA(0.75) 2 = 10mA(0.5625) 

= 5.625 mA 

c. V DS = V DD - I d R d = 16 V - (5.625 mA)(2 kfl) 

= 16 V - 11.25 V = 4.75 V 

d. V D = V DS = 4.75 V 

e . v G = V GS = — 2 V 

f . V s = 0 V 



Graphical Approach The resulting Shockley curve and the vertical line at V G $ = — 2 V 
are provided in Fig. 7.7. It is certainly difficult to read beyond the second place without 




FIG, 7,7 

Graphical solution for the network of Fig. 7.6. 



significantly increasing the size of the figure, but a solution of 5.6 mA from the graph of 
Fig. 7.7 is quite acceptable. 

a. Therefore, 

Vgs q = ~V GG = -2Y 

b. I D = 5.6 mA 

c. Vds = V DD - I d R d = 16 V - (5.6mA)(2kH) 

= 16 V - 11.2 V = 4.8 V 

d. V D = V DS = 4.8 V 

e . v G = V GS = — 2 V 

f . = 0 V 

The results clearly confirm the fact that the mathematical and graphical approaches 
generate solutions that are quite close. 



7.1 SELF-BIAS CONFIGURATION ^ 

The self-bias configuration eliminates the need for two dc supplies. The controlling gate- 
to-source voltage is now determined by the voltage across a resistor R s introduced in the 
source leg of the configuration as shown in Fig. 7.8. 




FIG. 7.8 

JFET self-bias configuration. 



For the dc analysis, the capacitors can again be replaced by “open circuits” and the resis- 
tor R g replaced by a short-circuit equivalent since I G = 0 A. The result is the network of 
Fig. 7.9 for the important dc analysis. 

The current through R s is the source current I s , but I s = Id and 

Vr s = Id^s 

For the indicated closed loop of Fig. 7.9, we find that 

-V G5 - = 0 

and V GS = ~V Rs 



or 



Vgs ~ ~Id r s 



( 7 . 10 ) 



Note in this case that is a function of the output current I D and not fixed in magnitude 
as occurred for the fixed-bias configuration. 

Equation (7.10) is defined by the network configuration, and Shockley’s equation relates 
the input and output quantities of the device. Both equations relate the same two variables, 
Id and V G g, permitting either a mathematical or a graphical solution. 



SELF-BIAS 427 
CONFIGURATION 



Vdd 




FIG. 7.9 

DC analysis of the self -bias 
configuration. 



428 



FET BIASING 



A mathematical solution could be obtained simply by substituting Eq. (7.10) into 
Shockley’s equation as follows: 

_ VgA 2 



In = I, 



DSS 



= I 



DSS 



or 



In = I 



DSS' 



1 - 



1 + 



-InRs^ 2 



V P J 

Ij^}s 

V P 

ipRs 

Vp 



By performing the squaring process indicated and rearranging terms, we obtain an equation 
of the following form: 

In + Kd n + Ko = 0 



The quadratic equation can then be solved for the appropriate solution for Id- 

The sequence above defines the mathematical approach. The graphical approach re- 
quires that we first establish the device transfer characteristics as shown in Fig. 7.10. Since 
Eq. (7.10) defines a straight line on the same graph, let us now identify two points on the 
graph that are on the line and simply draw a straight line between the two points. The most 
obvious condition to apply is I D = 0 A since it results in V GS = —IpRs = (0 A)R S = 0 V. 
For Eq. (7.10), therefore, one point on the straight line is defined by I D = 0A and 
V G s — 0 V, as appearing on Fig. 7.10. 




The second point for Eq. (7.10) requires that a level of Vqs or Id be chosen and the cor- 
responding level of the other quantity be determined using Eq. (7.10). The resulting levels 
of I D and Vqs will then define another point on the straight line and permit the drawing of 
the straight line. Suppose, for example, that we choose a level of I D equal to one-half the 
saturation level. That is, 



Id = 



Ipss 

2 



Then 



Vgs ~ IpRs ~ 



Ipss^s 

2 



The result is a second point for the straight-line plot as shown in Fig. 7.11. The straight line 
as defined by Eq. (7.10) is then drawn and the quiescent point obtained at the intersection 
of the straight-line plot and the device characteristic curve. The quiescent values of I D and 
Vqs can then be determined and used to find the other quantities of interest. 

The level of V D s can be determined by applying Kirchhoff’s voltage law to the output 
circuit, with the result that 

Vr s + Vds + Vr d ~ Vdd — 0 
Vds — Vdd ~ Vr s ~ Vr d “ Vdd ~ Is^s ~ IdRd 



and 



but 

and 

In addition, 



and 




FIG. 7.1 1 

Sketching the self-bias line. 



Id ~ Is 



Vds ~ Vdd Id(Rs + Rd) 



V s — Id^s 



V G = ov 



Vd ~ Vds + V s — V DD V R[) 



SELF-BIAS 429 
CONFIGURATION 



( 7 . 11 ) 

( 7 . 12 ) 

( 7 . 13 ) 

( 7 . 14 ) 



EXAMPLE 7.2 

a - Vgs q - 
b- Id q . 
c - Vds- 

d. V s . 

e. V G . 

f. V D . 



Determine the following for the network of Fig. 7.12: 



20 V 




Solution: 

a. The gate-to-source voltage is determined by 

Vqs = —Id^s 

Choosing I D = 4 mA, we obtain 

V G s = —(4 mA)(l kft) = -4 V 
The result is the plot of Fig. 7.13 as defined by the network. 




430 FET BIASING 




Sketching the self-bias line for the network of Fig. 7.12. 



If we happen to choose Id ~ 8 mA, the resulting value of V GS would be —8 V, as 
shown on the same graph. In either case, the same straight line will result, clearly dem- 
onstrating that any appropriate value of I D can be chosen as long as the corresponding 
value of Vqs as determined by Eq. (7.10) is employed. In addition, keep in mind that 
the value of Vqs could be chosen and the value of I D determined graphically. 

For Shockley’s equation, if we choose Vqs = V P /2 = — 3 V, we find that 
Id = loss / 4 — 8 mA/4 = 2 mA, and the plot of Fig. 7.14 will result, representing the 
characteristics of the device. The solution is obtained by superimposing the network 
characteristics defined by Fig. 7.13 on the device characteristics of Fig. 7.14 and finding 
the point of intersection of the two as indicated on Fig. 7.15. The resulting operating 
point results in a quiescent value of gate-to- source voltage of 

V G s q = -2.6 V 




Sketching the device characteristics for the 
JFET of Fig. 7.12. 




FIG. 7.15 

Determining the Q-pointfor the network of 
Fig. 7.12. 



b. At the quiescent point 

b Q = 2.6 mA 

c. Eq. (7.11): V DS = V DD - I D (R S + R D ) 

= 20 V - (2.6 mA)(l kfl + 3.3 kfl) 
= 20 V - 11.18 V 

= 8.82 V 



VOLTAGE-DIVIDER 431 
BIASING 



d. 



e. 

f. 



Eq. (7.12): V s = Ws 

= (2.6mA)(lkI2) 

= 2.6 V 

Eq. (7.13): V G = 0 V 

Eq. (7.14): V D = V DS + = 8.82 V + 2.6 V = 11.42 V 

or V D = V DD - I d R d = 20 V - (2.6 mA)(3.3 kll) = 11.42 V 



EXAMPLE 7.3 Find the quiescent point for the network of Fig. 7.12 if: 

a. R s = 100 12. 

b. R s = 10 kfl. 

Solution: Both R s = 100 II and R s = 10 kll are plotted on Fig. 7.16. 

a. For R s = 100 12: 

I Dq = 6.4 mA 

and from Eq. (7.10), 

Vgs, = -0.64 V 

b. For R s = 10 kll 

Vgs, = -4.6 V 

and from Eq. (7.10), 

I Dq = 0.46 mA 

In particular, note how lower levels of Rs bring the load line of the network closer to the 
I D axis, whereas increasing levels of R s bring the load line closer to the Vqs axis. 




7.4 VOLTAGE-DIVIDER BIASING ^ 

The voltage-divider bias arrangement applied to B JT transistor amplifiers is also applied to 
FET amplifiers as demonstrated by Fig. 7.17. The basic construction is exactly the same, 
but the dc analysis of each is quite different. I G = 0 A for FET amplifiers, but the magni- 
tude of I B for common-emitter BJT amplifiers can affect the dc levels of current and volt- 
age in both the input and output circuits. Recall that I B provides the link between input and 
output circuits for the BJT voltage-divider configuration, whereas V GS does the same for 
the FET configuration. 



432 FET BIASING 




The network of Fig. 7.17 is redrawn as shown in Fig. 7.18 for the dc analysis. Note 
that all the capacitors, including the bypass capacitor Cg, have been replaced by an “open- 
circuit” equivalent in Fig. 7.18b. In addition, the source Vdo was separated into two 
equivalent sources to permit a further separation of the input and output regions of the 
network. Since Iq = 0 A, Kirchhoff s current law requires that I R = Ir 2 , and the series 
equivalent circuit appearing to the left of the figure can be used to find the level of Vq. The 
voltage Vq, equal to the voltage across 7? 2 , can be found using the voltage-divider rule and 
Fig. 7.18a as follows: 



RiVpp 

R\ + 7?2 



( 7 . 15 ) 




FIG. 7.18 

Redrawn network of Fig. 7.17 for dc analysis. 



Applying Kirchhoff s voltage law in the clockwise direction to the indicated loop of 
Fig. 7.18 results in 



- V GS - V Rs = 0 
V G s = V G - V Rs 



and 



Substituting V Rs = I S R S = IdRs, we have 



(7.16) 



VOLTAGE-DIVIDER 433 
BIASING 



Vgs ~ Vg bRs 



The result is an equation that continues to include the same two variables appearing in 
Shockley’s equation: V GS and h> The quantities Vq and R s are fixed by the network con- 
struction. Equation (7.16) is still the equation for a straight line, but the origin is no longer 
a point in the plotting of the line. The procedure for plotting Eq. (7.16) is not a difficult one 
and will proceed as follows. Since any straight line requires two points to be defined, let us 
first use the fact that anywhere on the horizontal axis of Fig. 7.19 the current I D = 0 mA. If 
we therefore select I D to be 0 mA, we are in essence stating that we are somewhere on the 
horizontal axis. The exact location can be determined simply by substituting I D = 0 mA 
into Eq. (7.16) and finding the resulting value of Vqs as follows: 

Vgs ~ “ IdRs 

= V G ~ (OmA )R S 



and 



VGS ~ ^G|/ D =0mA 



(7.17) 



The result specifies that whenever we plot Eq. (7.16), if we choose Id = 0 mA, the value 
of V GS for the plot will be V G volts. The point just determined appears in Fig. 7.19. 




Sketching the network equation for the voltage -divider configuration. 



For the other point, let us now employ the fact that at any point on the vertical axis V GS = 0 V 
and solve for the resulting value of I D : 

Vgs — V G H h)Rs 
o V = Eg - IdRs 



and 



, V c 






£ 

II 

O 

< 



(7.18) 



The result specifies that whenever we plot Eq. (7.16), if V G $ = 0 V, the level of I D is 
determined by Eq. (7.18). This intersection also appears on Fig. 7.19. 

The two points defined above permit the drawing of a straight line to represent Eq. (7.16). 
The intersection of the straight line with the transfer curve in the region to the left of the verti- 
cal axis will define the operating point and the corresponding levels of I D and V GS . 

Since the intersection on the vertical axis is determined by I D = V G / R s and V G is fixed 
by the input network, increasing values of R s will reduce the level of the Id intersection as 



434 FET BIASING 




shown in Fig. 7.20. It is fairly obvious from Fig. 7.20 that: 

Increasing values of R$ result in lower quiescent values of I D and declining values 

o/Vgs- 



Once the quiescent values of I Dq and Vqs q are determined, the remaining network analy- 
sis can be performed in the usual manner. That is, 



Vds ~ V dd ~ 1d(Rd + Rs) 



Vp ~ V DD ~ Id^d 



Vs ~ Id^s 






Vdd 

R\ + R 2 



( 7 . 19 ) 

( 7 . 20 ) 

( 7 . 21 ) 

( 7 . 22 ) 



EXAIVIPLE 7.4 Determine the following for the network of Fig. 7.21 : 




FIG. 7.21 

Example 7.4. 



Solution: 

a. For the transfer characteristics, if I D = loss / 4 — BmA/4 = 2 mA, then Vqs — 
Vp/2 = — 4V/2 = — 2 V. The resulting curve representing Shockley’s equation 
appears in Fig. 7.22. The network equation is defined by 

t / _ ^2 Vdd 
V (Z 

^ 1+^2 

(270 kQ)(16V) 

_ 2.1 Mil + 0.27 Mil 
= 1.82 V 

and V GS = Vq ~ IpRs 

= 1.82 V - / D (1.5kH) 



VOLTAGE-DIVIDER 435 
BIASING 




Determining the Q-pointfor the network of Fig. 7.21. 



When I D = 0 mA, 
When V G5 = 0 V, 



V GS = +1.82 V 



I D ~ 



1.82 V 
1.5 kO 



1.21mA 



The resulting bias line appears on Fig. 7.22 with quiescent values of 

I Dq = 2.4 mA 

and V GSg = -1.8 V 

b. Vp = V DD — IdRd 

= 16 V - (2.4 mA)(2.4 kft) 

= 10.24 V 

c. V s = IoR s = (2.4mA)(1.5kH) 

= 3.6 V 

d. V ds — Vdd ~ Id(Rd + Rs) 

= 16 V - (2.4 mA)(2.4 kft + 1.5 kft) 

= 6.64 V 

or V DS = V D - V s = 10.24 V - 3.6 V 

= 6.64 V 



436 FET BIASING 



e. Although seldom requested, the voltage V DG can easily be determined using 

- V G 

= 10.24 V - 1.82 V 

= 8.42 V 



7.5 COMMON-GATE CONFIGURATION ^ 

The next configuration is one in which the gate terminal is grounded and the input signal 
typically applied to the source terminal and the output signal obtained at the drain terminal 
as shown in Fig. 7.23a. The network can also be drawn as shown in Fig. 7.23b. 





FIG. 7.23 

Two versions of the common- gate configuration. 




FIG. 7.24 

Determining the network 
equation for the configuration of 
Fig. 7.23. 



The network equation can be determined using Fig. 7.24. 

Applying Kirchhoff’ s voltage law in the direction shown in Fig. 7.24 will result in 

— V gs ~ Is*s + Vss = 0 
and V GS = V ss ~ 

but I s = I D 



so 



Vgs ~ Vss Id^s 



( 7 . 23 ) 



Applying the condition Id ~ 0 mA to Eq. 7.23 will result in 

Vgs = V ss - (0)R S 



and 



V G s = 



Vss\ 



I D —0mA 



( 7 . 24 ) 



Applying the condition Vqs = 0 V to Eq. 7.23 will result in 

0 — Vss Id r s 



and 



, V ss 




Id = t~ 

K s 


> 

O 

II 



( 7 . 25 ) 



The resulting load-line appears in Fig. 7.25 intersecting the transfer curve for the JFET 
as shown in the figure. 

The resulting intersection defines the operating current Id q and voltage Vd q for the net- 
work as also indicated in the network. 



COMMON-GATE 437 
CONFIGURATION 




Determining the Q-pointfor the network of Fig. 7.24. 



Applying Kirchhoff s voltage law around the loop containing the two sources, the JFET 
and the resistors R D and R s in Fig. 7.23a and Fig. 7.23b will result in 

+ V dd ~ h)Ri) ~ V DS ~ Ws + Vss = 0 
Substituting I s = I D we have 

+ V DD + Vss ~ Vds ~ b(R D + Rs) — 0 



so that 



Vds ~ V DD + Vss Id( r d + Rs) 



( 7 . 26 ) 



with 



Vd ~ V dd IdRd 



( 7 . 27 ) 



and 



Vs ~ V S s + Id^s 



( 7 . 28 ) 



EXAMPLE 7.5 Determine the following for the common-gate configuration of Fig. 7.26: 

a - V G s q 

b- b Q 

c. V D 

d. y G 

e. V s 12 V 




FIG. 7.26 
Example 7.5. 




438 FET BIASING Solution: Even though V ss is not present in this common-gate configuration the equa- 

tions derived above can still be used by simply substituting V S s — 0 V into each equation 
in which it appears. 

a. For the transfer characteristics Eq. 7.23 becomes 

Vgs — 0 - I d R s 

and V GS = -lefts 

For this equation the origin is one point on the load line while the other must be 
determined at some arbitrary point. Choosing I D = 6 mA and solving for Vqs will 
result in the following: 

V G s = -lifts = -(6mA)(680I2) = -4.08 V 
as shown in Fig. 7.27. 




Determining the Q-pointfor the network of Fig. 7.26. 



The device transfer curve is sketched using 

lD = I f = = 3 mA(at Vp/2) 

and V GS = 0.3 V P = 0.3(— 6 V) = -1.8 V (at I D = 7 DSS /2) 

The resulting solution is: 

V G s q s -2.6 V 

b. From Fig. 7.27, 

I Dq = 3.8 mA 

c. V D = V DD - lift a 

= 12 V - (3.8mA)(1.5kH) = 12 V - 5.7 V 
= 6.3 V 

d. V G = 0 V 

e. Vs = I d R s = (3.8 mA)(680 II) 

= 2.58 V 

f • Vds =V d ~ V s 

= 6.3 V - 2.58 V 

= 3.72 V 



7.6 SPECIAL CASE: V CSq = 0 V 



DEPLETION-TYPE 439 
MOSFETs 



A network of recurring practical value because of its relative simplicity is the configuration 
of Fig. 7.28. Note that direct connection of the gate and source terminals to ground resulting 
in V GS = 0 V. It specifies that for any dc condition the gate to source voltage must be zero 
volts. This will result in a vertical load line at V GSq — 0 V as shown in Fig. 7.29. 




FIG. 7.28 

Special case V G s Q = OV 
configuration. 




Finding the Q-point for the network of Fig. 7.28. 



Since the transfer curve of a JFET will cross the vertical axis at I DSS the drain current 
for the network is set at that level. 



Therefore, 

Applying Kirchhoff’ s voltage law: 

Vdd 




- h)Rn ~ Vps ~ 0 



and 

with 

and 



Vds ~ V dd IpRp 



Vp = Vps 
V s = OV 



( 7 . 29 ) 



( 7 . 30 ) 

( 7 . 31 ) 

( 7 . 32 ) 



7.7 DEPLETION-TYPE MOSFETs ^ 

The similarities in appearance between the transfer curves of JFETs and depletion-type 
MOSFETs permit a similar analysis of each in the dc domain. The primary difference 
between the two is the fact that depletion-type MOSFETs permit operating points with posi- 
tive values of V GS and levels of I D that exceed I DSS . In fact, for all the configurations dis- 
cussed thus far, the analysis is the same if the JFET is replaced by a depletion-type MOSFET. 

The only undefined part of the analysis is how to plot Shockley’s equation for positive 
values of V GS . How far into the region of positive values of V G g and values of I D greater than 
Ipss does the transfer curve have to extend? For most situations, this required range will be 
fairly well defined by the MOSFET parameters and the resulting bias line of the network. 
A few examples will reveal the effect of the change in device on the resulting analysis. 



EXAMPLE 7.6 For the ^-channel depletion-type MOSFET of Fig. 7.30, determine: 

a. Io Q and V GSq . 
b- V ns- 



440 FET BIASING 




FIG. 7.30 
Example 7.6. 



Solution: 



a. For the transfer characteristics, a plot point is defined by I D = Ipss/^ = 6 mA/4 = 1.5 mA 
and V GS = V P /2 = -3 V/2 = —1.5 V. Considering the level of V P and the fact that 
Shockley’s equation defines a curve that rises more rapidly as Vqs becomes more positive, 
a plot point will be defined at Vqs — + 1 V. Substituting into Shockley’s equation yields 



Id ~ Idss 



= 6 m A ^ 1 - 
= 10.67 mA 



i-iSsY 

VpJ 

+ 1 V 



-3 V 



= 6mA(l+-j = 6mA(1.778) 



The resulting transfer curve appears in Fig. 7.31. Proceeding as described for JFETs, 
we have 



Eq. (7.15): V G 
Eq. (7.16): V G5 



10MO(18 V) 

— = 1 5 V 

io mu + no mu 

V G - I d R s = 1.5 V - / d (750 a) 




FIG. 7.31 

Determining the Q-pointfor the network of Fig. 7.30. 



Setting Id = 0 mA results in 



DEPLETION-TYPE 441 
MOSFETs 



V G s= 1.5 V 



Setting V GS = 0 V yields 



/ =^ = 
D Rs 



1.5 V 
750 ii 



= 2 mA 



The plot points and resulting bias line appear in Fig. 7.31. The resulting operating 
point is given by 



I Dq = 3.1 mA 
Vgs q = -0.8 V 

b. Eq. (7.19): 

Vds = Vdd _ Id(Rd + Rs) 

= 18 V - (3.1 mA)(1.8 kll + 750 1 1) 

= 10.1 V 



EXAMPLE 7.7 Repeat Example 7.6 with R$ = 15011. 

Solution: 



a. The plot points are the same for the transfer curve as shown in Fig. 7.32. For the bias line, 
V GS =V g - I D Rs = 1-5 V - 7 d (150 fl) 

Setting Id = 0 mA results in 

V GS = 1.5 V 

Setting V GS = 0 V yields 



/ =^ = 
D R< 



1.5 V 
150 fl 



= 10 mA 




FIG. 7.32 

Example 7.7. 

The bias line is included on Fig. 7.32. Note in this case that the quiescent point results 
in a drain current that exceeds I D ss , with a positive value for Vqs • The result is 

I D q = 7 - 6 mA 

Vgs q = +0.35 V 

b. Eq. (7.19): 



Vds — Vdd ~ Id(Rd + Rs) 

= 18 V - (7.6mA)(1.8kll + 15011) 

= 3.18 V 



442 



FET BIASING 



EXAMPLE 7.8 Determine the following for the network of Fig. 7.33: 

a. I D(J and V GSq . 

b. V D . 




Solution: 



a. The self-bias configuration results in 



Vgs ~ IpRs 

as obtained for the JFET configuration, establishing the fact that Vqs must be less than 
0 V. There is therefore no requirement to plot the transfer curve for positive values of 
Vqs , although it was done on this occasion to complete the transfer characteristics. A 
plot point for the transfer characteristics for Vqs < 0 V is 



_ Ipss _ 8 mA 
4 “ 4 



2 mA 



and 




-8 V 
2 



-4 V 



and for Vqs > 0 V, since V P = —8 V, we will choose 
Vgs — +2V 

and I D = / a ,s(l - ^f) = 8 mA^l - 

= 12.5 mA 

The resulting transfer curve appears in Fig. 7.34. For the network bias line, at 
Vqs = 0 V, I D = 0 mA. Choosing Vqs = — 6 V gives 



Ip ~ 



Vgi 

Rs 



The resulting Q-point is given by 



-6 V 
2.4 kl2 



2.5 mA 



I Dq = 1.7 mA 
= -4.3 V 

b. V D = V DD - I[)Rp 

= 20 V - (1.7 mA)(6.2kD) 

= 9.46 V 



The example to follow employs a design that can also be applied to JFET transistors. At 
first impression it appears rather simplistic, but in fact it often causes some confusion 
when first analyzed due to the special point of operation. 




ENHANCEMENT-TYPE 443 
MOSFETs 




Determining the Q-pointfor the network of Fig. 7.33. 



EXAMPLE 7.9 Determine V DS for the network of Fig. 7.35. 

Solution: The direct connection between the gate and source terminals requires that 

V GS = 

Since Vqs is fixed at 0 V, the drain current must be I D ss (by definition). In other words, 

Vc.Sc, = OV 

and I Dq = 10 mA 

There is therefore no need to draw the transfer curve, and 

V D = V DD - IdR d = 20 V - (10mA)(1.5kD) 

= 20 V - 15 V 

= 5 V 



20 V 
1.5 kQ 




Idss~ mA 
V P = - 4 V 



? S 



FIG. 7.35 
Example 7.9. 



7.8 ENHANCEMENT-TYPE MOSFETs ^ 

The transfer characteristics of the enhancement-type MOSFET are quite different from 
those encountered for the JFET and depletion-type MOSFETs, resulting in a graphical 
solution quite different from those of the preceding sections. First and foremost, recall that 
for the ^-channel enhancement-type MOSFET, the drain current is zero for levels of gate- 
to-source voltage less than the threshold level VGS(Th> as shown in Fig. 7.36. For levels of 
Vgs greater than VGS(Th> the drain current is defined by 



I D — k(V GS ^GS(Th)) 2 



( 7 . 33 ) 



Since specification sheets typically provide the threshold voltage and a level of drain 
current (/£>( on )) an d its corresponding level of VGS(on> two points are defined immedi- 
ately as shown in Fig. 7.36. To complete the curve, the constant k of Eq. (7.33) must be 
determined from the specification sheet data by substituting into Eq. (7.33) and solving 
for k as follows: 

I D — k(V GS ~ V G s(Th)) 2 

b(on) = k(V GS ( on) ~ VgS( Th)) 2 




FET BIASING 




FIG. 7.36 

Transfer characteristics of an n-channel enhancement-type MOSFET. 



and 



k = 



*D(on) 



(VGS( on) ^GS(Th)) 



( 7 . 34 ) 



Once k is defined, other levels of I D can be determined for chosen values of V G $- Typically, 
a point between Vcs(Th) and VGS(on) and one just greater than Vcsion) will provide a sufficient 
number of points to plot Eq. (7.33) (note I Dl and I Dl on Fig. 7.36). 



Feedback Biasing Arrangement 

A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig. 7.37. 
The resistor R G brings a suitably large voltage to the gate to drive the MOSFET “on.” Since 
Iq = 0 mA, V Rg = 0 V and the dc equivalent network appears as shown in Fig. 7.38. 





FIG. 7.37 

Feedback biasing arrangement. 



FIG. 7.38 

DC equivalent of the 
network of Fig. 7.37. 



A direct connection now exists between drain and gate, resulting in 

Vd = V G 



and 



Vds ~ Vgs 



( 7 . 35 ) 



For the output circuit, 



Vds ~ Vdd IdRd 



which becomes the following after substituting Eq. (7.27): 



ENHANCEMENT-TYPE 445 
MOSFETs 



Vgs ~ V dd Id^d 



( 7 . 36 ) 



The result is an equation that relates I D to V GS , permitting the plot of both on the same set 
of axes. 

Since Eq. (7.36) is that of a straight line, the same procedure described earlier can be 
employed to determine the two points that will define the plot on the graph. Substituting 
I D = 0 mA into Eq. (7.36) gives 



VGS ~ Vdd \ I D =0 mA 



Substituting V GS = 0 V into Eq. (7.36), we have 



v DD 




Id = 1T 

k d 


> 

o 

II 



( 7 . 37 ) 



( 7 . 38 ) 



The plots defined by Eqs. (7.33) and (7.36) appear in Fig. 7.39 with the resulting operating 
point. 




Determining the Q-pointfor the network of Fig. 7.37. 



EXAMPLE 7.10 Determine I Dq and V DSq for the enhancement-type MOSFET of Fig. 7.40. 




446 



FET BIASING 



Solution: 



Plotting the Transfer Curve Two points are defined immediately as shown in Fig. 7.41. 
Solving for k , we obtain 



Eq. (7.34): 



k = 






D{ on) 



(^GSCon) - 

6 mA 



VGS( Th)) 

6 X 10 -3 



(8 V - 3 V) 2 25 

= 0.24 X 10“ 3 A/V 2 



A/V 2 




FIG. 7.41 

Plotting the transfer curve for the MOSFET of Fig. 7.40. 



For V GS = 6 V (between 3 and 8 V): 

I D = 0.24 X 10“ 3 (6 V - 3 V) 2 = 0.24 X 10“ 3 (9) 

= 2.16 mA 

as shown on Fig. 7.41. For V GS = 10 V (slightly greater than VGS(Th)X 
I D = 0.24 X 10“ 3 (10V - 3 V) 2 = 0.24 X 10“ 3 (49) 

= 11.76 mA 

as also appearing on Fig. 7.41. The four points are sufficient to plot the full curve for the 
range of interest as shown in Fig. 7.41. 

For the Network Bias Line 

Vgs = Vdd ~ h)R[) 

= 12 V - I D ( 2 kfl) 

Eq. (7.37): Vq$ = V DD = 12 V| /D=0mA 

V dd 12 V 

Eq. (7.38): I D - — - — - 6 mA| Vcs=0 v 

The resulting bias line appears in Fig. 7.42. 

At the operating point, 

I Dq = 2.75 mA 

Vgs, = 6.4 V 
Vds q = Vgs q = 6.4 V 



and 

with 




Voltage-Divider Biasing Arrangement 

A second popular biasing arrangement for the enhancement-type MOSFET appears in 
Fig. 7.43. The fact that I G = 0 mA results in the following equation for Vqq as derived 
from an application of the voltage-divider rule: 



R2 Vpp 

R\ + 7?2 



( 7 . 39 ) 



Applying Kirchhoff s voltage law around the indicated loop of Fig. 7.43 results in 

+v c - Vgs -V Rs = 0 

and V GS = V G - V Rs 



or 



Vgs ~ Vg ~ IpRs 



( 7 . 40 ) 



For the output section, 

and 

or 



^ + Vds + V Rd ~V dd = 0 

Vds ~ Vdd ~ Vr s ~ Vr d 

Vds = V DD - Ij)(Rs + Rd) 



( 7 . 41 ) 



Since the characteristics are a plot of I D versus V GS and Eq. (7.40) relates the same two 
variables, the two curves can be plotted on the same graph and a solution determined at their 
intersection. Once Id q and Vgs q are known, all the remaining quantities of the network such 
as V DS , V D , and can be determined. 



EXAMPLE 7.1 1 Determine I Dq , V GSq , and V DS for the network of Fig. 7.44. 

Solution: 



Network 



Eq. (7.39): 






RiVpp 

R\ 3” R 2 



(18MD)(40 V) 
22 MO + 18 MO 



18 V 



Eq. (7.40): V GS = V G - I D R S = 18 V - / D (0.82 kll) 



ENHANCEMENT-TYPE 447 
MOSFETS 



Vdd 




FIG. 7.43 

Voltage -divider biasing 
arrangement for an n-channel 
enhancement MOSFET. 



448 



FET BIASING 




FIG. 7.44 

Example 7.11. 



When I D = OmA, 

V GS = 18 V - (0mA)(0.82kI2) = 18 V 
as appearing on Fig. 7.45. When V GS = 0 V, 



Vgs 

0 

Id 



as appearing on Fig. 7.45. 



18 V - 7 D (0.82kft) 
18 V - / D (0.82kn) 
18 V 



0.82 m 



= 21.95 mA 




Determining the Q-pointfor the network of Example 7.11. 



Device 



^GS(Th) — 5 V, 
Eq. (7.34): k = 



Id ~ 



b{ on) = 3 mA with V G S(on) = 10 V 

Id( on) 

(^GS(on) “ ^GS(Th)f 

r = 0.12 X 10“ 3 A/V 2 

(10 V — 5 V) 2 

k(Vos ~ VastTh)) 2 
0.12 X 10“ 3 (V gs - 5) 2 



and 



COMBINATION 449 
NETWORKS 



which is plotted on the same graph (Fig. 7.45). From Fig. 7.45, 



I Dq = 6.7 mA 
y GSe = 12.5 V 

Eq. (7.41): V DS = V DD - I D (R S + R D ) 

= 40 V - (6.7 mA)(0.82 kO + 3.0 kH) 
= 40 V - 25.6 V 

= 14.4 V 



7.9 SUMMARY TABLE ^ 

Table 7.1 reviews the basic results and demonstrates the similarity in approach for a num- 
ber of FET configurations. It also reveals that the analysis of dc configurations for FETs is 
fairly straightforward. Once the transfer characteristics are established, the network bias 
line can be drawn and the g-point determined at the intersection of the device transfer 
characteristic and the network bias curve. The remaining analysis is simply an application 
of the basic laws of circuit analysis. 

7.10 COMBINATION NETWORKS ^ 

Now that the dc analysis of a variety of BJT and FET configurations is established, the 
opportunity to analyze networks with both types of devices presents itself. Fundamentally, 
the analysis simply requires that we first approach the device that will provide a terminal 
voltage or current level. The door is then usually open to calculating other quantities and 
concentrating on the remaining unknowns. These are usually particularly interesting prob- 
lems due to the challenge of finding the opening and then using the results of the past few 
sections and Chapter 4 to find the important quantities for each device. The equations and 
relationships used are simply those we have employed on more than one occasion — there 
is no need to develop any new methods of analysis. 



EXAMPLE 7.12 Determine the levels of V D and for the network of Fig. 7.46. 




FIG. 7.46 

Example 7.12. 




TABLE 7.1 

FET Bias Configurations 



Type 



Configuration 



Pertinent Equations 



Graphical Solution 



JFET 

Fixed-bias 




Vgs q — ~Vgg 
Vds = Vdd ~ b R s 



Q-point 



Van 0 V n 



JFET 

Self-bias 




Vgs ~ ~Ie>Rs 

Vds = Vdd ~ Id(Rd + Rs) 




2-point^S 



JFET 

Voltage-divider 

bias 




^G = 



R?V] 



2 V DD 



R\ T 
Vgs — Vg ~ IdRs 
Vds ~ Vdd ~ Id(Rd + Rs) 



2-point 

. 




JFET 

Common-gate 




V gs — V ss IdRs 

Vds = V DD + V S s ~ Id( r d + Rs) 





[ h 




r Fss 




Vss 


2-point^\ 






0 VssVt 



JFET 

(R d = o 




Vgs — ~IdRs 
Vd = Vdd 
Vs — IdRs 
Vds = V DD — I s Rs 



Id 

1 1 Fss 

■ V ~ i ' l 

2-pornt-— 

VpiVas |o 



JFET 

Special case 
(Vgs g = 0V) 



Van + 



b Q — bss 



2-point 



V GS = 0 V 



Depletion-type 
MOSFET 
Fixed-bias 
(and MESFETs) 




VgSq — + V GG 
Vds = V DD — I d R s 




2-point 



0 Vqg F gs 



Depletion-type 

MOSFET 

Voltage-divider 

bias 

(and MESFETs) 




= 



RiVdd 



R\ f R2 
V G s = V G I s Rs 
Vds = Vdd ~ Id(Rd + Rs) 



V G\ 


Id 




\ 2-poi' 11 


Idss j 




v p 


0 v G v c 



Enhancement 
type MOSFET 
Feedback 
configuration 
(and MESFETs) 



R c \ r d 



n 



V G s — V DS 
Vgs = V DD — IdRd 




^GS(Th) v V DD V GS 
V GS( on) 



Enhancement 
type MOSFET 
Voltage-divider 
bias 

(and MESFETs) 




t j _ R 2 V DD 
V r: — 

u R { + R 2 

Vgs = Vg ~ IdRs 




GS{ Th) v G v GS 



450 



Solution: From experience we now realize that Vqs is typically an important quantity to 
determine or write an equation for when analyzing JFET networks. Since Vqs is a level for 
which an immediate solution is not obvious, let us turn our attention to the transistor con- 
figuration. The voltage-divider configuration is one where the approximate technique can 
be applied (f3R E = 180 X 1.6 kll = 288 kll > 10 R 2 = 240 kll), permitting a determi- 
nation of V B using the voltage-divider rule on the input circuit. 

For V B , 



24 kI2(16 V) 
82 kO + 24 m 



3.62 V 



Using the fact that V BE = 0.7 V results in 



and 



V £ = V b - V be = 3.62 V 
= 2.92 V 

_ Vre _ Ya — ^-92 V _ 
R e ~ R e ~ 1.6 kU ” 



- 0.7 V 



1.825 mA 



with I c = I E = 1.825 mA 

Continuing, we find for this configuration that 



Id ~ is ~ ic 

and V D = 16 V - 7 D (2.7kft) 

= 16 V - (1.825 mA)(2.7 kfl) = 16 V - 4.93 V 

= 11.07 V 



The question of how to determine Vq is not as obvious. Both V GE and V DS are unknown 
quantities, preventing us from establishing a link between V D and V c or from V E to V D . A 
more careful examination of Fig. 7.46 reveals that Vq is linked to V B by Vqs (assuming that 
V R(} = 0 V). Since we know V B if we can find Vqs , Vq can be determined from 

V C =Vb~ Vgs 

The question then arises as to how to find the level of Vqs q from the quiescent value of 
The two are related by Shockley’s equation: 

( V GS Q \ 2 

I Dq ~ /d,s,s( 1 - — J 

and Vq Sq could be found mathematically by solving for V GSq and substituting numerical 
values. However, let us turn to the graphical approach and simply work in the reverse 
order employed in the preceding sections. The JFET transfer characteristics are first 
sketched as shown in Fig. 7.47. The level of I Dq = I Sq = Iq q = I Eq is then established by 
a horizontal line as shown in the same figure. V GSq is then determined by dropping a line 
down from the operating point to the horizontal axis, resulting in 

V GSe = -3.7 V 



COMBINATION 451 
NETWORKS 




(mA) 

Ass 



I D = 1.825 mA 

Q 



FIG. 7.47 

Determining the Q-pointfor the network of Fig. 7.46. 



452 FET BIASING 



O 16 V 




FIG. 7.48 
Example 7.13. 




FIG. 7.50 

Self-bias configuration 
to be designed. 



The level of V c is given by 

Vc=Vb- Vgs q = 3.62 V - (-3.7 V) 

= 7.32 V 



EXAMPLE 7.13 Determine V D for the network of Fig. 7.48. 

Solution: In this case, there is no obvious path for determining a voltage or current level for 
the transistor configuration. However, turning to the self-biased JFET, we can derive an equa- 
tion for V GS and determine the resulting quiescent point using graphical techniques. That is, 

V G s = -IdRs = -/z>(2.4kn) 

resulting in the self-bias line appearing in Fig. 7.49, which establishes a quiescent point at 

= -2.4 V 
I Dq = 1 rnA 




FIG. 7.49 

Determining the Q-pointfor the network of Fig. 7.48. 



For the transistor, 



Ie = Ic ~ Id ~ 1 



Ic 1 mA 

and I B = — = = 12.5 llA 

$ 80 

V B = 16 V — 7#(470 kfl) 

= 16 V - (12.5/xA)(470kn) = 16 V - 5.88 V 
= 10.12V 

and V E = V D = V B - V BE 

= 10.12 V - 0.7 V 

= 9.42 V 



7.11 DESIGN ^ 

The design process is a function of the area of application, level of amplification desired, 
signal strength, and operating conditions. The first step is normally to establish the proper dc 
levels of operation. 

For example, if the levels of Vd and I D are specified for the network of Fig. 7.50, the 
level of Vqs q can be determined from a plot of the transfer curve and R s can then be de- 
termined from Vqs = —Id^s- If Vdd I s specified, the level of R D can then be calculated 
from R d = ( V DD — V D )/I D . Of course, the values of R s and R D may not be standard 
commercial values, requiring that the nearest commercial values be employed. However, 
with the tolerance (range of values) normally specified for the parameters of a network, 




DESIGN 453 



the slight variation due to the choice of standard values will seldom cause a real concern 
in the design process. 

The above is only one possibility for the design phase involving the network of Fig. 7.50. 
It is possible that only V DD and R D are specified together with the level of V DS . The device to 
be employed may have to be specified along with the level of R s . It appears logical that the 
device chosen should have a maximum V DS greater than the specified value by a safe margin. 

In general, it is good design practice for linear amplifiers to choose operating points 
that do not crowd the saturation level (loss) or cutoff (Vp) regions. Levels of V GSq close to 
Vpj 2 or levels of I Dq near loss / 2 are certainly reasonable starting points in the design. Of 
course, in every design procedure the maximum levels of I D and V DS as appearing on the 
specification sheet must not be exceeded. 

The examples to follow have a design or synthesis orientation in that specific levels are 
provided and network parameters such as R D , R s , V DD , and so on, must be determined. In 
any case, the approach is in many ways the opposite of that described in previous sections. 
In some cases, it is just a matter of applying Ohm’ s law in its appropriate form. In particular, 
if resistive levels are requested, the result is often obtained simply by applying Ohm’ s law 
in the following form: 



^unknown T 



where V R and I R are often parameters that can be found directly from the specified voltage 
and current levels. 



EXAMPLE 7. 1 4 For the network of Fig. 7.5 1 , the levels of V D and I D are specified. Deter- 
mine the required values of R D and R$. What are the closest standard commercial values? 




FIG. 7.51 
Example 7.14. 



Solution: As defined by Eq. (7.42), 
R d = 



Vr d Vdd 



h 



Do 



'D n 



and 



20 V - 12 V 
2.5 mA 



2.5 mA 



= 3.2 ka 



Plotting the transfer curve in Fig. 7.52 and drawing a horizontal line at I D q = 

—Id^s establishes the level of R s : 
-(-IV) 



results in V GSq = — 1 V, and applying V GS 



Rs 



-(Vasg) 



2.5 mA 



0.4 ka 



The nearest standard commercial values are 



R d = 3.2 ka => 3.3 ka 
R s = 0.4 kD 0.39 ka 



2.5 mA 




FIG. 7.52 

Determining Vgs q far the network 
of Fig. 7.51. 




ITT 



454 FET BIASING 




^GS(on) 
A>(on) = 
V GS( Th) 



FIG. 7.54 

Example 7.16. 



EXAMPLE 7.1 5 For the voltage-divider bias configuration of Fig. 7.53, if V D = 12 V and 
Vgs q — — 2 V, determine the value of R$. 




Example 7.15. 



Solution: 



with 



The level of Vq is determined as follows: 



V G 

Id 



47 kH(16V) 
47 kll + 91 kO 



Vpp ~ Vp 
Rp 

16 V - 12 V 

i.8 m 



2.22 mA 



The equation for Vqs is then written and the known values substituted: 

Vgs = Vq - I d R s 
-2 V = 5.44 V - (2.22 mA)R s 
-7.44 V = -(2.22 mA )R S 



and 



7.44 V 
2.22 mA 



3.35 ka 



The nearest standard commercial value is 3.3 kll. 



= 6 V 
4 mA 
= 3 V 



EXAMPLE 7.16 The levels of V DS and I D are specified as V DS — \Vpp and = //)( on ) 
for the network of Fig. 7.54. Determine the levels of V DD and R D . 

Solution: Given I D = Io(on) — 4 mA and V GS = VGS(on) — 6 V, for this configuration, 

Vps — ^GS — \VpP 

and 6 V = 

so that Vpp = 12 V 

Vpp ~ ^ps _ ^pp ~ j^PP _ l^pp 

Ip{ on) ^P(on) ^P(on) 

= -P~= 1.5kft 

4 mA 

which is a standard commercial value. 



Applying Eq. (7.42) yields 



Rr 



V Rn 



L P 



and 



7.12 TROUBLESHOOTING 



p-CHANNEL FETs 455 



How often has a network been carefully constructed only to find that when the power is 
applied, the response is totally unexpected and fails to match the theoretical calculations? 
What is the next step? Is it a bad connection? A misreading of the color code for a resistive 
element? An error in the construction process? The range of possibilities seems vast and 
often frustrating. The troubleshooting process first described in the analysis of BJT transis- 
tor configurations should narrow down the list of possibilities and isolate the problem area 
following a definite plan of attack. In general, the process begins with a rechecking of the 
network construction and the terminal connections. This is usually followed by the check- 
ing of voltage levels between specific terminals and ground or between terminals of the 
network. Seldom are current levels measured since such maneuvers require disturbing the 
network structure to insert the meter. Of course, once the voltage levels are obtained, cur- t 
rent levels can be calculated using Ohm’s law. In any case, some idea of the expected volt- 
age or current level must be known for the measurement to have any importance. In total, 
therefore, the troubleshooting process can begin with some hope of success only if the 
basic operation of the network is understood along with some expected levels of voltage or 
current. For the ^-channel JFET amplifier, it is clearly understood that the quiescent value 
of VgSq is limited to 0 V or a negative voltage. For the network of Fig. 7.55, Vgs q is limited 
to negative values in the range 0 V to V P . If a meter is hooked up as shown in Fig. 7.55, 
with the positive lead (normally red) to the gate and the negative lead (usually black) to the 
source, the resulting reading should have a negative sign and a magnitude of a few volts. 
Any other response should be considered suspicious and needs to be investigated. 

The level of V D $ is typically between 25% and 75% of V DD . A reading of 0 V for V DS 
clearly indicates that either the output circuit has an “open” or the JFET is internally short- 
circuited between drain and source. If V D is V DD volts, there is obviously no drop across R D , 
due to the lack of current through R D , and the connections should be checked for continuity. 

If the level of V D s seems inappropriate, the continuity of the output circuit can easily be 
checked by grounding the negative lead of the voltmeter and measuring the voltage levels 
from V DD to ground using the positive lead. If V D = Vdd , the current through R D may be 
zero, but there is continuity between Vd and Vdd- If Vs = Vdd> the device is not open be- 
tween drain and source, but it is also not “on.” The continuity through to Vs is confirmed, 
however. In this case, it is possible that there is a poor ground connection between R s and 
ground that may not be obvious. The internal connection between the wire of the lead and 
the terminal connector may have separated. Other possibilities also exist, such as a shorted 
device from drain to source, but the troubleshooter will simply have to narrow down the 
possible causes for the malfunction. 

The continuity of a network can also be checked simply by measuring the voltage across 
any resistor of the network (except for R G in the JFET configuration). An indication of 0 V im- 
mediately reveals the lack of current through the element due to an open circuit in the network. 

The most sensitive element in the BJT and JFET configurations is the amplifier itself. 

The application of excessive voltage during the construction or testing phase or the use 
of incorrect resistor values resulting in high current levels can destroy the device. If you 
question the condition of the amplifier, the best test for the FET is the curve tracer since 
it not only reveals whether the device is operable, but also its range of current and voltage 
levels. Some testers may reveal that the device is still fundamentally sound but do not reveal 
whether its range of operation has been severely reduced. 

The development of good troubleshooting techniques comes primarily from experience 
and a level of confidence in what to expect and why. There are, of course, times when the 
reasons for a strange response seem to disappear mysteriously when you check a network. 

In such cases, it is best not to breathe a sigh of relief and continue with the construction. 

The cause for such a sensitive “make or break” situation should be found and corrected, or 
it may reoccur at the most inopportune moment. 




FIG. 7.55 

Checking the dc operation of the 
JFET self-bias configuration. 



7.13 p-CHANNEL FETs 



The analysis thus far has been limited solely to ^-channel FETs. For /7-channel FETs, a 
mirror image of the transfer curves is employed, and the defined current directions are 
reversed as shown in Fig. 7.56 for the various types of FETs. 




456 



FET BIASING 




(b) 




FIG. 7.56 

p-Channel configurations: (a) JFET; (b) depletion-type MOSFET; 
(c) enhancement-type MOSFET. 



Note for each configuration of Fig. 7.56 that each supply voltage is now a negative volt- 
age drawing current in the indicated direction. In particular, note that the double- sub script 
notation for voltages continues as defined for the ^-channel device: V G $, V DS , and so on. In 
this case, however, V GS is positive (positive or negative for the depletion-type MOSFET) 
and V DS negative. 

Due to the similarities between the analysis of ^-channel and /^-channel devices, one can 
assume an ^-channel device and reverse the supply voltage and perform the entire analysis. 
When the results are obtained, the magnitude of each quantity will be correct, although the 
current direction and voltage polarities will have to be reversed. However, the next example 



will demonstrate that with the experience gained through the analysis of ^-channel devices, 
the analysis of /7-channel devices is quite straightforward. 



p-CHANNEL FETs 457 



EXAMPLE 7.17 Determine I Dq , V GSq , and V DS for the p-channel JFET of Fig. 7.57. 




FIG. 7.57 
Example 7.17. 



Solution: We have 

20 kI2(— 20 V) 

Vg ~ 20 kfi + 68 kn ~~ ~ 4 

Applying Kirchhoff ’ s voltage law gives 

V G ~ V G s + lefts = 0 

and V GS — V G + I D R S 

Choosing Id = 0 mA yields 

V g = -4.55 V 

as appearing in Fig. 7.58. 




FIG. 7.58 

Determining the Q-pointfor the JFET configuration of Fig. 7.57. 



Choosing V GS = 0 V, we obtain 



h) ~ ~ 



Vg 

Rs 



-4.55 V 

1.8 kn 



2.53 mA 



as also appearing in Fig. 7.58. 




458 



FET BIASING 



The resulting quiescent point from Fig. 7.58 is given by 

I Dq = 3.4 mA 
= 1.4 V 

For V DS , Kirchhoff’ s voltage law results in 

—lifts + Vds ~ hfti) + V dd — 0 
and V DS = ~V DD + Id(Rd + Rs) 

= -20 V + (3.4mA)(2.7kI2 + 1.8 kO) 
= -20 V + 15.3 V 
= -4.7 V 



7.14 UNIVERSAL JFET BIAS CURVE ^ 

Since the dc solution of a FET configuration requires drawing the transfer curve for each 
analysis, a universal curve was developed that can be used for any level of I DS s and V P . 
The universal curve for an n-channel JFET or depletion-type MOSFET (for negative val- 
ues of VgSq) is provided in Fig. 7.59. Note that the horizontal axis is not that of Vqs but of 
a normalized level defined by Vqs/ \ V P \ , the \ V P \ indicating that only the magnitude of V P 
is to be employed, not its sign. For the vertical axis, the scale is also a normalized level of 
Id/Idss- The result is that when I D = I DSS , the ratio is 1, and when V GS = V P , the ratio 
V G s/|Vf.| is — 1. Note also that the scale for Id/Idss is on the left rather than on the right as 
encountered for I D in past exercises. The additional two scales on the right need an intro- 
duction. The vertical scale labeled m can in itself be used to find the solution to fixed-bias 
configurations. The other scale, labeled Af, is employed along with the m scale to find the 




\V P \ 



FIG. 7.59 

Universal JFET bias curve. 



solution to voltage-divider configurations. The scaling for m and M come from a mathe- 
matical development involving the network equations and normalized scaling just intro- 
duced. The description to follow will not concentrate on why the m scale extends from 0 to 
5 at Vqs/ | Vp\ = —0.2 and the M scale ranges from 0 to 1 at V GS / \ V P \ =0, but rather on 
how to use the resulting scales to obtain a solution for the configurations. The equations 
for m and M are the following, with V G as defined by Eq. (7.15): 



|Vp| 

Idss r s 



( 7 . 43 ) 



M = m X 



Vg_ 

\V P \ 



( 7 . 44 ) 



with 



V G = 



RtYdd 



R\ + R 2 

Keep in mind that the beauty of this approach is the elimination of the need to sketch the 
transfer curve for each analysis, that the superposition of the bias line is a great deal easier, 
and that the calculations are fewer. The use of the m and M axes is best described by 
examples employing the scales. Once the procedure is clearly understood, the analysis can 
be quite rapid, with a good measure of accuracy. 



UNIVERSAL JFET 459 
BIAS CURVE 



EXAMPLE 7.1 8 Determine the quiescent values of I D and Vq$ for the network of Fig. 7.60. 




FIG. 7.60 
Example 7.18. 



Solution: Calculating the value of m, we obtain 

I v P \ 1—3 v| 

m = ' = = 0 31 

bss R s (6mA)(1.6kft) 

The self-bias line defined by R s is plotted by drawing a straight line from the origin through 
a point defined by m = 0.31, as shown in Fig. 7.61. 

The resulting Q-point: 



L D 



= 0.18 



and 






= -0.575 



Idss I Vp | 

The quiescent values of I D and V G s can then be determined as follows: 



I Dq = 0.18 I DSS = 0.18(6 mA) = 1.08 mA 
= -0.575 1 V P \ = -0.575(3 V) = -1.73 V 



and 




460 



FET BIASING 



\Vp\ 



Ip 

Ipss 



M- m x 



IVol 




FIG. 7.61 

Universal curve for Examples 7.18 and 7.19. 



EXAMPLE 7.1 9 Determine the quiescent values of I D and Vqs for the network of Fig. 7.62. 




FIG. 7.62 
Example 7.19. 



Solution: Calculating m gives 

|Vp| 

m = 

bss R s 



I — 6 V | 

(8mA)(1.2kfl) 



0.625 



Determining Vq yields 



R 2 V dd _ (220 kD)(18 V) 

R x + R 2 ~ 910 kD + 220 kD 



Finding M, we have 

V r /3 5V\ 

M = m X = 0.625 = 0.365 

Ivpl V6vy 

Now that m and M are known, the bias line can be drawn on Fig. 7.61. In particular, note 
that even though the levels of I D $s and V P are different for the two networks, the same 
universal curve can be employed. First find M on the M axis as shown in Fig. 7.61. Then 
draw a horizontal line over to the m axis and, at the point of intersection, add the magni- 
tude of m as shown in the figure. Using the resulting point on the m axis and the M inter- 
section, draw the straight line to intersect with the transfer curve and define the Q-point. 
That is, 



and 

with 



= 0.53 



and 






= -0.26 



I DSS 



I D = 0.53 I DSS = 0.53(8 mA) = 4.24 mA 






-0.26 1 V P \ = -0.26(6 V) = -1.56 V 



PRACTICAL 461 
APPLICATIONS 



7.1 5 PRACTICAL APPLICATIONS ^ 

The applications described here take full advantage of the high input impedance of field- 
effect transistors, the isolation that exists between the gate and drain circuits, and the linear 
region of JFET characteristics that permit approximating the device by a resistive element 
between the drain and source terminals. 



Voltage-Controlled Resistor (Noninverting Amplifier) 



One of the most common applications of the JFET is as a variable resistor whose resis- 
tance value is controlled by the applied dc voltage at the gate terminal. In Fig. 7.63a, the 
linear region of a JFET transistor has been clearly indicated. Note that in this region 
the various curves all start at the origin and follow a fairly straight path as the drain-to- 
source voltage and drain current increase. Recall from your basic dc courses that the plot 
of a fixed resistor is nothing more than a straight line with its origin at the intersection 
of the axes. 

In Fig. 7.63b, the linear region has been expanded to a maximum drain-to- source voltage 
of about 0.5 V. Note that even though the curves do have some curvature to them, they can 
easily be approximated by fairly straight lines, all having their origin at the intersection of 
the axes and a slope determined by the gate-to- source dc voltage. Recall from earlier dis- 
cussions that for an I-V plot where the current is the vertical axis and the voltage the 
horizontal axis, the steeper the slope, the less is the resistance; and the more horizontal 
the curve, the greater is the resistance. The result is that a vertical line has 0 D resistance 
and a horizontal line has infinite resistance. At V G s = 0 V, the slope is the steepest and 
the resistance the least. As the gate-to- source voltage becomes increasingly negative, the 
slope decreases until it is almost horizontal near the pinch-off voltage. 

It is important to remember that this linear region is limited to levels of V D s that are 
relatively small compared to the pinch-off voltage. In general, the linear region of a JFET 
is defined by V DS « V DSma and | V GS | « | V P \ . 

Using Ohm’s law, let us calculate the resistance associated with each curve of Fig. 7.63b 
using the current that results at a drain-to- source voltage of 0.4 V. 



V G s — 0 V: R ds 

V GS — —0.5 V: R ds 
V G s - _ 1V: R D s 



Vds 

Ids 

Vds 

Ids 

Vds 

Ids 



0.4 V 
4mA 
0.4 V 

2.5 mA 
0.4 V 

1.5 mA 



= 100 a 



160 a 



= 267 a 




FIG. 7.63 

JFET characteristics: (a) defining the linear region; (b) expanding the linear region. 



Vgs = — 1-5 V: R ds 
Vgs — - 2V: R ds 



Vps 

Ids 

Vps 

Ids 



0.4 V 
0.9 mA 
0.4 V 
0.5 mA 



444 0 

800 a 



Vgs ~ “2.5 V: R DS — 



Vps 



*DS 



0.4 V 
0.12 mA 



= 3.3 ka 



In particular, note how the drain-to-source resistance increases as the gate-to-source 
voltage approaches the pinch-off value. 

The results just obtained can be verified by Eq. (6.1) using the pinch-off voltage of —3 V 
and R 0 = 100 a at V G s — 0 V. We have 



R PS 

Vgs = — 0.5 V: R ds 
V G s ~ “IV: Rds 

Vqs — “1-5 V: R DS 



Rn 



(-W ( 



_ loo a 
2 ~ \ v GS 



yp 

too a 



_ -0.5 V 
" -3 V 

ioo a 



i - 



-IV 
-3 V 

ioo a 



i - 



-1.5 V 



-3 V y 

= 144 a (versus 160 a above) 



= 225 a (versus 267 a above) 



= 400 a (versus 444 a above) 



462 



-3 V 



ioo n 



2 



PRACTICAL 463 
APPLICATIONS 



V G s — “2 V: R ds 



V GS — — 2.5 V: R ds 




—2 V 
-3 V 



100H 



1 - 



-2.5 V 
-3 V 



= 900 II (versus 800 II above) 



2 — 3.6 kll (versus 3.3 kll above) 



Although the results are not an exact match, for most applications Equation (6.1) provides 
an excellent approximation to the actual resistance level for R DS . 

Keep in mind that the possible levels of Vqs between 0 V and pinch-off are infinite, 
resulting in the full range of resistor values between 100 12 and 3.3 kll. In general, therefore, 
the above discussion is summarized by Fig. 7.64a. For Vqs — 0 V, the equivalence of Fig. 
7.64b would result; for Vqs — frl.5 V, the equivalence of Fig. 7.64c; and so on. 





for V DS « V DSmax 
V GS « Vp 



(a) 



G 

o 



9 D 




9 D 


r ds > ioo n 


G 

° Rds 


>4oo n 


ov | 


1.5 V 




A 5 




As 


> 

o 

II 

» 8 




= -1.5 V 


(b) 




(c) 



FIG. 7.64 

JFET voltage-controlled drain resistance: (a) general equivalence; 
(b) with V GS = 0 V; (c) with V GS = -1.5 V. 



Fet us now investigate the use of this voltage-controlled drain resistance in the nonin- 
verting amplifier of Fig. 7.65a — noninverting indicates that the input and output signals 
are in phase. The op-amp of Fig. 7.65a is discussed in detail in Chapter 10, and the equation 
for the gain is derived in Section 10.4. 

If Rf = R\, the resulting gain is 2, as shown by the in-phase sinusoidal signals of Fig. 
7.65a. In Fig. 7.65b, the variable resistor has been replaced by an n-channel JFET. If 
Rf = 3.3 kll and the transistor of Fig. 7.63 were employed, the gain could extend from 
1 + 3.3 kH/3.3 kll = 2 to 1 + 3.3kH/100H = 34 for V G g varying from —2.5 V to 
0 V, respectively. In general, therefore, the gain of the amplifier can be set at any value 
between 2 and 34 by simply controlling the applied dc biasing voltage. The effect of this 
type of control can be extended to an extensive variety of applications. For instance, if the 
battery voltage of a radio should start to drop due to extended use, the dc level at the gate of 
the controlling JFET will drop, and the level of R D $ will decrease also. A drop in R DS will 
result in an increase in gain for the same value of Rp and the output volume of the radio can 
be maintained. A number of oscillators (networks designed to generate sinusoidal signals 
of specific frequencies) have a resistance factor in the equation for the frequency generated. 
If the frequency generated should start to drift, a feedback network can be designed that 
changes the dc level at the gate of a JFET and therefore its drain resistance. If that drain 
resistance is part of the resistance factor in the frequency equation, the frequency generated 
can be stabilized or maintained. 



464 



FET BIASING 




(b) 




FIG. 7.65 

(a) Noninverting op-amp configuration; (b) using the voltage-controlled drain-to-source resistance 
of a JFET in the noninverting amplifier. 



One of the most important factors that affect the stability of a system is tempera- 
ture variation. As a system heats up, the usual tendency is for the gain to increase, which in 
turn will usually cause additional heating and may eventually result in a condition referred 
to as “thermal runaway.” Through proper design, a thermistor can be introduced that will 
affect the biasing level of a voltage-controlled variable JFET resistor. As the resistance 
of the thermistor drops with increase in heat, the biasing control of the JFET can be such 
that the drain resistance changes in the amplifier design to reduce the gain — establishing 
a balancing effect. 

Before leaving the subject of thermal problems, note that some design specifications 
(often military type) require that systems that are overly sensitive to temperature variations 
be placed in a “chamber” or “oven” to establish a constant heat level. For instance, a 1-W 
resistor may be placed in an enclosed area with an oscillator network to establish a constant 
ambient heat level in the region. The design then centers on this heat level, which would be 
so high compared to the heat normally generated by the components that the variations in 
temperature levels of the elements could be ignored and a steady output frequency assured. 

Other areas of application include any form of volume control, musical effects, meters, 
attenuators, filters, stability designs, and so on. One general advantage of this type of sta- 
bility is that it avoids the need for expensive regulators (Chapter 15) in the overall design, 
although it should be understood that the purpose of this type of control mechanism is to 
“fine-tune” rather than to provide the primary source of stability. 



For the noninverting amplifier, one of the most important advantages associated with 
using a JFET for control is the fact that it is dc rather than ac control. For most systems, 
dc control not only results in a reduced chance of adding unwanted noise to the system, but 
also lends itself well to remote control. For example, in Fig. 7.66a, a remote control panel 
controls the amplifier gain for the speaker by an ac line connected to the variable resistor. 



PRACTICAL 465 
APPLICATIONS 





(b) 




FIG. 7.66 

Demonstrating the benefits of dc control: system with (a) ac control; (b) dc control ; 

(c) RF noise pickup. 





466 FET BIASING 



The long line from the amplifier can easily pick up noise from the surrounding air 
as generated by fluorescent lights, local radio stations, operating equipment (even 
computers), motors, generators, and so on. The result may be a 2-mV signal on the line 
with a 1-mV noise level — a terrible signal-to-noise ratio, which would only contribute to 
further deterioration of the signal coming in from the microphone due to the loop gain of 
the amplifier. In Fig. 7.66b, a dc line controls the gate voltage of the JFET and the variable 
resistance of the noninverting amplifier. Even though the dc line voltage on the line may 
be only — 2 V, a ripple of 1 mV picked up by the long line will result in a very large signal- 
to-noise ratio, which could essentially be ignored in the distortion process. In other words, 
the noise on the dc line would simply move the dc operating point slightly on the device 
characteristics and would have almost no effect on the resulting drain resistance — isolation 
between the noise on the line and the amplifier response would be almost ideal. 

Even though Figures 7.66a and 7.66b have a relatively long control line, the control line 
may only be 6" long, as shown in the control panel of Fig. 7.66c, where all the elements of 
the amplifier ar